JP3831040B2 - Semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including a non-volatile memory and a central processing unit. For example, a single-chip microcomputer incorporating a flash memory and a central processing unit, a data processing unit, or an external operation power source of a microprocessor is unified. It relates to a technology that is effective when applied.
[0002]
[Prior art]
Examples of microcomputers with built-in flash memory include H8 / 538F, H8 / 3048, and H8 / 3434F manufactured by Hitachi, Ltd.
[0003]
A memory cell transistor of a flash memory has a floating gate, a control gate, a source, and a drain, and holds binary information according to the state of charge injection into the floating gate. For example, when charge is injected into the floating gate, the threshold voltage of the memory cell increases, and the threshold voltage viewed from the control gate is increased, so that no current flows through the memory cell. Further, by discharging charges from the floating gate and lowering the threshold voltage viewed from the control gate, a current flows through the memory cell. Although not particularly limited, an operation for raising the threshold voltage of the memory cell higher than the word line selection level at the time of reading is an erase operation (the data selected by the logic value is “1”: erased state). The operation of lowering the threshold voltage below the word line selection level at the time of reading is referred to as a write operation (the data selected thereby is a logical value “0”: write state). Note that the erased state and the written state of the data stored in the memory cell may be defined oppositely to the above.
[0004]
In erasing and writing to the memory cell transistor, since the floating gate must be placed in a high electric field, a high voltage for erasing and writing that is higher than a general power supply voltage such as 3 V or 5 V is required. . Such a high voltage has been conventionally supplied as an external power source.
[0005]
[Problems to be solved by the invention]
However, when such a high voltage is obtained from an external power supply, a circuit for generating the high voltage must be mounted on the circuit board on which the microcomputer is mounted. There is a problem that special consideration is required for the design and the usability is poor.
[0006]
The present inventor has studied to enable a microcomputer incorporating a flash memory to operate with a single power source such as 3V or 5V. That is, the external single power supply is boosted internally to generate a high voltage for writing and erasing.
[0007]
At this time, the operating power supply of the microcomputer is lowered to 3V due to the demand for low power consumption, and there is a system that uses 3V, and there is a system that uses a single 5V power supply. Whether the power supply voltage is 3V or 5V is determined by the specifications of the system to which the microcomputer is applied. For this reason, it is a good idea for a semiconductor manufacturer to design a microcomputer so that it can operate with a relatively wide range of power supplies such as 3V to 5V.
[0008]
In consideration of this, the following points were made clear by the inventors' investigation. That is, the charge injection method for the flash memory includes a channel injection method in which charges are injected into the floating gate by flowing a relatively large current through the channel of the memory cell transistor to generate hot electrons in the vicinity of the drain, and a floating gate and drain. There is a tunnel current system in which a predetermined electric field strength is applied between them to flow a tunnel current through a relatively thin tunnel oxide film near the drain to inject charges. The former requires a relatively large current and is not suitable for internal boosting, but the latter can be stably built-in flash over a relatively wide external power supply voltage range including low-voltage operation by simply performing internal boosting. It has been clarified that memory writing and erasing cannot be realized.
[0009]
An object of the present invention is to stably operate in a relatively wide external power supply voltage range including low voltage operation in a semiconductor integrated circuit such as a microcomputer incorporating a nonvolatile memory such as a flash memory that can be electrically written and erased. It is to enable writing and erasing of the built-in nonvolatile memory.
[0010]
Another object of the present invention is to improve the usability of a semiconductor integrated circuit such as a microcomputer incorporating a nonvolatile memory such as a flash memory which can be electrically written and erased.
[0011]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0012]
[Means for Solving the Problems]
The outline of typical ones of the inventions disclosed in the present application will be briefly described as follows.
[0013]
That is, a semiconductor integrated circuit such as a microcomputer includes a non-volatile memory such as an electrically erasable and writable flash memory, and a central processing unit capable of accessing the non-volatile memory on a single semiconductor substrate. A single power supply voltage supplied to the power supply terminal is used as an operating power supply. The nonvolatile memory includes a voltage clamping unit that clamps an output voltage to a first voltage having a level lower than the single power supply voltage using a reference voltage having a small power supply voltage dependency, and an output of the voltage clamping unit Boosting means capable of boosting the voltage to a positive high voltage and a negative high voltage, and a plurality of nonvolatile memory cells that are erased and written using the positive and negative high voltages output from the boosting means. Comprising.
[0014]
According to this semiconductor integrated circuit, the voltage clamping means forms a voltage having a small power supply voltage dependency, and the voltage level is supplied from the outside within an allowable range of the allowable operating power supply voltage of the semiconductor integrated circuit. Since it is clamped to a voltage lower than the single power supply voltage, the boosted voltage generated by the boosting means operated with this clamp voltage, that is, the write and erase voltages do not depend on the external power supply voltage. Therefore, the built-in nonvolatile memory can be erased and written in a relatively wide external power supply voltage range including low voltage operation. In addition, since this can be achieved with a single external power supply voltage, the usability of the semiconductor integrated circuit incorporating the nonvolatile memory is improved.
[0015]
In order to improve the boosting operation efficiency, when the boosted voltage reaches a predetermined level, the substrate bias voltage common to the MOS transistors that perform the charge pump is changed. For example, a p-channel MOS transistor and a capacitor are coupled to a boosting node that forms a negative high voltage, and has a charge pump circuit that generates a negative high voltage by a charge pump action by them, which is common to the MOS transistors. There is further provided switching means for switching the substrate bias voltage from the output voltage of the voltage clamping means to a second voltage having a level lower than that. The second voltage is a voltage having a higher level than the boosted voltage at the time of switching. In this example, when the substrate bias voltage is lowered, the threshold voltage of the MOS transistor is reduced due to the so-called substrate bias effect, and this facilitates the movement of charges through the MOS transistor that performs charge pumping. This improves the boosting operation efficiency and shortens the time required to obtain a specified boosted voltage.
[0016]
The boosted voltage during boosting by the charge pump swings up and down in synchronization with the switching operation of the charge pump MOS transistor. In order to prevent the substrate bias voltage from oscillating due to the influence of the ripple component, the switching means causes the substrate bias voltage to become the second voltage even if the boosted voltage fluctuates up and down after the substrate bias voltage is switched. Provide hysteresis characteristics to maintain. Such a hysteresis characteristic can be achieved by using a hysteresis comparator or holding the state by a circuit such as an SR flip-flop.
[0017]
When operating a plurality of charge pump circuits with the same power supply, it is desirable to shift the phase of operation of each charge pump circuit in order to reduce the instantaneous voltage drop of the power supply. For example, the boosting means includes a negative boosting charge pump circuit that generates a negative high voltage by a charge pumping action of a MOS transistor coupled to a boosting node that forms a negative high voltage and a capacitor, and a positive boosting voltage. When having a positive boosting charge pump circuit that generates a positive high voltage by a charge pumping action by a MOS transistor coupled to the boosting node to be formed and a capacitor, the MOS transistor included in the positive boosting charge pump circuit is negative The phase of the ON operation period may be different from that of the MOS transistor included in the boosting charge pump circuit.
[0018]
Since a relatively large current is required for erasing and writing to the nonvolatile memory, it is desirable that the power supply of the booster circuit is not directly connected to the power supplies of other circuits. According to this aspect, the voltage clamping means includes a reference voltage generation circuit having a small power supply voltage dependency, and negative feedback control of the output circuit to the first voltage using the reference voltage output from the reference voltage generation circuit as a reference voltage. And a second constant voltage generation circuit that performs negative feedback control of the output circuit to the first voltage using the voltage output from the first constant voltage generation circuit as a reference voltage. It is desirable that the output voltage of the second constant voltage generating circuit is supplied to the positive booster and the negative booster.
[0019]
A third constant voltage generating circuit for performing negative feedback control of the output circuit using the voltage output from the first constant voltage generating circuit as a reference voltage, and reading out the output voltage of the third constant voltage generating circuit; The operating power supply voltage can be used.
[0020]
It is desirable to provide a trimming circuit so that the output voltage of the voltage clamp means can be finely adjusted for process variations. At this time, trimming control means for controlling the trimming circuit in accordance with trimming adjustment information and register means for setting trimming adjustment information to be supplied to the trimming control means are provided. The register means receives the trimming adjustment information from a specific area of the nonvolatile memory. Thereby, trimming can be performed freely by software. There is no restriction that it cannot be changed once programmed, as in the case of using a fuse.
[0021]
When the trimming adjustment information also affects the read voltage of the non-volatile memory, the transfer of the trimming adjustment information from the non-volatile memory to the register means may be performed when it takes a longer time than usual to read from the non-volatile memory. It is desirable for preventing malfunction. That is, such transfer may be performed in synchronization with the reset operation of the semiconductor integrated circuit. Thereby, the fluctuation of the internal voltage until the trimming operation is confirmed can be confirmed during the reset, and the read operation can be stabilized after the reset operation. When the trimming adjustment information affects only the write and erase voltages of the nonvolatile memory, the trimming adjustment information may be transferred during the reset period or before the first vector fetch (instruction fetch) after the reset is released. .
[0022]
Considering the point of selecting trimming information in the test mode, it is preferable that the central processing unit can access the register means in the test mode.
[0023]
The wafer completion state of the semiconductor integrated circuit is a write state (for example, a logic value “0” with a low threshold voltage), and shipment of the semiconductor integrated circuit is an erased state (for example, a logic value “1” with a high threshold voltage). It is desirable that the trimming state becomes extreme between the writing state and the erasing state so that there is no significant difference in the output voltage of the voltage clamping means. Therefore, the trimming control means determines the trimming position of the trimming circuit according to the value of the trimming adjustment information, and the trimming position and the trimming adjustment information when the trimming adjustment information is the all-bit logical value “1”. It has selection logic that selects the trimming position when all bit logical values are “0” so that they are adjacent to each other. When the nonvolatile memory is in the write state in the wafer completion state, the nonvolatile memory is in the erased state at the time of shipment. The difference in the output voltage of the voltage clamping means is minimized.
[0024]
It takes time to obtain a specified boosted voltage by the boosting means, and this time is also affected by process variations. Write and erase operations must be started after the boosted voltage reaches a specified voltage. Such management is realized by software by a central processing unit. That is, it has a control register for controlling the nonvolatile memory, and the control register starts a write operation using a write setup bit for instructing the booster to start a boost operation for writing and a boost voltage. A write enable bit for instructing the booster, an erase setup bit for instructing the boosting means to start the boost operation for erasure, and an erase enable bit for instructing the start of the erase operation using the boosted voltage. As a result, it is possible to reduce hardware such as a timer that manages the timing of actually starting erase or write after an erase or write operation is instructed.
[0025]
Further, the control register is provided with a rewrite enable bit for instructing a preparation state of the boost operation by the boosting means, and the erase setup bit and the write setup bit are instructed on condition that the rewrite enable bit is a true value. By making it acceptable, the write or erase operation can be performed on condition that the rewrite enable bit is a true value, so that the nonvolatile memory may be undesirably rewritten due to a runaway of the central processing unit or the like. Help to prevent.
[0026]
In order to further improve the reliability of preventing undesired rewriting of the nonvolatile memory, the control register adds a protect bit in which a value is set according to the state of the external terminal, and the protect bit is a true value. It is preferable to perform an interlock that enables the boost enable bit to be set to a true value (predetermined value) on condition that it is (predetermined value).
[0027]
In order to reduce the burden imposed on the internal circuit by the application of a negative voltage necessary for erasing or writing, it is desirable to switch the applied voltage after once setting the word line or the like to the ground potential. For example, an electrically erasable and writable flash memory and a central processing unit capable of accessing the flash memory are included in one semiconductor substrate, and a single power supply voltage supplied to an external power supply terminal is used as an operation power supply. In the microcomputer, the flash memory includes a memory cell array having a plurality of memory cell transistors each having a control gate connected to a word line, a drain connected to a bit line, and a source connected to a source line; A booster circuit that generates a high voltage for an erase operation, an address decoder that forms a word line selection signal based on an address signal, and a word line selection level during a read operation having a first polarity with respect to the ground potential, and writing The word line selection level is set to the second polarity with respect to the ground potential. Word driver circuit and all word lines are forced to the ground potential at the start and end of the write operation, the operation power supply of the word driver is switched to the ground potential, and the polarity of the selection level of the selection signal of the address decoder is logically inverted And timing control means for switching the operating power supply of the word driver.
[0028]
DETAILED DESCRIPTION OF THE INVENTION
<Microcomputer chip>
FIG. 3 is a block diagram of a microcomputer (microprocessor or data processing apparatus) according to an example of the present invention. The microcomputer 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
[0029]
The microcomputer 1 shown in the figure is not particularly limited, but includes a central processing unit (CPU) 2, flash memories (FLE 0, FLE 1) 3, flash memory control register (FLC) 4, and random access memory (RAM) 5. , Interrupt controller (INTC) 6, multiplier (MULT) 7, timer (ATU) 8, bus and system controller (BSC, SYS) 9, watchdog timer (WDT) 10, direct memory access controller (DMA) 11, clock Pulse generator (CPG) 12, serial communication interface (SCI) 13, phase locked loop circuit (PLL) 14, analog / digital converter (A / D_0, A / D_1), and a plurality of port inputs / outputs PA, P , A PC, PD, PE, PG, PH, the PM. Each circuit block is coupled to an address bus, a data bus, a control bus, etc. (not shown).
[0030]
Although not particularly limited, the microcomputer 1 is used for embedded device control, and the operation program of the CPU 2 is stored in the flash memory 3. The RAM 5 serves as a work area for the CPU 2 or a temporary storage area for data.
[0031]
The microcomputer 1 shown in FIG. 3 uses a single external power supply voltage Vcc supplied to the external power supply terminal Pvcc as an operation power supply. Pvss is a ground terminal. The potential supplied to the ground terminal is the ground voltage Vss. The external power supply voltage Vcc is not particularly limited, but corresponds to so-called 3V and 5V power supplies (with an allowable error of ± 10%), and a voltage in the range of 2.7V to 5.5V is set as an allowable range of the external power supply voltage. .
[0032]
In FIG. 3, RES is a reset terminal (reset signal) of the microcomputer, VppMON and VssMON are monitor terminals for the internal boosted voltage, and Pfwe is a write protect terminal for the flash memory 3. In particular, VppMON is for monitoring the internal positive boost voltage, and VssMON is for monitoring the internal negative boost voltage.
[0033]
<Flash memory>
FIG. 4 shows an overall block diagram of the flash memory 3 and a control register 4. FIG. 4 representatively shows one flash memory 3 indicated by FLE0 in FIG. The other flash memory 3 indicated by FLE1 is also the same and is not shown.
[0034]
In FIG. 4, 17 is a data bus and 18 is an address bus. Although not particularly limited, the CPU 2, the RAM 5, and the flash memory 3 that are representatively shown share the address bus 18 and the data bus 17. The control register 4 shown in FIG. 3 includes an erase block designation register EBR1, a rewrite control register FLMCR1, and reference voltage trimming registers TRMR1 and TRMR2 in FIG. Each control register EBR1, FLMCR1, TRMR1, TRMR2 is made accessible by the CPU2. CPU access to the registers TRMR1 and TRMR2 has the limitations described later.
[0035]
A large number of nonvolatile memory cells are arranged in the memory cell array 30. Although not specifically shown, the nonvolatile memory cell has a source, a drain, a floating gate, and a control gate, and a gate oxide film (insulating film) is thinned so that a tunnel current due to a tunnel phenomenon can flow. The source is coupled to the source line, the drain is coupled to the bit line, and the control gate is coupled to the word line. The X decoder (X-DEC) 31 decodes the X address signal fetched from the address bus 18 into the address buffer 32 to form a word line selection signal. The word driver (WDRV) 33 drives the word line selected by the word line selection signal to a predetermined selection level according to the operation mode (write, erase, read, etc.). The bit line selected via the Y selector 34 is connected to the write circuit 35 or the sense amplifier 36. The sense amplifier 36 detects the data read from the memory cell, gives the data corresponding to the logical value to the output buffer 37, and the output buffer 37 performs the output operation to the data bus 17 in accordance with the data output operation instruction. The write circuit 35 applies a write voltage corresponding to the write data supplied from the data bus 17 to the input buffer 38 to the bit line selected by the Y selector 34. A Y decoder (Y-DEC) 31 decodes a Y address signal taken into the address buffer 32 from the address bus 18 and forms a selection signal for the Y selector 34. The source and substrate control unit 39 performs control to select the source line of the erase block designated by the erase block designation register EBR1, and controls the substrate voltage of the memory cell array 30 according to the erase or write operation.
[0036]
In FIG. 4, reference numeral 40 denotes a power supply circuit for the flash memory, which generates a high voltage for writing and erasing and an operating voltage for a read system based on the single external power supply voltage Vcc. The power supply circuit 40 includes a reference voltage circuit, a read clamp power supply circuit, a boost clamp power supply circuit, a first positive booster circuit, a second positive booster circuit, a negative booster circuit, and various voltages formed by the above circuits. A voltage supply switch group is selected and supplied to the internal circuit of the flash memory 3.
[0037]
The trimming control unit 42 is a control circuit for adjusting the characteristics of the power supply circuit with respect to process variations and the like. Control data for the trimming controller 42 is supplied from the reference voltage trimming register TRMR1 and the boost voltage trimming register TRMR2. Various operating power sources generated by the power source circuit 40 are selected according to the operation of the flash memory and supplied to the source control unit 39, the write circuit 35, the word driver 33, and the like. The power supply control unit 41 performs a writing sequence, an erasing sequence, etc. relating to power supply at this time. The power control unit 41 has a write sequencer, an erase sequencer, and the like. Control data for a write sequence and an erase sequence is given from the rewrite control register FLMCR1. A circuit block indicated by 43 is other control logic of the flash memory 3.
[0038]
FIG. 5 shows a configuration example of the memory cell array 30. Although not particularly limited, in the illustrated structure, the bit line is constituted by the main bit line 300 and the sub bit line 301, and the drain of the nonvolatile memory cell 302 is coupled to the sub bit line 301. The main bit line 300 and the sub bit line 301 are selectively turned on by a selection MOS transistor 303. The sources of the nonvolatile memory cells 302 are commonly connected to a predetermined source line 304 for each group. 305 is a word line, and 306 is a select line of the selection MOS transistor.
[0039]
FIG. 6 shows an example of a voltage application state in the erase operation. The minimum unit of erasing is a block unit that shares a source line. The erase selection source line is -9.5V, the select line 306 is -9.5V, the erase selection word line is 9.5V, and the erase unselected word line is 0V (ground potential Vss). As a result, electrons are injected into the floating gate of the nonvolatile memory cell 302 in the block to be erased 307, and the threshold voltage of the nonvolatile memory cell is increased. That is, data is erased by utilizing the electron tunneling phenomenon from the drain (source) and channel portion to the floating gate through the gate insulating film.
[0040]
FIG. 7 shows an example of a voltage application state in the write operation. Writing is performed for each word line. The write selection word line is −9.5 V, the write selection bit line is 6.5 V, the write non-selection bit line is 0 V, the write selection select line is 9.5 V, and the source line is open (floating). As a result, electrons are emitted from the floating gate of the nonvolatile memory cell 302 selected for writing, and the threshold voltage of the memory cell is lowered. That is, data is written by utilizing the electron tunneling phenomenon from the floating gate to the drain (source) and the channel portion through the gate insulating film.
[0041]
FIG. 8 is a block diagram showing the operating power supply in each part of the flash memory. In FIG. 8, what is indicated by 33Z is the driver (ZDRV) of the select line 306. The driver 33Z is supplied with a decode signal from a Z decoder (Z-DEC) 31Z for decoding an address signal assigned to block selection. The Z driver 33Z drives the select line according to the selection signal output from the Z decoder 31Z. What is indicated by 33Y is a Y select driver, which determines the level of the switch control signal of the Y selector 34. In FIG. 4, the Y select driver 33Y, the Z driver 33Z, and the Z decoder 31Z are not shown.
[0042]
FIG. 9 shows the meanings of the various operation power supplies shown in FIG. The relationship between the voltage and operation of these various operating power supplies is illustrated in FIG. FIG. 11 shows the voltages that can be taken by the various operating power supplies. 9.5V and 6.5V are generated by positive boosting, and -9.5V is generated by negative boosting.
[0043]
<Power supply circuit>
FIG. 1 schematically shows the main part of the power supply circuit 40. The power supply circuit 40 clamps the output voltage to the first voltage Vfix (2.5 V) having a level lower than the external power supply voltage Vcc (2.7 V to 5.5 V) using a reference voltage having a small power supply voltage dependency. A voltage clamping unit 44 is included, and a voltage boosting circuit using the voltage Vfix (also referred to as a clamp voltage Vfix) as an operation power supply is included. The booster circuit includes three charge pump circuits 45, 46 and 47 and a ring oscillator 48 common to them. The charge pump circuit 45 and the ring oscillator 48 constitute a first positive booster circuit, which forms a 9.5V positive boost voltage based on the clamp voltage Vfix. The charge pump circuit 46 and the ring oscillator 48 constitute a second positive booster circuit, which forms a 6.5V positive boost voltage based on the clamp voltage Vfix. The charge pump circuit 47 and the ring oscillator 48 constitute a negative booster circuit and forms a negative booster voltage of −9.5V based on the clamp voltage Vfix.
[0044]
The voltage clamp means 44 forms a clamp voltage Vfix having a small power supply voltage dependency, and the clamp voltage Vfix is higher than the single power supply voltage Vcc supplied from the outside within an allowable range of 2.7 V to 5.5 V. Since the voltage is clamped at a low voltage (2.5 V), the boosted voltage generated by the positive and negative booster circuits operated by the clamp voltage Vfix, that is, the write and erase voltages are stable without depending on the external power supply voltage Vcc. The voltage. In the configuration shown in FIG. 2 as a comparative example, the operating power supply of the ring oscillator and the charge pump circuit is the external power supply voltage Vcc, and the boosted voltage is varied depending on the external power supply voltage Vcc.
[0045]
<Clamp power supply>
FIG. 12 shows an example of the voltage clamp means 44. The voltage clamp means 44 includes a reference voltage generation circuit 400, a first constant voltage generation circuit 401, a second constant voltage generation circuit (boost clamp power supply circuit) 402, and a third low voltage generation circuit (read clamp power supply). Circuit) 403.
[0046]
The reference voltage generation circuit 400 is a circuit that generates a reference voltage Vref having small power supply voltage dependency and temperature dependency using a band gap of silicon or the like. The operating power supply of the reference voltage generating circuit 400 is Vcc. Since such a reference voltage generating circuit 400 is known, its detailed circuit configuration is not shown. In this example, the reference voltage Vref is 1.4V ± 0.3V.
[0047]
The first constant voltage generation circuit 401 is a circuit that performs negative feedback control of the output circuit to the clamp voltage Vrefa using the reference voltage Vref as a reference voltage. Specifically, a source follower circuit constituted by an n-channel MOS transistor Q1 and a feedback resistor circuit (ladder resistor circuit) FBR1 is provided as an output circuit, and has a CMOS operational amplifier OP1 and a non-inverting input terminal ( The reference voltage Vref is received at (+), the feedback signal from the output circuit is received at the inverting input terminal (−) of the operational amplifier OP1, and the conductance of the MOS transistor Q1 is controlled by the output of the operational amplifier OP1. The clamp voltage Vrefa is a constant voltage determined by the voltage dividing ratio of the feedback resistor circuit FBR1 and the reference voltage Vref. This clamp voltage Vrefa is logically independent of the power supply voltage Vcc. According to this example, the clamp voltage Vrefa is adjusted using the feedback resistor circuit FBR1 so as to be 2.5V.
[0048]
A more detailed example of the first constant voltage generation circuit 401 is shown in FIGS. As shown in FIG. 16, the voltage dividing ratio of the feedback resistor circuit FBR1 can be selected by a switch 410. That is, the feedback resistor circuit FBR1 constitutes a trimming resistor circuit capable of adjusting the resistance voltage dividing ratio. In FIG. 17, BIAS is a signal for biasing the current source transistors of the differential amplifier circuit and the output circuit, and is output from a bias circuit (not shown). FSTBYW is a standby signal, determines the state of the internal node in the low power consumption mode of the microcomputer 1, and cuts off a useless current through path.
[0049]
The second constant voltage generation circuit 402 is a circuit that performs negative feedback control of the output circuit to the clamp voltage VfixB using the clamp voltage Vrefa as a reference voltage. Specifically, a source follower circuit composed of an n-channel MOS transistor Q2 and a feedback resistor circuit FBR2 is provided as an output circuit, and has a CMOS operational amplifier OP2, and the clamp is connected to the non-inverting input terminal (+) of the operational amplifier OP2. The voltage Vrefa is received, the inverting input terminal (−) of the operational amplifier OP2 receives the feedback signal from the output circuit, and the conductance of the MOS transistor Q2 is controlled by the output of the operational amplifier OP2. The clamp voltage VfixB is a constant voltage determined by the voltage dividing ratio of the feedback resistor circuit FBR2 and the clamp voltage Vrefa. This clamp voltage Vrefa is logically independent of the power supply voltage Vcc. According to this example, the voltage dividing ratio of the feedback resistor circuit FBR2 is determined so that the clamp voltage VfixB is 2.5V. The clamp voltage VfixB in FIG. 12 corresponds to Vfix shown in FIG.
[0050]
The third constant voltage generation circuit 403 is a circuit that performs negative feedback control of the output circuit to the clamp voltage VfixA using the clamp voltage Vrefa as a reference voltage. Specifically, a source follower circuit constituted by an n-channel MOS transistor Q3 and a feedback resistor circuit FBR3 is provided as an output circuit, has an operational amplifier OP2, and the clamp voltage is applied to the non-inverting input terminal (+) of the operational amplifier OP2. Vrefa is received, the feedback signal from the output circuit is received at the inverting input terminal (−) of the operational amplifier OP2, and the conductance of the MOS transistor Q2 is controlled by the output of the operational amplifier OP2. The feedback signal is fed back through an n-channel MOS transistor Q4 for 2.5V output or an n-channel MOS transistor Q5 for 4.0V output. The clamp voltage VfixA is set to a substantially constant voltage determined by the voltage division ratio of the feedback resistor circuit FBR2 and the clamp voltage Vrefa. This clamp voltage Vrefa is logically independent of the power supply voltage Vcc. According to this example, the voltage dividing ratio of the feedback resistor circuit FBR2 is such that when the transistor Q4 is selected, the clamp voltage VfixA is 2.5V, and when the transistor Q5 is selected, the clamp voltage VfixA is 4.0V. Has been determined. The clamp voltage VfixA is used as an operation power source for the read system. Whether the clamp voltage VfixA is set to 2.5V or 4.0V is selected depending on the operation mode. For example, in read operation, the wordline selection level at the time of reading is VfixA = 4.0V from the viewpoint of reducing the wordline disturbance. Is used. At this time, Vcc is used as the sense amplifier power source. On the other hand, in the erase verify and the write verify, VfixA = 2.5V is used for the power supply of the driver of the Y selector and the sense amplifier so that the write and erase levels do not depend on the power supply voltage Vcc.
[0051]
The clamp voltage VfixB is an operation power source for boosting a high voltage used for writing and erasing, and is separated from the clamp voltage VfixA which is a power source for other read system operations. A relatively large current is required for programming and erasing, and a relatively large current flows through the booster circuit for supplying it. Therefore, the power supply voltage fluctuates due to the boosting operation by separating the boosting system from other power supply systems. Can minimize the influence of other circuits.
[0052]
《Boost circuit》
FIG. 13 shows the charge pumps 45 and 46 as an example of the first and second positive booster circuits and their peripheral circuits. Although not specifically shown, the charge pump circuits 45 and 46 each have a plurality of boosting nodes in which a MOS transistor and a capacitive element are coupled, and generate a high voltage by a charge pumping action of the MOS transistor and the capacitor. The clock drivers 420 and 421 generate a plurality of driving signals for causing the charge pump circuits 45 and 46 to perform the charge pump operation. The operating power supply of the clock drivers 420 and 421 is the clamp voltage VfixB. The drive signal shifts the phase and switches the plurality of MOS transistors, and sequentially applies a regular voltage change to one electrode of the capacitor, whereby the drive signal is sequentially and regularly applied to one electrode of the capacitor. The voltage of the other electrode that is changed according to the change is sequentially transmitted to the subsequent stage via the MOS transistor. The drive signal is generated in synchronization with the clock signal CLK output from the ring oscillator 48. Comparators 422 and 423 are provided in order to maintain the boosted voltages VPP6 and VPP9 generated by the charge pump circuits 46 and 45 at a specified voltage. The comparators 422 and 423 are supplied with voltages VCMP6 and VCMP9 obtained by dividing the boosted voltages VPP6 and VPP9 by the resistance circuits 428 and 429, and are compared with the clamp voltage Vrefa. The voltages VCMP6 and VCMP9 are made equal to or higher than the voltage Vrefa when the boosted voltage becomes a specified voltage (VPP6 = 6.5V, VPP9 = 9.5V). The comparators 422 and 423 invert the detection signals 424 and 425 from the low level to the high level by detecting the state. The detection signals 424 and 425 are ORed with the clock signal CLK by OR gates 426 and 427 and supplied to the clock drivers 420 and 421. Therefore, when the boosted voltages VPP6 and VPP9 reach a prescribed voltage, the outputs of the OR gates 426 and 427 are fixed at a high level, and during that time, the boosting operation by the charge pump circuits 45 and 46 is temporarily stopped. Reference numerals 430 and 431 denote switch circuits which are cut off when the boosting operation is completed.
[0053]
FIG. 14 shows a charge pump circuit 47 and its peripheral circuit as an example of a negative and positive booster circuit. Although not specifically shown, the charge pump circuit 47 has a plurality of boosting nodes each of which is coupled with a MOS transistor and a capacitive element, and generates a negative high voltage by a charge pumping action of the MOS transistor and the capacitor. The clock driver 434 generates a drive signal having a plurality of phases for causing the charge pump circuit 47 to perform a charge pump operation. The operating power supply of the clock driver 434 is set to the clamp voltage VfixB. The drive signal shifts the phase and switches the plurality of MOS transistors, and sequentially applies a regular voltage change to one electrode of the capacitor, whereby the drive signal is sequentially and regularly applied to one electrode of the capacitor. The voltage of the other electrode that is changed according to the change is sequentially transmitted to the subsequent stage via the MOS transistor. The drive signal is generated in synchronization with the clock signal CLK output from the ring oscillator 48 shown in FIG. In order to maintain the negative boosted voltage VPPMNS9 generated by the charge pump circuit 47 at a specified voltage, a comparator 435 is provided. The comparator 435 is supplied with a voltage VPCMP9 obtained by dividing the boosted voltage VPPMNS9 by the resistance circuit 436, and is compared with the ground potential Vss. The voltage VPCMP9 is made lower than the ground voltage Vss when the boosted voltage VPPNMS becomes a specified voltage (VPPMNS9 = −9.5 V). The comparator 435 detects the state and inverts the detection signal 437 from the low level to the high level. The detection signal 437 is logically ORed with the clock signal CLK by an OR gate 438 and supplied to the clock driver 434. Therefore, when the boosted voltage VPPMNS9 reaches a specified voltage, the output of the OR gate 438 is fixed to a high level, and during that time, the boosting operation by the charge pump circuit 47 is temporarily stopped. A switch circuit 439 is cut off when the boosting operation is completed.
[0054]
The negative boosted voltage VPPMNS9 output from the charge pump circuit 47 can be observed from the monitor terminal VssMON. A circuit indicated by 440 is a switch circuit that is turned on in the test mode. The positive boosted voltages VPP6 and VPP9 can be selectively observed from the monitor terminal VCPMON as illustrated in FIG. Reference numerals 441 and 442 denote switch circuits that transmit the positive boosted voltages VPP6 and VPP9 to the monitor terminal VCPMON. MONE is an enable signal for instructing monitoring of the boosted voltage by the monitor terminal VppMON according to a high level, MONS is a signal for instructing whether to monitor VPP6 or VPP9, and the switch circuits 441 and 442 are signals MONE, The ON operation is performed exclusively in accordance with the state of MONS, whereby the desired boosted voltage VPP6 or VPP9 can be observed.
[0055]
In FIG. 13, what is indicated by OSE is an oscillation operation start instruction signal for the ring oscillator 48. A signal indicated by VPE1 is a signal for instructing the clock driver 421 and the charge pump circuit 46 to start a boosting operation. What is indicated by VPE2 is a signal instructing the clock driver 420 and the charge pump circuit 45 to start a boosting operation. In FIG. 14, a signal indicated by VPE3 is a signal for instructing the clock driver 434 and the charge pump circuit 47 to start a boosting operation.
[0056]
The three types of clock drivers 420, 421, and 434 have a common clamp power supply VfixB as the operation power supply, and use one ring oscillator 48 as a clock source. At this time, as illustrated in FIG. 13, the clock signal CLK is supplied to the clock driver 421 of the charge pump circuit 46 via the delay circuit 444. A clock signal CLK is supplied to the clock driver 420 of the charge pump circuit 45 via two stages of delay circuits 444 and 445 in series. On the other hand, as illustrated in FIG. 14, the clock signal CLK is supplied to the clock driver 434 of the charge pump circuit 47 without passing through the delay circuit. Accordingly, as illustrated in FIG. 18, the clock signal CLK output from the ring oscillator 48 is sequentially shifted in phase, so that the −9.5V boosting clock signal, the + 6.5V clock signal, and the + 9.5V clock signal are output. Are supplied to the clock drivers 434, 421, and 420. The drive signals of the charge pump circuits 47, 46, 45 formed by the clock drivers 434, 421, 420 are synchronized with the clock signals that are out of phase. That is, in the clock drivers 434, 421, and 420, the transistors are switched in synchronization with the change of the clock signal, and the current flowing through the circuit is changed in synchronization with the switching operation. Therefore, since the clock signals supplied to the clock drivers 434, 421, 420 are out of phase, the instantaneous current change that occurs in the entire clock drivers 434, 421, 420 is reduced, and the boosting clamp power supply circuit 402 is The burden on the power supply circuit can be reduced. This contributes to stabilization of the boosting operation and further stabilization of the writing and erasing operations.
[0057]
<Change of substrate bias voltage of charge pump circuit>
FIG. 19 shows an example of the charge pump circuit 47 and the clock driver 434 for boosting the negative voltage. In the charge pump circuit 47 shown only partially in FIG. 19, what is indicated by NP is a boost node. A charge transfer p-channel MOS transistor Q10 is arranged between adjacent boosting nodes. Further, one electrode of the charge pump capacitive element C1 is coupled to each boost node NP. One electrode of another capacitive element C2 is coupled to the gate of the MOS transistor Q10. P-channel type transfer MOS transistors Q11 and Q12 are arranged in parallel between the gate of the MOS transistor Q10 and the previous boost node NP. The gate of the MOS transistor Q11 is the boost node NP and the gate of the MOS transistor Q12 is the MOS. Coupled to the gate of transistor Q10. MOS transistors Q13 and Q14 are transistors for initializing boost node NP. The capacitance value of the capacitive element C1 is set larger than the capacitance value of C2. As described above, the charge pump circuit 47 is configured by connecting a plurality of unit circuits each including the MOS transistors Q10 to Q13 and the capacitive elements C1 and C2 in series.
[0058]
The clock driver 434 sequentially delays the clock signal CLK to generate three-phase clock signals φa to φc having different phases, and outputs four drive signals DS1 to DS4 based on the three-phase clock signals φa to φc. To do. FIG. 20 shows waveforms of clock signals φa to φc and drive signals DS1 to DS4 generated by the logic configuration of the clock driver 434 shown in FIG.
[0059]
The drive signals DS1 and DS2 are alternately supplied to the other electrode of the capacitive element C1, and the drive signals DS3 and DS4 are supplied alternately to the other electrode of the capacitive element C2. For example, in a state where the MOS transistor Q10 is turned off by the high level (t1) of DS4 and the level of the boosting node is raised by the high level (t1) of DS2, the previous boosting node NP is driven by the low level (t2) of DS1. When the voltage is lowered, the level of the gate of the adjacent MOS transistor Q10 is also lowered through the transistor Q11. Immediately thereafter, the level of the boosting node NP is further lowered by changing DS3 to the low level (t3). . The lowered level is transferred to boosting node NP in the next stage via MOS transistor Q10. By such a charge pump operation, the voltage VPPMNS9 is gradually boosted to a negative voltage.
[0060]
The NOR gate 450 shown in FIG. 19 replaces the function of the OR gate 438 described in FIG.
[0061]
The drive signals D1 to D4 are changed between the ground potential Vss and the clamp voltage VfixB. At the start of the boosting operation, the clamp voltage VfixB is applied to the gates of the MOS transistors Q10, Q11, Q12 of the charge pump circuit 47. As the boosting operation proceeds, the gate voltage is lowered. Therefore, if the substrate bias voltage common to the MOS transistors Q10, Q11, and Q12 is not set to at least the clamp voltage VfixB at the start of the boost operation, the pn junction portion of the transistor is undesirably put in the forward bias state. There is a risk of malfunction.
[0062]
In this example, the MOS transistors Q10, Q11, Q12 are formed in a common well region. The substrate bias voltage (well bias voltage) common to these MOS transistors Q10, Q11, and Q12 is set to the clamp voltage VfixB at the start of the boosting operation, and is switched to the ground voltage Vss in the middle.
[0063]
FIG. 21 shows a configuration for switching the substrate bias voltage of the charge pump circuit. In FIG. 21, reference numeral 460 denotes switch means for switching the substrate bias voltage to the clamp voltage VfixB or the ground voltage Vss. The switch state of the switch means 460 is not particularly limited, but is determined by the state of the output terminal Q of the set / reset type flip-flop (SR-FF) 461. An inverted signal of the boost enable signal VPE3 is supplied to the reset terminal R of the flip-flop 461, and the reset state is set when the boost operation is not performed. In this reset state, the switch means 460 selects the clamp voltage VfixB as the substrate bias voltage 462. The set terminal S of the flip-flop 461 receives the output signal 464 of the comparator 463. The comparator 463 monitors whether the potential of the voltage dividing point ND1 of the resistor circuit 436 is equal to or lower than the ground potential Vss. The voltage dividing point ND1 is set to the ground potential Vss when the boosted voltage VPPMNS9 becomes a predetermined voltage lower than the ground potential Vss. Therefore, when the boosted voltage Vss becomes a predetermined voltage lower than the ground potential Vss, the flip-flop 461 is set, whereby the switch unit 460 selects the ground voltage Vss as the substrate bias voltage 462. In FIG. 14, the switch means 460 is composed of an inverter having a clamp voltage VfixB and a ground voltage Vss as operation power supplies.
[0064]
When the substrate bias voltage 462 is switched to the ground voltage Vss having a level lower than the clamp voltage VfixB during the negative voltage boosting, the threshold voltages of the MOS transistors Q10, Q11, and Q12 become small due to the so-called substrate bias effect, thereby charging Charges are easily transferred through the MOS transistors Q10, Q11, and Q12 that perform pumping. Accordingly, it is possible to improve the efficiency of the negative voltage boosting operation in which the level difference of the target boosted voltage (VPPMNS9 = −9.5V) is the largest with respect to the operating power supply (VfixB = 2.5V), and the specified negative boosting The time until the voltage is obtained can be shortened.
[0065]
For example, FIG. 22 shows a transition state of the boosted voltage VPPMNS9 in the negative voltage boosting operation. FIG. 5A shows a transition state of the boosted voltage VPPMNS9 when the substrate bias voltage is fixed to the clamp voltage VfixB without switching. (B) shows a transition state when the substrate bias voltage is switched halfway. Compared to (a), in the case of (b), the negative voltage boosting operation efficiency is improved, and the time required to obtain the specified negative boosted voltage is shortened.
[0066]
Once the substrate bias voltage is switched to the ground potential Vss, the flip-flop 461 maintains the set state even if the output of the comparator 463 is subsequently inverted. That is, flip-flop 461 has a hysteresis characteristic that maintains the substrate bias voltage at ground potential Vss even if boosted voltage VPPMNS9 fluctuates up and down after the substrate bias voltage is switched. Such hysteresis characteristics can also be realized by using a hysteresis comparator in the comparator 463 instead of the SR flip-flop 461.
[0067]
As shown in FIG. 22, the boosted voltage in the course of boosting by the charge pump fluctuates up and down in synchronization with the switching operation of the charge pump MOS transistors Q10, Q11, and Q12. By switching the substrate bias voltage of the charge pump circuit 47 by the output signal of a circuit having hysteresis characteristics typified by the flip-flop 461, the substrate bias voltage once changed under the influence of the ripple component of the negative boost voltage is the original. Undesirable oscillation of the substrate bias that is changed again to the substrate bias can be prevented.
[0068]
<Software trimming of power supply circuit>
The feedback resistor circuit FBR1 of the constant voltage generation circuit 401 shown in FIGS. 12 and 16 and the resistor circuit 436 shown in FIG. 14 are trimming resistor circuits (trimming resistor circuits). As described with reference to FIG. 16, the configuration is a circuit such as a so-called ladder resistor circuit in which one of the many switches 410 is turned on to determine a voltage dividing point to be used as an output node. . In feedback resistance circuit FBR1, the feedback resistance value is determined according to the resistance voltage division ratio at the output node selected by switch 410. Similarly, in the resistance circuit 436, a voltage corresponding to the resistance voltage division ratio at the node (ND1) selected by the switch 410 is supplied to the comparator 463. The trimming of the feedback resistor circuit FBR1 has the significance of setting the clamp voltages VfixA and VfixB to desirable voltages by matching the original voltage Vrefa of the power supply circuit 40 to a required level with respect to process variations. The resistor circuit 436 on the negative boost circuit side can be trimmed by optimizing the boost level control and the well bias voltage switching point for the negative boost voltage VPPMNS9 having the largest boost width, thereby optimizing the negative boost operation. Has the significance of Note that the resistor circuits 428 and 429 on the positive booster circuit side may be trimmed.
[0069]
The selection signal of the switch 410 for determining the resistance voltage dividing ratio at the output node of the resistor circuit (also referred to as trimming resistor circuit) FBR1, 436 is generated by the selector 470 as illustrated in FIG. According to the example of FIG. 23, the selector 470 decodes the trimming information and sets one switch selection signal to the selection level. The selector 470 is individualized into the trimming resistor circuit FBR1 and the trimming resistor circuit 436, and is included in the trimming control unit 42 shown in FIG.
[0070]
The trimming information of the resistor circuit FBR1 is supplied from the reference voltage trimming register TRMR1 to the selector 470 of the resistor circuit FBR1, and the trimming information of the resistor circuit 436 is supplied from the boosted voltage trimming register TRMR2 to the selector 470 of the resistor circuit 436. As illustrated in FIG. 25, the trimming information (reference voltage trimming information) set in the reference voltage trimming register TRMR1 is VR0 to VR4 and TEVR. Trimming information (boosted voltage trimming information) set in the boosted voltage trimming register TRMR2 is VM0 to VM4 and TEVM.
[0071]
As illustrated in FIG. 23, a dedicated storage area 300 for storing the reference voltage trimming information and the boosted voltage trimming information is allocated to the memory cell array 30 of the flash memory 3. According to this example, the information in the area 300 is transferred to the registers TRMR1 and TRMR2 in synchronization with the reset operation of the microcomputer 1. This transfer control is not particularly limited, but is automatically performed by hardware as shown in FIG. That is, when the reset signal RST is asserted, the control unit 43 of the flash memory 3 controls the address buffer 32, the sense amplifier 36, the output buffer 37, etc. in order to read the data in the area 300 to the data bus 17, The data in the area 300 is automatically read out to the outside. On the other hand, the registers TRMR1 and TRM2 are controlled so that data can be input from the data bus 17 in synchronization with the assertion of the reset signal RST. As a result, the data in area 300 is automatically transferred to registers TRMR1 and TRMR2.
[0072]
The reference voltage trimming information and the boost voltage trimming information are determined at the time of a device test in order to absorb process variations and the like. The data transfer described with reference to FIG. 24 is also performed when the test mode is set in the microcomputer 1. In the initial stage of the device test, since the flash memory 3 is in a write state (trimming information in the region 300 is in a state where all bit logical values are “0”) in the wafer completion state, the trimming information in the registers TRMR1 and TRMR2 is in all bit logic. The value is set to “0”. In the test mode, the registers TRMR1 and TRMR2 can be read / written by the CPU2. At the time of device test, the positive and negative boosted voltages are monitored from the monitor terminals VppMON and VssMON, and the reference voltage trimming information and the boosted voltage trimming information are determined so that they become a prescribed voltage. The reference voltage trimming information and boosted voltage trimming information thus determined are stored in the predetermined area 300 of the flash memory 3 by the CPU 2 under a predetermined test mode. Thereafter, each time the microcomputer 1 is reset, the power supply circuit 40 is controlled in accordance with the optimally determined reference voltage trimming information and boosted voltage trimming information. Access to the predetermined area 300 is prohibited in the normal operation mode (or user mode). If the predetermined test mode is set again, the area can be accessed to reset the reference voltage trimming information and the boost voltage trimming information. Device tests by semiconductor manufacturers include tests at the time of shipment in addition to tests at the wafer stage. It is also possible to set reference voltage trimming information and boosted voltage trimming information at each test stage. It is assumed that the reference voltage trimming information and the boosted voltage trimming information are finally written in the predetermined area 300 after a test at the shipping stage.
[0073]
According to this example, the flash memory 3 is in a writing state (for example, a state of a logical value “0” having a low threshold voltage) in a wafer completion state of the microcomputer. At the time of shipment of the microcomputer, the flash memory is in an erased state (for example, a state of a logical value “1” having a high threshold voltage). It is desirable that the trimming state becomes extreme between the writing state and the erasing state so that a large difference in the output voltage of the power supply circuit does not occur. For example, when the reference voltage trimming information and the boosted voltage trimming information are finally written in the predetermined region 300 after the shipping stage test, the boosted voltage initially obtained in the wafer stage test and the initial stage in the shipping test are initially set. If there is a large difference that cannot be ignored from the boosted voltage obtained, the test or inspection efficiency may be reduced. In the case of a microcomputer chip that does not require trimming, it can be shipped in an erased state.
[0074]
Therefore, as illustrated in FIG. 23, the selector 470 performs the trimming position when the trimming adjustment information is the all-bit logical value “1” and the trimming position when the trimming adjustment information is the all-bit logical value “0”. Are selected so as to be adjacent to each other. As a result, the difference in the output voltage of the power supply circuit can be minimized both when the flash memory 3 is in the written state in the wafer completion state and when the flash memory is in the erased state at the time of shipment. . For example, according to the example of FIG. 23, when the flash memory 3 is in the write state (trimming information in the area 300 is in the state of all bit logical values “0”) in the wafer completion state, it is indicated by “000” and the switch is set at the trimming position. When the microcomputer is shipped and the flash memory is in the erased state (the trimming information in the area 300 is in the state of all bit logical values “1”), the switch is selected at the trimming position indicated by “111”.
[0075]
As is apparent from FIG. 12, the trimming adjustment information also affects the read voltage of the flash memory 3. That is, the clamp voltage Vrefa output from the constant voltage circuit 401 including the feedback resistor circuit FBR1 to be trimmed is used as a reference voltage for the read clamp power supply circuit 403 that generates the read power supply. At this time, the transfer of the trimming adjustment information from the flash memory 3 to the register TRMR1 is performed when the read access to the flash memory 3 can be performed in a time longer than the specified access time of the read operation in order to prevent malfunction. Is desirable. This is because even if the read voltage is slightly lower than a prescribed value, if the read time is extended, data can be read accurately from the memory array. In this respect, the microcomputer 1 performs initial transfer of trimming adjustment information in synchronization with the reset operation. Therefore, fluctuations in the internal voltage until the trimming operation is confirmed can be determined during the reset, and the read operation can be stabilized after the reset operation. When the trimming adjustment information affects only the write and erase voltages of the flash memory 3, the trimming adjustment information may be transferred during the reset period or before the first vector fetch (instruction fetch) after reset release. .
[0076]
<Rewrite sequence for flash memory>
A detailed example of the rewrite control register FLMCR1 and the erase block designation register EBR1 of the flash memory 3 is shown in FIG. Bits EB0 to EB7 of the erase block designation register EBR1 are erase block designation data.
[0077]
The rewrite control register FLMCR1 has control bits of P, E, PV, EV, PSU, ESU, SWE, and FWE, and their true values are not particularly limited, but are set to a logical value “1”.
[0078]
The rewrite enable bit SWE indicates a preparation state for the boosting operation by the power supply circuit 40. For example, when the rewrite enable bit SWE is set to the logical value “1”, the control signal OSE shown in FIG. 13 is asserted, whereby the ring oscillator 48 starts the oscillation operation and outputs the clock signal CLK. Further, the boost clamp power supply VfixB is activated.
[0079]
The write setup bit PSU instructs the power supply circuit 40 to start a boost operation for writing. According to this example, when the write setup bit PSU is set to the logical value “1”, the control signals VPE1, VPE2, and VPE3 shown in FIG. 13 are asserted, and the clock drivers 420, 421, and 434 and the charge pump circuit 45, The operation of 46, 47 is started, and the voltage VPP6, VPP9, VPPMNS9 is started to step up to + 6.5V, + 9.5V, -9.5V. In order to substantially perform the boosting operation, it is premised on the supply of the clock signal CLK from the ring oscillator 48.
[0080]
The write enable bit P instructs the start of a write operation using the boosted voltages VPP6, VPP9, and VPPMNS9.
[0081]
The erase setup bit ESU instructs the power supply circuit 40 to start the boosting operation for erase. According to this example, when the erase setup bit ESU is set to the logical value “1”, the control signal VPE2 shown in FIG. 13 and the control signal VPE3 shown in FIG. 14 are asserted, and the clock drivers 420 and 434 and the charge pump The operations of the circuits 45 and 47 are started, and the voltage VPP9 and VPPMNS9 are started to be boosted to + 9.5V and −9.5V. In order to substantially perform the boosting operation, it is premised on the supply of the clock signal CLK from the ring oscillator 48.
[0082]
The erase enable bit E instructs the start of the erase operation using the boosted voltages VPP9 and VPPMNS9.
[0083]
It takes time to obtain a specified boosted voltage by the boosting means, and the time is affected by process variations. Write and erase operations must be started after the boosted voltage reaches a specified voltage. At this time, the time from the start of the boost operation to the start of writing can be determined by the time from the setting of the bit PSU to the logical value “1” to the setting of the bit P to the logical value “1”. . Similarly, the time from the start of the boost operation to the start of erasing can be determined by the time from setting the bit ESU to the logical value “1” to setting the bit E to the logical value “1”. . These bits are set by executing software by the CPU 2. As a result, it is possible to reduce hardware such as a timer that manages the timing of actually starting erase or write after an erase or write operation is instructed. Further, such a time setting can be arbitrarily determined according to circuit characteristics.
[0084]
In addition, on the condition that the rewrite enable bit SWE is a true value, the start of the boost operation by the erase setup bit ESU and the write setup bit PSU can be substantially accepted. Execution is possible on condition that SWE is a true value. Therefore, it is useful for preventing the occurrence of a situation where the flash memory 3 is undesirably rewritten due to a runaway of the CPU 2 or the like.
[0085]
The protect bit FWE of the rewrite control register FLMCR1 is set to a value corresponding to the state of the external terminal Pfwe. FWE is a read-only bit. The protect bit FWE performs an interlock that enables the boost enable bit SWE to be set to a logical value “1” on the condition that it is a true value, for example, a logical value “1”. That is, the protect bit FWE is used as one of the initialization signals of the boost enable bit SWE. Only when FWE = 1, the boost enable bit SWE can be set / cleared. When FWE = 0, the boost enable bit is in the initial state. For example, an unillustrated AND gate that takes the logical product of the corresponding signal line from the data bus and the protect bit FWE is provided, and the boost enable bit SWE bit can be the output of the AND gate. As a result, an interlock can be realized. By adding an interlock by the protect bit FWE, the rewrite protection by the SWE and the FWE can be doubled, and the reliability of the undesired rewrite prevention for the flash memory 3 can be further improved.
[0086]
FIG. 26 and FIG. 27 show an example of a control flowchart of the erase operation by the CPU 2. The CPU 2 sets the SWE bit of the register FLMCR1 to a logical value “1” (S1). In order to enable this setting, it is necessary that a signal having a logical value “1” is applied to the external terminal Pfwe and the protect bit FWE is set to the logical value “1”. As a result, the ring oscillator starts to oscillate. Then, n = 1 is substituted into an appropriate register (S2), and an erase block is set in the register EBR1 (S3). Next, the logical value “1” of the ESU bit of the register FLMCR1 is set (S4). As a result, the boosting operation by the clock drivers 420 and 434 and the charge pump circuits 45 and 47 is started. When the E bit of FLMCR1 is set to a logical value “1” after a predetermined time has elapsed, an erasing operation is started (S5). When the E bit of FLMCR1 is cleared to the logical value “0” after the erase operation is finished, the erase operation is stopped (S6). Then, the ESU bit 2 of the FLMCR1 is cleared to the logical value “0” to stop the boosting operation (S7). Thereafter, the EV bit of the FLMCR1 is set to the logical value “1” (S8), so that the erasing operation is performed. Erase verification is performed for. In the erase verify operation, after performing dummy write (S9) to the verify address and verify data read (S10), it is determined whether the read verify data is all bit logical values “1” (S11). If all bit logical values are “1”, the address is incremented until the last address is reached (S12, S13), and the above process is repeated for each address increment. If the data read in S11 is not the logical value “1”, the erase operation is insufficient. Therefore, the EV bit is cleared (S14), and the number of repetitions of erase does not reach the upper limit (N). (NG in S15), the process returns to S4 again to advance the erased state. If the process proceeds to the last address in S12, the erase verify is normally completed. In S15, when the number of times of erasure reaches the upper limit, the erase verify is terminated abnormally.
[0087]
FIG. 28 and FIG. 29 show an example of a control flowchart of the write operation by the CPU 2. The CPU 2 sets the SWE bit of the register FLMCR1 to a logical value “1” (T1). In order to enable this setting, it is necessary that a signal having a logical value “1” is applied to the external terminal Pfwe and the protect bit FWE is set to the logical value “1”. As a result, the ring oscillator starts to oscillate. Then, n = 1 is assigned to an appropriate register (T2), and an appropriate flag flag is cleared (= 0) (T3). Then, for example, 32-byte write data is continuously written to the flash memory 3 (T4). Write data is held in a data register included in the write circuit of the flash memory 3. Next, the logical value “1” of the PSU bit of the register FLMCR1 is set (T5). As a result, the boosting operation by the clock drivers 420, 421, 434 and the charge pump circuits 45, 46, 47 is started. When the P bit of FLMCR1 is set to a logical value “1” after a predetermined time has elapsed, a write operation is started (T6). After the write operation is completed, when the P bit of FLMCR1 is cleared to a logical value “0”, the write operation is stopped (T7). Then, the PSU bit 2 of FLMCR1 is cleared to the logical value “0” to stop the boosting operation (T8).
[0088]
Thereafter, by setting the PV bit of FLMCR1 to the logical value “1” (T9), the write verify for the write operation is performed. In the write verify operation, after performing dummy write (T10) to the verify address and verify data read (T11), the rewrite data is calculated based on the read verify data and the original data of the write, It is determined whether the write data is all bit logical values “1” (T12). The calculation of rewrite data is performed as shown in FIG. If the rewrite data is all bits “1”, the rewrite data is transferred to the RAM (T13), and the address increment is performed until the verification of the 32-byte data is completed (T14, T15). repeat. If the rewritten data is not all bits “1” in step T12, the flag flag is set to “1” (T16), and the process proceeds to step T14. When the 32-byte verify operation is completed, the PV bit is cleared (S17), and the flag flag is determined (T18). If flag = 0, writing of 32 bytes is normal, so the SWE bit is cleared (T19) and the writing operation is terminated. If flag = 1 in step T18, it is determined whether the number of writes has reached the predetermined upper limit value N (T20). If the predetermined number has been reached, the SWE bit is cleared (T21), and an abnormal end is determined. Is done. If the number of repetitions of the write operation has not reached the upper limit (N), the counter n is incremented (T22), and the process returns to step T3.
[0089]
FIG. 31 shows an example of a word line drive voltage switching system in order to reduce the burden imposed on the internal circuit by the application of a high voltage necessary for writing. Schematically, the operating voltage is switched after the word line is once set to the ground potential Vss. That is, when the boosting operation of the write boosting circuit is instructed by the PSU bit, all word lines are forced to the ground potential Vss during the period shown in FIG. Next, the power sources VPPX2, VSSXW, and VSSXS of the word driver WDRV are respectively switched to the ground potential Vss during the period shown in FIG. Next, as described in the column of address control, the polarity of the word line selection is reversed. For example, the selection level of the X address decoder that forms the word line selection signal based on the address signal is logically inverted from a high level (during a read operation) to a low level (during a write operation). After that, as shown in FIG. 31E, the power supply of the word driver is switched to the power supply for writing. Similarly, when writing is finished, all word lines are forced to the ground potential Vss, the driver power supplies VPPX1, VSSXW, VSSXS are switched to the ground potential Vss, the polarity of the word line selection logic is changed, and the power supply is switched. . The switching of the power is performed by a power supply switch group included in the power circuit 40, and the control is performed by the write sequencer of the power controller 41.
[0090]
Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.
[0091]
For example, the external single power source is not limited to 2.7 to 5.5V. The boosted voltage is not limited to 6.5V, 9.5V, and -9.5V, and can be changed. Similarly, the clamp voltage is not limited to 2.5V. Furthermore, the voltage application mode for writing and erasing is not limited to the above. The configurations of the booster circuit and the clamp circuit can be changed as appropriate. In addition, if the current supply capability is large, it is possible to share a clamp power source divided into a lead system and a boost system. The built-in module of the microcomputer can be changed as appropriate. The flash memory can adopt an appropriate circuit format such as NOR or AND. The flash memory is not limited to the use replacing the program memory, and may be used exclusively for data storage.
[0092]
In the above description, the case where the invention made mainly by the present inventor is applied to a microcomputer for device embedded control, which is a field of use that is the background of the invention, has been described. The present invention can be widely applied to semiconductor integrated circuits such as microcomputers and other dedicated controller LSIs.
[0093]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
[0094]
That is, the voltage clamping means forms a voltage having a small power supply voltage dependency, and the voltage level is clamped to a voltage lower than the single power supply voltage supplied from the outside within an allowable range. The boosted voltage generated by the boosting means operated in step 1, i.e., the write and erase voltages, does not depend on the external power supply voltage. Therefore, the built-in nonvolatile memory can be erased and written in a relatively wide external power supply voltage range including low voltage operation. In addition, since this can be achieved with a single external power supply voltage, the usability of a semiconductor integrated circuit incorporating a nonvolatile memory can be improved.
[0095]
When the boosted voltage reaches a predetermined level, the boosting operation efficiency can be improved by changing the substrate bias voltage common to the MOS transistors that perform charge pumping.
[0096]
Even if the boosted voltage fluctuates up and down after the substrate bias voltage is switched, a hysteresis characteristic is maintained to maintain the substrate bias voltage at the switched voltage. It is possible to prevent the substrate bias voltage from vibrating due to the influence of the ripple component when it swings up and down in synchronization with the switch operation.
[0097]
By shifting the phase of the operation of each charge pump circuit, the instantaneous voltage drop of the power supply can be reduced when a plurality of charge pump circuits are operated with the same power supply.
[0098]
The output voltage of the voltage clamp means can be trimmed according to the value of the register means that receives the transfer of trimming adjustment information from a specific area of the non-volatile memory. It is also possible to absorb the effects of.
[0099]
By transferring the trimming adjustment information to the register means in synchronization with the reset operation of the semiconductor integrated circuit, the fluctuation of the internal voltage until the trimming operation is confirmed can be determined during the reset, and the reliability can be improved.
[0100]
If the central processing unit makes the register means accessible in the test mode, the trimming information can be easily determined in the test mode.
[0101]
The wafer completion state of the semiconductor integrated circuit is a write state (for example, a logic value “0” with a low threshold voltage), and shipment of the semiconductor integrated circuit is an erased state (for example, a logic value “1” with a high threshold voltage) State), the selection logic for selecting adjacently the trimming position when the trimming adjustment information is all-bit logical value “1” and the trimming position when the trimming adjustment information is all-bit logical value “0”. By adopting, it is possible to prevent the trimming state from becoming extreme between the writing state and the erasing state and causing a large difference in the output voltage of the voltage clamping means.
[0102]
Reduces hardware such as timers by implementing management to start writing and erasing after obtaining the specified boosted voltage with the boosting means using software by the central processing unit using the write setup bit and erase setup bit be able to.
[0103]
The control register is provided with a rewrite enable bit for instructing the preparation state of the boosting operation by the boosting means, and the instruction by the erase setup bit and the write setup bit can be accepted on condition that the rewrite enable bit is a true value. By doing so, the write or erase operation can be performed on condition that the rewrite enable bit is a true value, so that it is possible to prevent the nonvolatile memory from being undesirably rewritten due to a runaway of the central processing unit or the like. To help.
[0104]
The control register adds a protect bit whose value is set according to the state of the external terminal, and the protect bit is an interface that enables the boost enable bit to be set to a true value on condition that it is a true value. When locking is performed, the reliability of preventing undesired rewriting of the nonvolatile memory can be further improved.
[0105]
If the applied voltage is switched after the word line or the like is once set to the ground potential, the burden imposed on the internal circuit by the application of the high voltage necessary for erasing or writing can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram schematically showing main parts of a power supply circuit.
FIG. 2 is a block diagram illustrating a comparative example of FIG.
FIG. 3 is a block diagram of a microcomputer according to an example of the present invention.
FIG. 4 is an overall block diagram of a flash memory built in a microcomputer.
FIG. 5 is a circuit diagram showing a configuration example of a memory cell array.
FIG. 6 is a circuit diagram showing an example of a voltage application state in an erase operation.
FIG. 7 is a circuit diagram showing an example of a voltage application state in a write operation.
FIG. 8 is a block diagram showing an operating power supply in each part of the flash memory.
FIG. 9 is an explanatory diagram showing the meaning of various operation power supplies shown in FIG. 8;
10 is an explanatory diagram showing the relationship between the voltage and operation of various operation power supplies shown in FIG.
11 is an explanatory diagram showing organized voltages that can be taken by the various operation power supplies in FIG. 8; FIG.
FIG. 12 is a circuit diagram of an example of voltage clamping means.
FIG. 13 is a circuit diagram of an example of first and second positive booster circuits.
FIG. 14 is a circuit diagram of an example of a negative and positive booster circuit.
FIG. 15 is an explanatory diagram of a circuit that enables a positive boosted voltage to be selectively monitored.
FIG. 16 is an explanatory diagram of a trimming resistor circuit of a first constant voltage generation circuit.
FIG. 17 is a detailed example circuit diagram of a first constant voltage generation circuit;
FIG. 18 is a waveform explanatory diagram of a boosting operation clock signal.
FIG. 19 is a circuit diagram illustrating an example of a charge pump circuit and a clock driver for boosting a negative voltage.
20 is a waveform explanatory diagram of a clock signal and a drive signal generated by the logic configuration of the clock driver shown in FIG. 19;
FIG. 21 is a block diagram schematically showing a configuration for switching the substrate bias voltage of a charge pump circuit.
FIG. 22 is an explanatory diagram showing a transition state of a boosted voltage in a negative voltage boosting operation.
FIG. 23 is a conceptual diagram of a trimming method in a trimming resistor circuit.
FIG. 24 is an explanatory diagram of a system for transferring trimming adjustment information from the flash memory to the control register in synchronization with the reset operation of the microcomputer.
FIG. 25 is a format diagram of an example of a control register.
FIG. 26 is a flowchart showing a part of the erase operation control by the CPU.
FIG. 27 is a flowchart showing the remainder of the erase operation control by the CPU.
FIG. 28 is a flowchart showing a part of write operation control by a CPU.
FIG. 29 is a flowchart showing the rest of the write operation control by the CPU.
FIG. 30 is an explanatory diagram of a rewrite data calculation method;
FIG. 31 is a timing chart showing an example of a word line drive voltage switching process in order to reduce a load imposed on an internal circuit by application of a high voltage necessary for writing.
[Explanation of symbols]
1 Microcomputer
2 Central processing unit
3 Flash memory
4 Control register for flash memory
FLMCR1 rewrite control register
TRMR1 reference voltage trimming register
TRMR2 boost voltage trimming register
Vcc External single power supply voltage
Vss Ground voltage
Pvcc Vcc external terminal
Pvss Vss external terminal
VppMON, VssMON Monitor terminal
Pfwe write protect terminal
RES reset terminal
30 memory cell array
31 X decoder
31Y Y decoder
33 Word driver
40 Power supply circuit
41 Power control unit
42 Trimming controller
44 Voltage clamping means
45, 46 Charge pump circuit for positive boost
47 Charge pump circuit for negative boost
48 Ring Oscillator
300 Main bit line
301 sub-bit line
302 Nonvolatile memory cell
304 source line
305 word line
400 Reference voltage generator
401 First constant voltage circuit
402 Second constant voltage circuit
403 Third constant voltage circuit
FBR1 feedback resistor circuit (trimming resistor circuit)
FBR2, FBR3 feedback resistor circuit
Vref reference voltage
Vrefa, VfixA, VfixB Clamp voltage
CLK clock signal
420, 421, 434 clock driver
436 Trimming resistor circuit
444, 445 delay circuit
VPP6, VPP9 Positive boost voltage
460 Substrate bias voltage switching means
VPPMNS9 negative boost voltage
461 SR flip-flop
464 comparator
NP boost node
Q10, Q11, Q12 Negative channel boosting p-channel MOS transistor
C1, C2 Capacitor for negative boost
DS1 to DS4 drive signal
470 selector
330 Trimming Information Storage Area in Flash Memory
FWE protect bit
SWE rewrite enable bit
ESU erase setup bit
PSU write setup bit
E Erase enable bit
P Write enable bit

Claims (14)

A semiconductor integrated circuit in which an electrically writable and erasable nonvolatile memory and a central processing unit accessible to the nonvolatile memory are formed on a single semiconductor substrate,
The semiconductor integrated circuit includes a voltage clamping unit and a booster circuit, and uses a single external power supply voltage supplied from the outside of the semiconductor substrate as an operation power supply, and the external power supply voltage of the semiconductor integrated circuit. The allowable range is from the first voltage to the second voltage smaller than the first voltage,
The voltage clamping means receives the external power supply voltage and generates a voltage smaller than the second voltage;
The booster circuit receives the voltage output from the voltage clamp unit and generates an internal positive boosted voltage or an internal negative boosted voltage that is greater than the voltage output from the voltage clamp unit,
The nonvolatile memory has a plurality of nonvolatile memory cells that erase or write data using the internal positive boosted voltage or the internal negative boosted voltage ,
The voltage clamp means receives the external power supply voltage, generates a reference voltage, a first constant voltage generation circuit that outputs a first clamp voltage using the reference voltage as a reference voltage, and the first A second constant voltage generation circuit that outputs a second clamp voltage using the voltage output from the constant voltage generation circuit as a reference voltage, and a third clamp voltage that uses the voltage output from the first constant voltage generation circuit as a reference voltage And a third constant voltage generating circuit that
The first constant voltage generation circuit includes a circuit that negatively feeds back the first clamp voltage,
The second constant voltage generation circuit includes a circuit that negatively feeds back the second clamp voltage,
The third constant voltage generation circuit includes a circuit that negatively feeds back the third clamp voltage,
The booster circuit is supplied with the second clamp voltage;
The semiconductor integrated circuit according to claim 3, wherein the third clamp voltage is an operating power supply voltage for a read system . In claim 1 ,
The booster circuit includes:
A charge pump circuit having a boost node connected to a P-type MOS transistor and a capacitor to generate the internal negative boost voltage;
Switch means for switching the substrate bias voltage so that the threshold value of the P-type MOS transistor becomes small while the voltage output from the boosting circuit reaches the internal negative boosted voltage from the start of boosting operation. A semiconductor integrated circuit. In claim 2 ,
A substrate integrated voltage of the P-type MOS transistor is not switched during the boosting operation when switched by the switch means after the boosting operation is started. In claim 1,
The booster circuit includes a negative voltage booster circuit having a boosting node connected to a MOS transistor and a capacitor for generating the internal negative boosted voltage, and a MOS transistor and a capacitor for generating the internal positive boosted voltage. A semiconductor integrated circuit comprising: a positive voltage boosting circuit having a boosting node connected thereto. In claim 1,
The semiconductor integrated circuit includes a trimming circuit for finely adjusting a voltage output from the booster circuit, a trimming control unit for controlling the trimming circuit according to trimming adjustment information, and trimming control for the trimming adjustment information. A register in which the trimming adjustment information is set to be supplied to the unit,
The semiconductor integrated circuit according to claim 1, wherein the register is supplied with the trimming adjustment information from a specific area of the nonvolatile memory. In claim 5 ,
In the semiconductor integrated circuit, the trimming adjustment information is set in the register in a reset operation of the semiconductor integrated circuit. In claim 6 ,
The semiconductor integrated circuit according to claim 1, wherein the central processing unit is accessible to the register. A semiconductor integrated circuit in which an electrically writable and erasable nonvolatile memory and a central processing unit accessible to the nonvolatile memory are formed on a single semiconductor substrate,
The semiconductor integrated circuit includes a voltage clamping unit and a booster circuit, and a single external power supply voltage supplied from the outside of the semiconductor substrate is used as an operation power supply.
The voltage clamp means receives the external power supply voltage and generates an internal voltage smaller than the external power supply voltage with a reference voltage having a small dependency on the external power supply voltage as a reference voltage,
The booster circuit receives the voltage output from the voltage clamp unit and generates an internal positive boosted voltage or an internal negative boosted voltage that is greater than the voltage output from the voltage clamp unit,
The nonvolatile memory has a plurality of nonvolatile memory cells that erase or write data using the internal positive boosted voltage or the internal negative boosted voltage ,
The voltage clamp means receives the external power supply voltage, generates a reference voltage, a first constant voltage generation circuit that outputs a first clamp voltage using the reference voltage as a reference voltage, and the first A second constant voltage generation circuit that outputs a second clamp voltage using the voltage output from the constant voltage generation circuit as a reference voltage, and a third clamp voltage using the voltage output from the first constant voltage generation circuit as a reference voltage A third constant voltage generating circuit for outputting,
The first constant voltage generation circuit includes a circuit that negatively feeds back the first clamp voltage,
The second constant voltage generation circuit includes a circuit that negatively feeds back the second clamp voltage,
The third constant voltage generation circuit includes a circuit that negatively feeds back the third clamp voltage,
The booster circuit is supplied with the second clamp voltage;
The semiconductor integrated circuit according to claim 3, wherein the third clamp voltage is an operating power supply voltage for a read system . In claim 8 ,
The booster circuit includes:
A charge pump circuit having a boost node connected to a P-type MOS transistor and a capacitor to generate the internal negative boost voltage;
Switch means for switching the substrate bias voltage so that the threshold value of the P-type MOS transistor becomes small while the voltage output from the boosting circuit reaches the internal negative boosted voltage from the start of boosting operation. A semiconductor integrated circuit. In claim 9 ,
A substrate integrated voltage of the P-type MOS transistor is not switched during the boosting operation when switched by the switch means after the boosting operation is started. In claim 8 ,
The booster circuit includes a negative voltage booster circuit having a boosting node connected to a MOS transistor and a capacitor for generating the internal negative boosted voltage, and a MOS transistor and a capacitor for generating the internal positive boosted voltage. A semiconductor integrated circuit comprising: a positive voltage boosting circuit having a boosting node connected thereto. In claim 8 ,
The semiconductor integrated circuit includes a trimming circuit for finely adjusting a voltage output from the booster circuit, a trimming control unit for controlling the trimming circuit according to trimming adjustment information, and trimming control for the trimming adjustment information. A register in which the trimming adjustment information is set to be supplied to the unit,
The semiconductor integrated circuit according to claim 1, wherein the register is supplied with the trimming adjustment information from a specific area of the nonvolatile memory. In claim 12 ,
In the semiconductor integrated circuit, the trimming adjustment information is set in the register in a reset operation of the semiconductor integrated circuit. In claim 13 ,
The semiconductor integrated circuit according to claim 1, wherein the central processing unit is accessible to the register.

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