JPH10214496A - Semiconductor integrated circuit and microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow stable write and erase of built-in flash memory in a comparatively wide voltage region of the external power source covering a low-voltage operation in a microcomputer with built-in flash memory. SOLUTION: A voltage clamp means 44 which uses a reference voltage generating circuit and a constant-voltage circuit forms a voltage Vfix small in power source voltage dependence and further its voltage level is clamped on a voltage lower than the single power source voltage Vcc which is fed externally within a permissible range. Thereby, the step-up voltage, namely write and erase voltage, generated by step-up means (45-48) which are operated by the clamp voltage Vfix does not depend on the external power source voltage Vcc.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit including a nonvolatile memory and a central processing unit. For example, the present invention relates to a one-chip microcomputer, a data processing unit or a microprocessor incorporating a flash memory and a central processing unit. The present invention relates to a technology which is effective when applied to unify an external operation power supply.

[0002]

2. Description of the Related Art As a microcomputer having a built-in flash memory, for example, H8 / 5 manufactured by Hitachi, Ltd.
38F, H8 / 3048, H8 / 3434F and the like.

[0003] A memory cell transistor of a flash memory has a floating gate, a control gate, a source and a drain, and holds binary information according to the state of charge injection into the floating gate. For example, when charge is injected into the floating gate, the threshold voltage of the memory cell increases, and the threshold voltage as viewed from the control gate is increased, so that no current flows through the memory cell. In addition, a current flows through the memory cell by discharging charges from the floating gate to lower the threshold voltage as viewed from the control gate. Although not particularly limited, an operation of setting the threshold voltage of the memory cell to be higher than a word line selection level at the time of reading is performed by an erasing operation (data selected thereby is a logical value "1":
The operation of making the threshold voltage of the memory cell lower than the word line selection level at the time of reading is referred to as a writing operation (the data selected thereby is a logical value "0": written state). Note that the erased state and the written state of the data stored in the memory cell may be defined in reverse to the above.

In erasing or writing to the memory cell transistor, the floating gate must be placed in a high electric field, so that a high voltage for erasing and writing, such as 3 V or 5 V, which is higher than a general power supply voltage, is applied. I need. Such a high voltage has been conventionally supplied as an external power supply.

[0005]

However, when such a high voltage is obtained from an external power supply, a circuit for generating the high voltage must be mounted on a circuit board on which the microcomputer is mounted. However, due to the high voltage, special consideration is required for the design of the circuit board, and there is a problem that the usability is poor.

The present inventor has studied making a microcomputer having a built-in flash memory operable with a single power supply such as 3V or 5V. That is, an external single power supply is internally boosted to generate a high voltage for writing and erasing.

At this time, the operating power supply of the microcomputer has been reduced to 3 V due to the demand for low power consumption, and there is a system which uses 3 V, and a system using a single 5 V power supply. Whether the power supply voltage is 3 V or 5 V is determined by the specifications of the system to which the microcomputer is applied. For this reason, it is advisable for a semiconductor maker to design a microcomputer so that it can operate with a relatively wide range of power supply such as 3 V to 5 V.

In consideration of this, the following points have been made clear according to the study of the present inventors. That is, a charge injection method for a flash memory includes a channel injection method in which a relatively large current flows through a channel of a memory cell transistor to generate hot electrons near a drain, thereby injecting charge into a floating gate, and a floating gate and a drain. There is a tunnel current method in which a predetermined electric field strength acts between the electrodes to cause a tunnel current to flow through a relatively thin tunnel oxide film near the drain to inject charges. The former requires a relatively large current and is not suitable for internal boosting.However, even in the latter case, simply performing internal boosting stably operates the built-in flash over a relatively wide external power supply voltage range including low-voltage operation. It has been revealed that writing and erasing of the memory cannot be realized.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit such as a microcomputer having an electrically writable and erasable nonvolatile memory such as a flash memory in a relatively wide external power supply voltage range including a low voltage operation. It is to enable stable writing and erasing of a built-in nonvolatile memory.

Another object of the present invention is to improve the usability of a semiconductor integrated circuit such as a microcomputer having an electrically writable and erasable nonvolatile memory such as a flash memory.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a semiconductor integrated circuit such as a microcomputer includes a non-volatile memory such as an electrically erasable and writable flash memory and a central processing unit capable of accessing the non-volatile memory on a single semiconductor substrate. A single power supply voltage supplied to the external power supply terminal is used as an operation power supply. The nonvolatile memory includes a voltage clamp unit that clamps an output voltage to a first voltage lower in level than the single power supply voltage by using a reference voltage having a small power supply voltage dependency, and an output of the voltage clamp unit. Boosting means capable of boosting the voltage to a positive high voltage and a negative high voltage,
And a plurality of non-volatile memory cells for erasing and writing using high positive and negative voltages output from the boosting means.

According to this semiconductor integrated circuit, the voltage clamping means forms a voltage having a small power supply voltage dependency, and the voltage level is externally set within an allowable operating power supply voltage of the semiconductor integrated circuit. Since the voltage is clamped to a voltage lower than the supplied single power supply voltage, the boosted voltage generated by the boosting means operated by the clamp voltage, that is, the write and erase voltages does not depend on the external power supply voltage. Therefore, erasing and writing of the built-in nonvolatile memory can be performed in a relatively wide external power supply voltage range including low-voltage operation. Moreover, since this can be achieved with a single external power supply voltage, the usability of a semiconductor integrated circuit having a built-in nonvolatile memory is improved.

In order to improve the boosting operation efficiency, when the boosted voltage reaches a predetermined level, an MO that performs a charge pump is operated.
The substrate bias voltage common to the S transistors is changed.
For example, a p-channel MOS transistor and a capacitor are coupled to a boost node that forms a negative high voltage, and a charge pump circuit that generates a negative high voltage by a charge pump action by the transistor is provided. Switching means for switching the substrate bias voltage from the output voltage of the voltage clamping means to a second voltage lower than the output voltage on the way is further provided. The second voltage is a voltage having a higher level than the boosted voltage at the time of the switching. In this example, when the substrate bias voltage is reduced, the threshold voltage of the MOS transistor is reduced due to the so-called substrate bias effect, which makes it easier for charges to move through the MOS transistor that performs the charge pump. This improves the boosting operation efficiency and shortens the time until a specified boosted voltage is obtained.

The boosted voltage that is being boosted by the charge pump swings up and down in synchronization with the switching operation of the charge pump MOS transistor. To prevent the substrate bias voltage from oscillating due to the influence of such a ripple component,
The switching means has a hysteresis characteristic for maintaining the substrate bias voltage at the second voltage even if the boosted voltage fluctuates up and down after the switching of the substrate bias voltage. Such a hysteresis characteristic uses a hysteresis comparator,
Alternatively, it can be achieved by holding the state by a circuit such as an SR flip-flop.

When a plurality of charge pump circuits are operated with the same power supply, it is desirable to reduce the instantaneous voltage drop of the power supply by shifting the operation phase of each charge pump circuit. For example, the boosting means includes a negative boosting charge pump circuit that generates a negative high voltage by a charge pumping operation of a MOS transistor and a capacitor coupled to a boosting node that forms a negative high voltage; When there is a positive boosting charge pump circuit that generates a positive high voltage by a charge pumping operation of a MOS transistor and a capacitor coupled to a boosting node to be formed, the MOS transistor included in the positive boosting charge pump circuit is connected to a negative electrode. The phase of the MOS transistor included in the boosting charge pump circuit during the ON operation period may be different.

Since a relatively large current is required for erasing and writing to the nonvolatile memory, it is desirable that the power supply of the booster circuit is not directly connected to the power supply of another circuit. According to this aspect, the voltage clamp means includes a reference voltage generation circuit having a small power supply voltage dependency, and a negative feedback control of the output circuit to the first voltage using the reference voltage output from the reference voltage generation circuit as a reference voltage. A first constant voltage generating circuit, and a second constant voltage generating circuit that performs negative feedback control of the output circuit to the first voltage using a voltage output from the first constant voltage generating circuit as a reference voltage. Preferably, the output voltage of the second constant voltage generating circuit is supplied to the positive booster and the negative booster.

A third constant voltage generating circuit for performing negative feedback control of the output circuit using the voltage output from the first constant voltage generating circuit as a reference voltage, wherein the output voltage of the third constant voltage generating circuit is It can be the operating power supply voltage of the reading system.

It is desirable to provide a trimming circuit so that the output voltage of the voltage clamping means can be finely adjusted with respect to process variations and the like. At this time, there are provided trimming control means for controlling the trimming circuit according to trimming adjustment information, and register means for setting trimming adjustment information to be supplied to the trimming control means. The register unit receives the transfer of the trimming adjustment information from a specific area of the nonvolatile memory.
Thereby, the trimming can be freely performed by software. There is no restriction that it cannot be changed after programming once as in the case of using a fuse.

When the trimming adjustment information also affects the read voltage of the non-volatile memory, the transfer of the trimming adjustment information from the non-volatile memory to the register means may take a longer time than required to read the non-volatile memory. It is desirable to do so in order to prevent malfunction. That is, such a transfer may be performed in synchronization with the reset operation of the semiconductor integrated circuit. Thereby, the fluctuation of the internal voltage until the trimming operation is determined can be determined during the reset,
After the reset operation, the read operation can be stabilized. When the trimming adjustment information affects only the write and erase voltages of the nonvolatile memory, the transfer of the trimming adjustment information may be performed during the reset period or before the first vector fetch (instruction fetch) after reset release. .

In consideration of selection of trimming information in the test mode, it is desirable that the central processing unit can access the register means in the test mode.

The completed state of the wafer of the semiconductor integrated circuit is a write state (for example, a state of a logic value "0" with a low threshold voltage), and the shipment of the semiconductor integrated circuit is an erase state (for example, a state of a logic value with a high threshold voltage). In the case of “1”), it is desirable that the trimming state becomes extreme between the writing state and the erasing state so that there is no large difference in the output voltage of the voltage clamp means. For this purpose, the trimming control means determines the trimming position of the trimming circuit according to the value of the trimming adjustment information, and the trimming position and the trimming adjustment information when the trimming adjustment information is the logical value “1” of all bits are determined. There is a selection logic for selecting the trimming position adjacent to all bits at logical value “0” so that the nonvolatile memory is in a write state in a wafer completed state and is in an erased state at the time of shipment. Both when and when
The difference in the output voltage of the voltage clamping means is minimized.

It takes a considerable amount of time to obtain a specified boosted voltage by the boosting means, and the time is affected by process variations. Write and erase operations must be started after the boosted voltage reaches the specified voltage. Such management is realized by software by a central processing unit. That is, it has a control register for controlling the nonvolatile memory, the control register includes a write setup bit for instructing the booster to start a boosting operation for writing, and a start of a writing operation using the boosted voltage. , An erase setup bit for instructing the boosting means to start a boosting operation for erasing, and an erase enable bit for instructing to start an erasing operation using a boosted voltage. This makes it possible to reduce hardware such as a timer for managing the timing at which erasing or writing is actually started after an erasing or writing operation is instructed.

Further, the control register is provided with a rewrite enable bit for instructing a preparation state for the boosting operation by the boosting means, and provided that the erase enable bit and the write setup bit are provided on condition that the rewrite enable bit is a true value. , The write or erase operation can be performed on condition that the rewrite enable bit is a true value. Therefore, the nonvolatile memory is undesirably rewritten due to runaway of the central processing unit or the like. Helps prevent things from happening.

In order to further improve the reliability of preventing undesired rewriting of the nonvolatile memory, the control register adds a protect bit in which a value is set according to the state of an external terminal, and the protect bit is a control bit. It is preferable to perform an interlock that enables the boost enable bit to be set to a true value (predetermined value) on the condition that is a true value (predetermined value).

In order to reduce the load on the internal circuit due to the application of a negative voltage necessary for erasing or writing, it is desirable that the applied voltage be switched after the word line or the like is once grounded. For example, a single semiconductor substrate includes an electrically erasable and writable flash memory and a central processing unit accessible to the flash memory, and a single power supply voltage supplied to an external power supply terminal is referred to as an operation power supply. In the microcomputer, the flash memory includes a memory cell array having a plurality of memory cell transistors having a control gate connected to a word line, a drain connected to a bit line, and a source connected to a source line. A booster circuit for generating a high voltage for an erasing operation, an address decoder for forming a word line selection signal based on an address signal, and a word line selection level at the time of a read operation having a first polarity with respect to a ground potential, and a write operation. The word line selection level at the time is set to the second polarity with respect to the ground potential. At the start and end of the word driver circuit and the write operation, all word lines are forced to the ground potential, the operation power supply of the word driver is switched to the ground potential, and the polarity of the selection level of the selection signal of the address decoder is logically inverted. And timing control means for switching the operation power supply of the word driver.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION

<< Microcomputer Chip >> FIG. 3 shows a block diagram of a microcomputer (microprocessor or data processing device) according to an example of the present invention. The microcomputer 1 shown in FIG. 1 is not particularly limited,
It is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The microcomputer 1 shown in FIG.
Is not particularly limited, but a central processing unit (CPU) 2,
Flash memory (FLE0, FLE1) 3, flash memory control register (FLC) 4, random access memory (RAM) 5, interrupt controller (INTC) 6, multiplier (MULT) 7, timer (A)
TU) 8, bus and system controller (BSC, S)
YS) 9, watchdog timer (WDT) 10, direct memory access controller (DMA) 11, clock pulse generator (CPG) 12, serial communication interface (SCI) 13, phase-locked loop circuit (PLL) 14, analog-to-digital converter (A / D — 0, A / D — 1) and a plurality of port inputs / outputs PA, PB, PC, PD, P
E, PG, PH, PM. Each of the circuit blocks is connected to an address bus, a data bus, a control bus, and the like (not shown).

Although not particularly limited, the microcomputer 1 is used for controlling embedded devices, and the operation program of the CPU 2 is stored in the flash memory 3. RAM
Reference numeral 5 denotes a work area of the CPU 2 or a temporary data storage area.

The microcomputer 1 shown in FIG. 3 uses a single external power supply voltage Vcc supplied to the external power supply terminal Pvcc as an operating power supply. Pvss is a ground terminal. The potential supplied to the ground terminal is the ground voltage Vss. Although the external power supply voltage Vcc is not particularly limited, so-called 3 V and 5 V
V power supply (tolerance is ± 10%), 2.7V ~
A voltage in a range of 5.5 V is set as an allowable range of the external power supply voltage.

In FIG. 3, RES is a microcomputer reset terminal (reset signal), VppMON, Vpp
ssMON is a monitor terminal for the internal boosted voltage, and Pfwe is a write protection terminal for the flash memory 3. In particular, VppMON is for monitoring the internal positive boosted voltage, and VssMON is for monitoring the internal negative boosted voltage.

<< Flash Memory >> FIG. 4 shows an overall block diagram of the flash memory 3 and a control register 4. In FIG. 4, FLE0 in FIG.
1 is representatively shown. The other flash memory 3 indicated by FLE1 is exactly the same and is not shown.

In FIG. 4, 17 is a data bus, and 18 is an address bus. Although not particularly limited, the CPU 2, the RAM 5, and the flash memory 3, which are representatively shown, share the address bus 18 and the data bus 17. The control register 4 shown in FIG. 3 includes an erase block designation register EBR1 and a rewrite control register F in FIG.
LMCR1, reference voltage trimming register TRMR1,
TRMR2. Each control register EB
R1, FLMCR1, TRMR1, TRMR2 are CPU
2 made accessible. Register TRMR
1, the CPU access to the TRMR2 has the following restrictions.

In the memory cell array 30, a large number of nonvolatile memory cells are arranged. Non-volatile memory cells are
Although not particularly shown, it has a source, a drain, a floating gate, and a control gate, and the gate oxide film (insulating film) is thin so that a tunnel current due to a tunnel phenomenon can flow. The source is connected to the source line, the drain is connected to the bit line, and the control gate is connected to the word line. An X decoder (X-DEC) 31 decodes the X address signal taken into the address buffer 32 from the address bus 18 to form a word line selection signal. The word driver (WDRV) 33 drives the word line selected by the word line selection signal to a predetermined selection level according to the operation mode (write, erase, read, etc.). The bit line selected via a Y selector 34 is connected to a write circuit 35 or a sense amplifier 36. The sense amplifier 36 detects data read from the memory cell, and supplies data according to the logical value to the output buffer 37, and the output buffer 37 performs an output operation to the data bus 17 in accordance with a data output operation instruction. The write circuit 35 applies a write voltage corresponding to the write data supplied from the data bus 17 to the input buffer 38 to Y
This is applied to the bit line selected by the selector 34. A Y decoder (Y-DEC) 31 decodes a Y address signal taken into the address buffer 32 from the address bus 18 to form a selection signal of the Y selector 34. The source / substrate control unit 39 includes an erase block designation register EB
It controls the selection of the source line of the erase block specified by R1, and controls the substrate voltage of the memory cell array 30 according to the erase or write operation.

In FIG. 4, reference numeral 40 denotes a power supply circuit of the flash memory, which generates a high voltage for writing and erasing and an operating voltage for a reading system based on the single external power supply voltage Vcc. The power supply circuit 40 includes a reference voltage circuit, a read clamp power supply circuit, a boost clamp power supply circuit, a first positive booster circuit, a second positive booster circuit, a negative booster circuit, and various voltages formed by the above circuits. It has a group of voltage supply switches to be selectively supplied to the internal circuit of the flash memory 3.

The trimming control section 42 is a control circuit for adjusting the characteristics of the power supply circuit with respect to process variations and the like. Control data for the trimming control unit 42 is provided from the reference voltage trimming register TRMR1 and the boost voltage trimming register TRMR2. Various operation powers generated by the power supply circuit 40 are selected in accordance with the operation of the flash memory and supplied to the source control unit 39, the write circuit 35, the word driver 33, and the like. The power supply control unit 41 performs a writing sequence, an erasing sequence, and the like relating to power supply at this time. The power control unit 41 has a write sequencer, an erase sequencer, and the like. Control data for a write sequence or an erase sequence is given from the rewrite control register FLMCR1. The circuit block indicated by 43 is the flash memory 3
Other control logic.

FIG. 5 shows a configuration example of the memory cell array 30. Although not particularly limited, in the illustrated structure, the bit line is constituted by a main bit line 300 and a sub bit line 301, and the drain of the nonvolatile memory cell 302 is coupled to the sub bit line 301. The main bit line 300 and the sub bit line 301 are selectively turned on by the selection MOS transistor 303. The sources of the nonvolatile memory cells 302 are commonly connected to a predetermined source line 304 for each group. 305 is a word line, and 306 is a select line of the selection MOS transistor.

FIG. 6 shows an example of the voltage application state of the erase operation. The minimum unit of erasing is a block unit having a common source line. The erase select source line is -9.5 V, the select line 306 is -9.5 V, and the erase select word line is 9.5.
V, the erase unselected word line is set to 0V (ground potential Vss). As a result, electrons are injected into the floating gate of the nonvolatile memory cell 302 of the erase target block 307, and the threshold voltage of the nonvolatile memory cell is increased. That is, data is erased by utilizing the phenomenon of electron tunneling from the drain (source) and the channel to the floating gate via the gate insulating film.

FIG. 7 shows an example of the voltage application state of the write operation. Writing is performed for each word line. The write selection word line is -9.5 V, the write selection bit line is 6.5 V, the write non-selection bit line is 0 V, the write selection select line is 9.5 V, and the source line is open (floating). As a result, electrons are emitted from the floating gate of the nonvolatile memory cell 302 selected for writing, and the threshold voltage of the memory cell is lowered. That is, data writing is performed using the phenomenon of electron tunneling from the floating gate to the drain (source) and the channel portion via the gate insulating film.

FIG. 8 is a block diagram showing the operation power supply in each section of the flash memory. In FIG. 8, 3
What is indicated by 3Z is the driver (ZDRV) of the select line 306. The driver 33Z is supplied with a decode signal from a Z decoder (Z-DEC) 31Z that decodes an address signal assigned to block selection. The Z driver 33Z drives a select line according to a selection signal output from the Z decoder 31Z. 33Y
Is a Y select driver, which determines the level of the switch control signal of the Y selector 34. In FIG. 4, the Y select driver 33Y, the Z driver 33Z and the Z decoder 31Z are not shown.

FIG. 9 shows the meaning of the various operation power supplies shown in FIG. The relationship between the voltages of these various operation power supplies and the operation is illustrated in FIG. FIG. 11 shows the voltages that can be taken by the various operation power supplies. 9.5
V and 6.5V are generated by positive boost, and -9.5V
Is generated by negative boosting.

<< Power Supply Circuit >> FIG. 1 schematically shows a main part of the power supply circuit 40. The power supply circuit 40 clamps the output voltage to a first voltage Vfix (2.5 V) lower than the external power supply voltage Vcc (2.7 V to 5.5 V) using a reference voltage having a small power supply voltage dependency. It has a voltage clamp means 44, and has a booster circuit using the voltage Vfix (also called a clamp voltage Vfix) as an operation power supply. The booster circuit includes three charge pump circuits 4
5, 46, 47 and their common ring oscillator 48
Composed of The charge pump circuit 45 and the ring oscillator 48 constitute a first positive booster circuit, and form a 9.5 V positive booster voltage based on the clamp voltage Vfix. The charge pump circuit 46 and the ring oscillator 4
Reference numeral 8 denotes a second positive booster circuit, and the clamp voltage Vfix
To form a positive boosted voltage of 6.5V. The charge pump circuit 47 and the ring oscillator 48 form a negative booster circuit, and have a voltage of -9.5 based on the clamp voltage Vfix.
A negative boosted voltage of V is formed.

The voltage clamp means 44 forms a clamp voltage Vfix having a small power supply voltage dependency, and the clamp voltage Vfix is a single power supply voltage supplied from the outside within an allowable range of 2.7 V to 5.5 V. Since the voltage is clamped to a voltage lower than Vcc (2.5 V), the boosted voltages generated by the positive and negative booster circuits operated by the clamp voltage Vfix, that is, the write and erase voltages depend on the external power supply voltage Vcc. Not a stable voltage. In the configuration shown in FIG. 2 as a comparative example, since the operating power supply of the ring oscillator and the charge pump circuit is the external power supply voltage Vcc, the boosted voltage varies depending on the external power supply voltage Vcc.

<< Clamp Power Supply >> FIG. 12 shows an example of the voltage clamp means 44. The voltage clamping means 44 includes a reference voltage generation circuit 400, a first constant voltage generation circuit 401, a second constant voltage generation circuit (step-up clamp power supply circuit) 402, and a third low voltage generation circuit (read clamp power supply). Circuit) 403.

The reference voltage generation circuit 400 is a circuit that generates a reference voltage Vref having small power supply voltage dependency and low temperature dependency by utilizing the band gap of silicon or the like. The operation power supply of the reference voltage generation circuit 400 is Vcc. Since such a reference voltage generation circuit 400 is publicly known, its detailed circuit configuration is not shown. In this example, the reference voltage Vref is 1.4V ± 0.
3V.

The first constant voltage generation circuit 401 is a circuit that performs negative feedback control of the output circuit to the clamp voltage Vrefa using the reference voltage Vref as a reference voltage. In particular,
A source follower circuit constituted by an n-channel MOS transistor Q1 and a feedback resistor circuit (ladder resistor circuit) FBR1 is provided as an output circuit, and a CMO
The operational amplifier OP1 includes an S operational amplifier OP1, receives the reference voltage Vref at a non-inverting input terminal (+) of the operational amplifier OP1, receives a feedback signal from an output circuit at an inverting input terminal (−) of the operational amplifier OP1, and outputs the MO signal by the output of the operational amplifier OP1.
It controls the conductance of the S transistor Q1. The clamp voltage Vrefa is a constant voltage determined by the voltage dividing ratio of the feedback resistor circuit FBR1 and the reference voltage Vref. This clamp voltage Vrefa does not logically depend on the power supply voltage Vcc. According to this example, the feedback resistor circuit FB is controlled so that the clamp voltage Vrefa becomes 2.5 V.
It will be adjusted using R1.

A more detailed example of the first constant voltage generation circuit 401 is shown in FIGS. As shown in FIG. 16, the voltage dividing ratio of the feedback resistor circuit FBR1 is
10 makes it selectable. That is, the feedback resistor circuit FBR1 forms a trimming resistor circuit capable of adjusting the resistor division ratio. In FIG. 17, BIAS is a signal for biasing the current source transistors of the differential amplifier circuit and the output circuit, and is output from a bias circuit (not shown). FS
TBYW is used as a standby signal to determine the state of the internal node in the low power consumption mode of the microcomputer 1 and to cut off the useless current through path.

The second constant voltage generation circuit 402 is a circuit for performing negative feedback control of the output circuit to the clamp voltage VfixB using the clamp voltage Vrefa as a reference voltage. Specifically, a source follower circuit composed of an n-channel MOS transistor Q2 and a feedback resistor circuit FBR2 is provided as an output circuit, has a CMOS operational amplifier OP2, and is connected to a non-inverting input terminal (+) of the operational amplifier OP2 by the clamp. A voltage Vrefa is received, a feedback signal from an output circuit is received at an inverting input terminal (−) of the operational amplifier OP2, and the MOS is output by the output of the operational amplifier OP2.
It controls the conductance of the transistor Q2. The clamp voltage VfixB is set to a constant voltage determined by the voltage dividing ratio of the feedback resistor circuit FBR2 and the clamp voltage Vrefa. This clamp voltage Vrefa does not logically depend on the power supply voltage Vcc. According to this example, the voltage division ratio of the feedback resistor circuit FBR2 is determined so that the clamp voltage VfixB becomes 2.5V. The clamp voltage VfixB in FIG. 12 corresponds to Vfix shown in FIG.

The third constant voltage generation circuit 403 is a circuit that performs negative feedback control of the output circuit to the clamp voltage VfixA using the clamp voltage Vrefa as a reference voltage. Specifically, a source follower circuit including an n-channel MOS transistor Q3 and a feedback resistor circuit FBR3 is provided as an output circuit, has an operational amplifier OP2, and has the clamp voltage applied to a non-inverting input terminal (+) of the operational amplifier OP2. Receiving Vrefa, the feedback signal from the output circuit is received at the inverting input terminal (-) of the operational amplifier OP2, and the conductance of the MOS transistor Q2 is controlled by the output of the operational amplifier OP2. The feedback signal is 2.5V
Output n-channel MOS transistor Q4 or 4.0V output n-channel MOS transistor Q
Returned through 5. The clamp voltage VfixA is determined by the voltage dividing ratio of the feedback resistor circuit FBR2 and the clamp voltage Vrefa.
And the voltage is set almost constant. This clamp voltage Vrefa does not logically depend on the power supply voltage Vcc. According to this example, when the transistor Q4 is selected, the clamp voltage VfixA becomes 2.5V.
When the transistor Q5 is selected, the clamp voltage V
The feedback resistor circuit FBR2 is set so that fixA becomes 4.0V.
Are determined. The clamp voltage VfixA is used as a read-system operation power supply. Clamp voltage VfixA
Is set to 2.5 V or 4.0 V depending on the operation mode. For example, in a read operation, VfixA = 4.0 V is used as a word line selection level at the time of reading from the viewpoint of reducing word line disturbance. At this time, Vcc is used as the sense amplifier power supply. On the other hand, in the erase verify and the write verify, the power of the driver of the Y selector and the power of the sense amplifier are set to VfixA = V so that the write and erase levels do not depend on the power supply voltage Vcc.
2.5V is used.

The clamp voltage VfixB is used as an operating power supply for boosting a high voltage used for writing and erasing, and is separated from the clamp voltage VfixA used as a power supply for other read-related operations. A relatively large current is required for writing and erasing, and a relatively large current flows in the booster circuit for supplying it. Can minimize the influence of other circuits.

<< Boost Circuit >> FIG. 13 shows the charge pumps 45 and 46 as an example of first and second positive boost circuits.
And their peripheral circuits. Although not particularly shown, each of the charge pump circuits 45 and 46 has a plurality of boosting nodes in which a MOS transistor and a capacitance element are coupled, and generates a high voltage by the charge pumping action of the MOS transistor and the capacitor. Clock driver 4
Reference numerals 20 and 421 generate drive signals of a plurality of phases for causing the charge pump circuits 45 and 46 to perform the charge pump operation. The operating power supply of the clock drivers 420 and 421 is the clamp voltage VfixB. The drive signal switches the plurality of MOS transistors by shifting the phase and applies a regular voltage change to one electrode of the capacitor sequentially, whereby the drive signal is sequentially and regularly applied to one electrode of the capacitor. The voltage of the other electrode changed according to the change is sequentially transmitted to the subsequent stage via the MOS transistor. The drive signal is generated in synchronization with a clock signal CLK output from the ring oscillator 48.
Comparators 422 and 423 are provided to maintain the boosted voltages VPP6 and VPP9 generated by the charge pump circuits 46 and 45 at specified voltages. Comparator 4
22 and 423 are voltages VCMP6 and VPP obtained by dividing the boosted voltages VPP6 and VPP9 by the resistance circuits 428 and 429, respectively.
CMP9 is supplied and compared with the clamp voltage Vrefa. Voltages VCMP6 and VCMP9 are the regulated voltages (VPP6 = 6.5V, VPP9 = 9.5V)
Is set to the voltage Vrefa or more. Comparator 42
2, 423 inverts the detection signals 424, 425 from low level to high level by detecting the state. Detection signals 424 and 425 are OR gates 426 and 4
The logical sum of the clock signal CLK and the clock signal CLK is calculated by the clock driver 27 and supplied to the clock drivers 420 and 421. Therefore, when the boosted voltages VPP6 and VPP9 reach the prescribed voltages, the outputs of the OR gates 426 and 427 are fixed at a high level, and during that time, the charge pump circuits 45 and 46 are fixed.
Is temporarily stopped. 430,431
Is a switch circuit that is cut off when the boost operation is completed.

FIG. 14 shows a charge pump circuit 47 as an example of a negative and positive booster circuit and its peripheral circuits. Although not particularly shown, the charge pump circuit 47 has a plurality of boosting nodes each having a MOS transistor and a capacitive element coupled thereto, and generates a negative high voltage by the charge pumping action of the MOS transistor and the capacitor. The clock driver 434 generates a multi-phase drive signal for causing the charge pump circuit 47 to perform a charge pump operation. The operating power supply of the clock driver 434 is the clamp voltage VfixB. The drive signal switches the plurality of MOS transistors by shifting the phase and applies a regular voltage change to one electrode of the capacitor sequentially, whereby the drive signal is sequentially and regularly applied to one electrode of the capacitor. The voltage of the other electrode changed according to the change is sequentially transmitted to the subsequent stage via the MOS transistor. The drive signal is applied to the ring oscillator 4 shown in FIG.
8 is generated in synchronization with the clock signal CLK output from the clock signal CLK. A comparator 435 is provided to maintain the negative boosted voltage VPPMNS9 generated by the charge pump circuit 47 at a specified voltage. The comparator 435 is supplied with a voltage VPCMP9 obtained by dividing the boosted voltage VPPMNS9 by a resistance circuit 436 and comparing the voltage with the ground potential Vss. The voltage VPCMP9 is the boosted voltage VPPNMS
Becomes a prescribed voltage (VPPMNS9 = -9.5V), the voltage is made lower than the ground voltage Vss. The comparator 435 inverts the detection signal 437 from a low level to a high level by detecting the state. The detection signal 437 is ORed with the clock signal CLK by the OR gate 438 and supplied to the clock driver 434.
Therefore, when the boosted voltage VPPMNS9 reaches a specified voltage, the output of the OR gate 438 is fixed at a high level, and during that time, the boosting operation by the charge pump circuit 47 is temporarily stopped. A switch circuit 439 is cut off when the boost operation is completed.

The negative boosted voltage VPPMNS9 output from the charge pump circuit 47 is connected to the monitor terminal Vss.
It can be observed from MON. The circuit indicated by 440 is a switch circuit that is turned on in the test mode. The positive boosted voltages VPP6 and VPP9 can be selectively observed from a monitor terminal VCPMON as illustrated in FIG. Reference numerals 441 and 442 denote positive boosted voltages VPP6 and VPP9 as monitor terminals VCPPM.
This is a switch circuit that transmits ON. MONE is an enable signal for instructing monitoring of the boosted voltage by the monitor terminal VppMON at a high level, and MONS is VPP6.
Or a signal instructing which of VPP9 is to be monitored, and the switch circuits 441 and 442 are exclusively turned on in accordance with the states of the signals MONE and MONS in the test mode, whereby the desired boosted voltage VPP6 or VPP9 can be observed.

In FIG. 13, what is indicated by OSE is a signal for instructing the ring oscillator 48 to start an oscillating operation. The signal indicated by VPE1 is a signal for instructing the clock driver 421 and the charge pump circuit 46 to start a boosting operation. The clock driver 420 and the charge pump circuit 4 are denoted by VPE2.
5 is a signal for instructing the start of the step-up operation for No. 5. FIG.
The signal indicated by VPE3 in FIG. 4 is a signal for instructing the clock driver 434 and the charge pump circuit 47 to start a boosting operation.

The three types of clock drivers 420, 4
21 and 434 are clamp power supplies V whose operating power supplies are common.
fixB, and uses one ring oscillator 48 as a clock source. At this time, as illustrated in FIG. 13, the clock driver 421 of the charge pump circuit 46 receives the clock signal CL via the delay circuit 444.
K is supplied. The clock signal CLK is supplied to the clock driver 420 of the charge pump circuit 45 via the delay circuits 444 and 445 of two stages in series. On the other hand, FIG.
The clock signal CL is supplied to the clock driver 434 of the charge pump circuit 47 without using a delay circuit as shown in FIG.
K is supplied. Therefore, the clock signal C output from the ring oscillator 48 as illustrated in FIG.
LK are sequentially shifted in phase to generate clock signals 434, 421, and 4 as a -9.5V step-up clock signal, a + 6.5V clock signal, and a + 9.5V clock signal.
20. Clock drivers 434, 421,
The charge pump circuits 47, 46, 4 formed by 420
5 are synchronized with the clock signals whose phases are shifted from each other. That is, the clock drivers 434 and 42
Reference numerals 1 and 420 indicate that the transistor is switched in synchronization with the change of the clock signal, and the current flowing in the circuit is changed in synchronization with the switching operation. Therefore, since the phases of the clock signals supplied to the clock drivers 434, 421, and 420 are shifted, the clock driver 43
4, 421, and 420, the instantaneous current change that occurs is reduced, so that the load on a power supply circuit such as the boost clamp power supply circuit 402 can be reduced. This contributes to stabilization of the boosting operation and further to stabilization of the writing and erasing operations.

<< Change of Substrate Bias Voltage of Charge Pump Circuit >> FIG. 19 shows an example of the negative voltage boosting charge pump circuit 47 and clock driver 434.
Charge pump circuit 47 only partially shown in FIG.
Are boosted nodes indicated by NP. A p-channel type M for charge transfer between adjacent boosting nodes
An OS transistor Q10 is provided. Further, one electrode of a charge pump capacitance element C1 is coupled to each boost node NP. MOS transistor Q
One electrode of another capacitive element C2 is coupled to the gate of 10. P-channel transfer MOS transistors Q11 and Q12 are arranged in parallel between the gate of the MOS transistor Q10 and the boosting node NP in the preceding stage. The gate of the MOS transistor Q11 is connected to the boosting node NP, and the gate of the MOS transistor Q12 is connected to the MOS. It is coupled to the gate of transistor Q10. MOS transistors Q13 and Q14 are transistors for initializing boosting node NP. The capacitance value of the capacitance element C1 is larger than the capacitance value of C2. As described above, the charge pump circuit 47 is connected to the MOS transistor Q1.
A plurality of unit circuits each including a set of 0 to Q13 and capacitive elements C1 and C2 are connected in series.

The clock driver 434 sequentially delays the clock signal CLK to generate three-phase clock signals φa to φc having different phases, and generates the three-phase clock signals φa to φc.
It outputs four drive signals DS1 to DS4 based on φc. FIG. 20 shows the clock driver 43 shown in FIG.
Clock signals .phi.a to .phi.
c and the waveforms of the drive signals DS1 to DS4.

The drive signals DS1 and DS2 are alternately supplied to the other electrode of the capacitive element C1.
S3 and DS4 are alternately supplied to the other electrode of the capacitive element C2. For example, in a state where the MOS transistor Q10 is turned off by the high level (t1) of DS4 and the level of the boosting node is raised by the high level (t1) of DS2, the boosting node NP of the preceding stage is set to the DS level.
1 is lowered by the low level (t2) of the MOS transistor Q1 via the transistor Q11.
The level of the gate of 0 is also lowered, and immediately after that, the level of the boosting node NP is further lowered by changing DS3 to the low level (t3). The lowered level is applied to the next-stage boosting node N via the MOS transistor Q10.
Moved to P. By such a charge pump operation, the voltage VPPMNS9 is gradually increased to a negative voltage.

The NOR gate 450 shown in FIG. 19 replaces the function of the OR gate 438 described with reference to FIG.

The drive signals D1 to D4 are connected to the ground potential Vss.
And the clamp voltage VfixB. At the start of the boosting operation, the MOS of the charge pump circuit 47
A clamp voltage VfixB is applied to the gates of the transistors Q10, Q11, Q12. As the boosting operation proceeds, the gate voltage decreases. Therefore, at the start of the boosting operation, these MOS transistors Q1
Unless the substrate bias voltage common to 0, Q11, and Q12 is at least set to the clamp voltage VfixB, the pn junction of the transistor may be undesirably set to a forward bias state and cause a malfunction.

In this example, the MOS transistor Q1
0, Q11 and Q12 are formed in a well region common to them. These MOS transistors Q10, Q1
1 and Q12, the substrate bias voltage (well bias voltage) becomes the clamp voltage Vfix at the start of the boosting operation.
B, and is switched to the ground voltage Vss on the way.

FIG. 21 shows a configuration for switching the substrate bias voltage of the charge pump circuit.
In FIG. 21, reference numeral 460 denotes switch means for switching the substrate bias voltage to the clamp voltage VfixB or the ground voltage Vss. The switch state of the switch means 460 is not particularly limited, but is determined by the state of the output terminal Q of the set / reset type flip-flop (SR-FF) 461. The reset terminal R of the flip-flop 461 has a boost enable signal VPE
The inversion signal of No. 3 is supplied, and the reset state is set when the boosting operation is not performed. In this reset state, the switch means 460 selects the clamp voltage VfixB as the substrate bias voltage 462. The set terminal S of the flip-flop 461 is the output signal 4 of the comparator 463.
Receive 64. The comparator 463 is connected to the resistance circuit 43
It is monitored whether the potential of the voltage dividing point ND1 of No. 6 is equal to or lower than the ground potential Vss. The voltage dividing point ND1 is set to the ground potential Vss when the boosted voltage VPPMNS9 becomes a predetermined voltage lower than the ground potential Vss. Therefore, when the boosted voltage Vss becomes a predetermined voltage lower than the ground potential Vss, the flip-flop 461 is set, whereby the switch means 460 selects the ground voltage Vss as the substrate bias voltage 462. In FIG. 14, the switch means 460 is constituted by an inverter using the clamp voltage VfixB and the ground voltage Vss as operating power supplies.

The substrate bias voltage 46
2 is switched to the ground voltage Vss lower than the clamp voltage VfixB, the threshold voltage of the MOS transistors Q10, Q11, Q12 becomes smaller due to the so-called substrate bias effect, whereby the MOS transistors Q10, Q11, Charges are easily transferred via Q12. Therefore, the operating power supply (Vf
ixB = 2.5V) and the target boosted voltage (VP
The efficiency of the negative voltage boosting operation having the largest level difference (PMNS9 = -9.5 V) can be improved, and the time required to obtain the specified negative boosted voltage can be shortened.

For example, FIG. 22 shows a transition state of the boosted voltage VPPMNS9 in the negative voltage boosting operation. In the figure, (a) shows the boosted voltage VPPM when the substrate bias voltage is fixed to the clamp voltage VfixB without switching.
The transition state of NS9 is shown. (B) shows a transition state when the substrate bias voltage is switched on the way. Compared with (a), in the case (b), the efficiency of the negative voltage boosting operation is improved, and the time required to obtain the specified negative boosted voltage is shortened.

When the substrate bias voltage is once set to the ground potential Vs
When switched to s, the flip-flop 461 maintains the set state even if the output of the comparator 463 is subsequently inverted. That is, it can be said that the flip-flop 461 has a hysteresis characteristic that maintains the substrate bias voltage at the ground potential Vss even when the boosted voltage VPPMNS9 swings up and down after the switching of the substrate bias voltage. Such a hysteresis characteristic is caused by the SR flip-flop 461
Alternatively, a hysteresis comparator may be used for the comparator 463.

As shown in FIG. 22, the boosted voltage in the course of boosting by the charge pump is an MO for the charge pump.
It swings up and down in synchronization with the switching operation of the S transistors Q10, Q11 and Q12. The flip-flop 461
The substrate bias voltage of the charge pump circuit 47 is switched by an output signal of a circuit having a hysteresis characteristic represented by the equation (1), whereby the substrate bias voltage once changed due to the ripple component of the negative boosted voltage is restored to the original substrate bias. Undesired oscillation of the substrate bias that is changed can be prevented.

<< Software Trimming of Power Supply Circuit >> The feedback resistance circuit FBR1 of the constant voltage generation circuit 401 shown in FIGS. 12 and 16, and the resistance circuit 43 shown in FIG.
Reference numeral 6 denotes a trimmable resistor circuit (trimming resistor circuit). The configuration is as described with reference to FIG.
This is a circuit such as a so-called ladder resistance circuit that turns on one of the many switches 410 to determine a voltage dividing point to be adopted as an output node. In the feedback resistance circuit FBR1, the feedback resistance value is determined according to the resistance voltage division ratio at the output node selected by the switch 410. Similarly, in the resistance circuit 436, a voltage corresponding to the resistance division ratio at the node (ND1) selected by the switch 410 is supplied to the comparator 463. The trimming of the feedback resistor circuit FBR1 is based on the original voltage Vref of the power supply circuit 40 with respect to process variations.
a to the required level, and clamp voltage Vfix
A and VfixB have the meaning of setting the desired voltage. The trimming of the resistor circuit 436 on the negative boosting circuit side is performed by the negative boosting voltage VPP having the largest boosting width.
This has the significance of optimizing the negative boost operation by making the boost level control and the well bias voltage switching point for the MNS 9 particularly adjustable. The resistance circuit 4 on the positive booster circuit side
28 and 429 may be trimmed.

The selection signal of the switch 410 for determining the resistance voltage dividing ratio at the output node of the resistor circuit (also called the trimming resistor circuit) FBR1 436 is shown in FIG.
Are generated by the selector 470 as illustrated in FIG. According to the example of FIG. 23, the selector 470 decodes the trimming information and sets one switch selection signal to a selection level. The selector 470 is a trimming resistor circuit FBR
1 and a trimming resistor circuit 436, which are included in the trimming control unit 42 shown in FIG.

The trimming information of the resistor circuit FBR1 is transmitted from the reference voltage trimming register TRMR1 to the resistor circuit FBR.
The trimming information of the resistor circuit 436 is supplied from the boosted voltage trimming register TRMR2 to the selector 470 of the resistor circuit 436. FIG.
5, the reference voltage trimming register T
The trimming information (reference voltage trimming information) set in the RMR1 is VR0 to VR4, TEVR. The trimming information (boosted voltage trimming information) set in the boosted voltage trimming register TRMR2 is VM0 to VM.
4, TEVM.

As exemplified in FIG. 23, a dedicated storage area 300 for storing the reference voltage trimming information and the boosted voltage trimming information is allocated to the memory cell array 30 of the flash memory 3. According to this example, the information in the area 300 is synchronized with the reset operation of the microcomputer 1 by the registers TRMR1 and TRM.
Transferred to R2. This transfer control is not particularly limited, but is automatically performed by hardware as shown in FIG. That is, when the reset signal RST is asserted, the control unit 43 of the flash memory 3 controls the address buffer 32, the sense amplifier 36, the output buffer 37, and the like to read the data in the area 300 onto the data bus 17, and The data in the area 300 is automatically read out. On the other hand, the register TRMR
1 and TRM2 are controlled so that data can be input from the data bus 17 in synchronization with the assertion of the reset signal RST.
As a result, the data in the area 300 is stored in the register TRMR.
1, automatically transferred to TRMR2.

The reference voltage trimming information and the boosted voltage trimming information are determined at the time of device test in order to absorb process variations and the like. The data transfer described with reference to FIG. 24 is also performed when the microcomputer 1 is set to the test mode. In the initial stage of the device test, the flash memory 3 is in the written state (the trimming information in the area 300 is in the state of all bits having the logical value “0”) in the wafer completed state, so the trimming information in the registers TRMR1 and TRMR2 is in the all-bits logical state. The value is set to “0”. In the test mode, the registers TRMR1 and TRMR2 are made readable and writable by the CPU 2. At the time of the device test, the positive and negative boosted voltages are monitored from the monitor terminals VppMON and VssMON, and the reference voltage trimming information and the boosted voltage trimming information are determined so that the boosted voltages become specified voltages. The reference voltage trimming information and the boosted voltage trimming information thus determined are stored in a predetermined area 300 of the flash memory 3 by the CPU 2 in a predetermined test mode. Then, the microcomputer 1
Is reset, the power supply circuit 40 is controlled in accordance with the optimally determined reference voltage trimming information and boosted voltage trimming information. Access to the predetermined area 300 is prohibited in a normal operation mode (or a user mode). If the predetermined test mode is set again, it is possible to access the area and reset the reference voltage trimming information and the boosted voltage trimming information. Device tests by semiconductor manufacturers include not only wafer-level tests but also factory tests. It is also possible to set reference voltage trimming information and boosted voltage trimming information at each test stage. It is assumed that the reference voltage trimming information and the boosted voltage trimming information are finally written in the predetermined area 300 after the test at the shipping stage.

According to this example, when the wafer of the microcomputer is completed, the flash memory 3 is in a write state (for example, a state in which the threshold voltage is a low logical value “0”). At the time of shipment of the microcomputer, the flash memory is in an erased state (for example, a state in which the threshold voltage is a high logical value "1"). It is desirable to prevent the trimming state between the writing state and the erasing state from being extreme, so that there is no large difference in the output voltage of the power supply circuit. For example, after the test at the shipping stage, the reference voltage trimming information and the boosted voltage trimming information are finally stored in the predetermined area 30.
When writing 0, if there is a significant difference that cannot be ignored between the boosted voltage initially obtained in the test at the wafer stage and the boosted voltage initially obtained in the test at the time of shipping, the test or inspection efficiency May be reduced. In the case of a microcomputer chip that does not require trimming, it can be shipped in an erased state.

For this purpose, the selector 470 is provided with the configuration shown in FIG.
As exemplified in FIG. 3, a selection is made such that the trimming position when the trimming adjustment information is all-bit logical value “1” and the trimming position when the trimming adjustment information is all-bit logical value “0” are selected so as to be adjacent to each other. Has logic. Thereby, the difference between the output voltage of the power supply circuit can be minimized both when the flash memory 3 is set to the writing state in the wafer completed state and when the flash memory is set to the erasing state at the time of shipment. . For example, according to the example of FIG. 23, when the flash memory 3 is in a write state (the trimming information in the area 300 is a state in which all bits have the logical value “0”) in the wafer completed state, “00”
When the switch is selected at the trimming position indicated by "0" and the flash memory is in an erased state (trimming information in the area 300 is a state in which all bits have the logical value "1") at the time of shipment of the microcomputer, it is indicated by "111". A switch is selected at the trimming position.

As is apparent from FIG. 12, the trimming adjustment information also affects the read voltage of the flash memory 3. That is, the feedback resistor circuit F to be trimmed
The clamp voltage Vrefa output from the constant voltage circuit 401 including the BR1 is used as a reference voltage of the read clamp power supply circuit 403 that generates a read power supply. At this time, the transfer of the trimming adjustment information from the flash memory 3 to the register TRMR1 is performed when the read access to the flash memory 3 can be performed by spending a longer time than the specified access time of the read operation. Is desirable. This is because, even when the read voltage is slightly lower than a prescribed value, data can be accurately read from the memory array by increasing the read time. At this point, the microcomputer 1 performs the initial transfer of the trimming adjustment information in synchronization with the reset operation. Therefore, the fluctuation of the internal voltage until the trimming operation is determined can be determined during the reset,
After the reset operation, the read operation can be stabilized. When the trimming adjustment information affects only the write and erase voltages of the flash memory 3, the trimming adjustment information may be transferred during the reset period or before the first vector fetch (instruction fetch) after reset release. .

<< Rewrite Sequence for Flash Memory >> Rewrite control register FLMCR1 and erase block designation register EBR1 of the flash memory 3
A detailed example is shown in FIG. Bits EB0 to EB7 of the erase block designation register EBR1 are erase block designation data.

The rewrite control register FLMCR1 has P,
It has control bits of E, PV, EV, PSU, ESU, SWE, and FWE, and their true values are not particularly limited, but are set to the logical value “1”.

The rewrite enable bit SWE indicates a preparation state for the boosting operation by the power supply circuit 40. For example, when the rewrite enable bit SWE is set to the logical value "1", the control signal OSE shown in FIG. 13 is asserted, whereby the ring oscillator 48 starts oscillating and outputs the clock signal CLK. Further, the step-up clamp power supply VfixB is activated.

The write setup bit PSU instructs the power supply circuit 40 to start a boosting operation for writing. According to this example, the write setup bit PS
When U is set to the logical value "1", the control signals VPE1, VPE2 and VPE3 shown in FIG. 13 are asserted, and the operations of the clock drivers 420, 421 and 434 and the charge pump circuits 45, 46 and 47 are started. Voltage VPP
6, VPP9 and VPPMNS9 are +6.5 V, +9.5
The boost operation to V, -9.5V is started. The supply of the clock signal CLK from the ring oscillator 48 is premised on the fact that the boosting operation is performed substantially.

The write enable bit P instructs the start of a write operation using the boosted voltages VPP6, VPP9 and VPPMNS9.

The erase setup bit ESU instructs the power supply circuit 40 to start a boosting operation for erasing. According to this example, when the erase setup bit ESU is set to the logical value "1", the control signal VPE2 shown in FIG.
And the control signal VPE3 shown in FIG. 14 is asserted,
The operations of the clock drivers 420, 434 and the charge pump circuits 45, 47 are started, and the voltages VPP9, VPPM
NS9 starts boosting operation to + 9.5V and -9.5V. The supply of the clock signal CLK from the ring oscillator 48 is premised on the fact that the boosting operation is performed substantially.

Erasure enable bit E has a boosted voltage VP
P9 and VPPMNS9 are instructed to start an erasing operation.

It takes a considerable amount of time to obtain a specified boosted voltage by the boosting means, and the time is affected by process variations. Write and erase operations must be started after the boosted voltage reaches the specified voltage. At this time, the time from the start of the boosting operation to the start of writing can be determined by the time from when the bit PSU is set to the logical value “1” to when the bit P is set to the logical value “1”. . Similarly, the time from the start of the boosting operation to the start of erasing can be determined by the time from when the bit ESU is set to the logical value “1” to when the bit E is set to the logical value “1”. . The setting of those bits is C
This is realized by executing software by the PU2. This makes it possible to reduce hardware such as a timer for managing the timing at which erasing or writing is actually started after an erasing or writing operation is instructed. Further, such a time setting can be arbitrarily determined according to the circuit characteristics.

On the condition that the rewrite enable bit SWE is a true value, the start of the boosting operation by the erase setup bit ESU and the write setup bit PSU can be substantially accepted. Rewrite enable bit SWE
Is executable on condition that is a true value. Therefore, it is useful to prevent a situation in which the flash memory 3 is undesirably rewritten due to a runaway of the CPU 2 or the like.

The value of the protect bit FWE of the rewrite control register FLMCR1 is set according to the state of the external terminal Pfwe. FWE is a read-only bit. The protect bit FWE performs an interlock that enables the boost enable bit SWE to be set to the logical value "1", provided that it is a true value, for example, the logical value "1". That is, the boost enable bit S
Protect bit FW as one of the WE initialization signals
E is used. Only when FWE = 1, the boost enable bit SWE can be set / cleared. When FWE = 0, the boost enable bit is in the initial state. For example, a corresponding signal line from a data bus and the protect bit FW
A not-shown AND gate for taking a logical AND with E may be provided, and the boost enable bit SWE bit may be an output of the AND gate. Thereby, an interlock can be realized. By adding the interlock by the protect bit FWE, the rewrite protection by the SWE and the FWE can be doubled, and the reliability of preventing the unwanted rewriting of the flash memory 3 can be further improved.

FIGS. 26 and 27 show an example of a control flowchart of the erase operation by the CPU 2. FIG. CPU2
Sets the SWE bit of the register FLMCR1 to the logical value “1”.
(S1). In order to enable this setting, it is necessary that a signal of logic value "1" is applied to the external terminal Pfwe and the protection bit FWE is set to logic value "1". This causes the ring oscillator to start oscillating. Then, n = 1 is assigned to an appropriate register (S2), and an erase block is set in the register EBR1 (S3). Next, the logic value "1" of the ESU bit of the register FLMCR1 is set (S4). Thus, the clock drivers 420 and 434 and the charge pump circuit 45,
The boosting operation by 47 is started. After a certain time,
When the E bit of FLMCR1 is set to the logical value "1", the erasing operation is started (S5). When the E bit of FLMCR1 is cleared to a logical value "0" after the end of the erasing operation, the erasing operation is stopped (S6). And FLM
The ESU bit 2 of CR1 is cleared to the logical value “0” to stop the boosting operation (S7).
By setting the V bit to a logical value "1" (S
8) Erase verify for the erase operation is performed. In the erase verify operation, after performing dummy write (S9) to the verify address and reading of the verify data (S10), it is determined whether or not the read verify data has the logical value "1" of all bits (S1).
1). If the logical value of all bits is "1", address increment is performed until the last address is reached (S1).
2, S13), the above processing is repeated for each address increment. If the data read in S11 is not the logical value "1", the erasing operation is insufficient, so the EV bit is cleared (S14), and if the number of repetitions of erasing does not reach the upper limit (N), (NG in S15), the process returns to S4 again to advance the erased state. If the processing has progressed to the last address in S12, the erase verify is normally completed. In S15, when the number of times of erasing has reached the upper limit, the erase verify is abnormally terminated.

FIGS. 28 and 29 show an example of a control flowchart of the write operation by the CPU 2. CP
U2 sets the SWE bit of the register FLMCR1 to a logical value "1" (T1). In order to enable this setting, it is necessary that a signal of logic value "1" is applied to the external terminal Pfwe and the protection bit FWE is set to logic value "1". This causes the ring oscillator to start oscillating. Then, n = 1 is substituted into an appropriate register (T2), and an appropriate flag is cleared (= 0).
(T3). Then, for example, 32 bytes of write data are continuously written to the flash memory 3 (T4).
The write data is held in a data register included in the write circuit of the flash memory 3. Next, register FL
The logical value “1” of the PSU bit of MCR1 is set (T
5). This allows the clock drivers 420, 421,
434 and the charge pump circuits 45, 46, 47 start a boosting operation. After a certain time, FLMCR
When the P bit of 1 is set to the logical value "1", the write operation is started (T6). After the end of the write operation, F
When the P bit of LMCR1 is cleared to logical value "0",
The write operation is stopped (T7). And FLMC
The PSU bit 2 of R1 is cleared to the logical value “0” to stop the boosting operation (T8).

Thereafter, by setting the PV bit of FLMCR1 to the logical value "1" (T9), the write verify for the write operation is performed. In the write verify operation, after performing a dummy write (T10) to the verify address and reading the verify data (T11), rewrite data is calculated based on the read verify data and the original data of the write, and the calculated rewrite data is calculated. It is determined whether the write data is a logical value “1” of all bits (T12). The calculation of the rewrite data is performed as shown in FIG. If the rewrite data is all bits “1”, the rewrite data is
M (T13) and increments the address until the verification of the 32-byte data is completed (T1).
4, T15), the above processing is repeated for each address increment. If the rewrite data is not all bits "1" at step T12, the flag is set to "1" (T16), and the process proceeds to step T14. 32
When the byte verify operation is completed, the PV bit is cleared (S17), and the flag is determined (T1).
8). If flag = 0, writing of 32 bytes is normal, so the SWE bit is cleared (T19),
The write operation ends. Fl in step T18
If ag = 1, it is determined whether the number of times of writing has not reached the predetermined upper limit N (T20). If the number of writings has reached the predetermined value, the SWE bit is cleared (T21), and the process ends abnormally. If the number of repetitions of the write operation has not reached the upper limit (N), the counter n is incremented (T22), and the process returns to step T3.

FIG. 31 shows an example of a word line drive voltage switching method for reducing the load on the internal circuit due to the application of a high voltage required for writing. Schematically,
The operating voltage is switched after the word line is once set to the ground potential Vss. That is, when the boost operation of the write booster circuit is instructed by the PSU bit, all the word lines are forced to the ground potential Vss during the period shown in FIG. Next, during the period shown in FIG. 31C, the power supplies VPPX2, VSSXW, VS of the word driver WDRV are used.
SXS are each switched to the ground potential Vss. Next, as described in the address control column, the polarity of the word line selection is inverted. For example, the selection level of an X address decoder that forms a word line selection signal based on an address signal is logically inverted from a high level (during a read operation) to a low level (during a write operation). Thereafter, as shown in FIG. 31E, the power supply of the word driver is switched to the power supply for writing. Similarly, when writing is completed, all the word lines are forced to the ground potential Vss, the power supplies VPPX1, VSSXW and VSSXS of the driver are switched to the ground potential Vss, and the polarity of the word line selection logic is changed.
Switch the power supply. The power supply is switched by the power supply circuit 40.
The control is performed by a write sequencer of the power supply control unit 41.

Although the invention made by the inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and can be variously modified without departing from the gist of the invention. No.

For example, the external single power supply is 2.7 to 5.5 V
It is not limited to. The boost voltage is 6.5V, 9.5V,-
It is not limited to 9.5 V and can be changed. Similarly, the clamp voltage is not limited to 2.5V. Furthermore, the voltage application modes of writing and erasing are not limited to the above. The configurations of the booster circuit and the clamp circuit can be changed as appropriate. If the current supply capability is large, it is possible to use a common clamp power supply for the read system and the boost system. The built-in module of the microcomputer can be appropriately changed. The flash memory can adopt an appropriate circuit format such as NOR and AND. The flash memory is not limited to a use replacing the program memory, and may be used exclusively for data storage.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer for controlling the installation of equipment as a background of application has been described. However, the present invention is not limited to this. The present invention can be widely applied to semiconductor integrated circuits such as microcomputers for general use and other dedicated controller LSIs.

[0093]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the voltage clamping means forms a voltage having a small power supply voltage dependency, and its voltage level is clamped to a voltage lower than a single power supply voltage supplied from outside within an allowable range, The boosted voltage generated by the booster operated by the clamp voltage, that is, the write and erase voltages does not depend on the external power supply voltage. Therefore, erasing and writing of the built-in nonvolatile memory can be performed in a relatively wide external power supply voltage range including low-voltage operation.
Moreover, since this can be achieved with a single external power supply voltage, the usability of a semiconductor integrated circuit having a built-in nonvolatile memory can be improved.

When the boosted voltage reaches a predetermined level, the efficiency of the boosting operation can be improved by changing the substrate bias voltage common to the MOS transistors that perform the charge pump.

By providing a hysteresis characteristic of maintaining the substrate bias voltage at the switched voltage even if the boosted voltage fluctuates up and down after the switching of the substrate bias voltage, the boosted voltage in the process of being boosted by the charge pump is used for the charge pump. It is possible to prevent the substrate bias voltage from oscillating due to the influence of ripple components when the MOS transistor swings up and down in synchronization with the switching operation of the MOS transistor.

By shifting the operation phase of each charge pump circuit, the instantaneous voltage drop of the power supply can be reduced when a plurality of charge pump circuits are operated with the same power supply.

By enabling the output voltage of the voltage clamp means to be trimmed by the value of the register means receiving the transfer of the trimming adjustment information from the specific area of the nonvolatile memory, the trimming can be performed freely by software, and the chip-by-chip It is also possible to absorb the effects of process variations.

By transferring the trimming adjustment information to the register means in synchronization with the reset operation of the semiconductor integrated circuit, a change in the internal voltage until the trimming operation is determined can be determined during the reset, thereby improving reliability. Can be.

If the central processing unit makes the register means accessible in the test mode, the trimming information can be easily determined in the test mode.

The completed state of the wafer of the semiconductor integrated circuit is a write state (for example, a state of a logic value “0” with a low threshold voltage), and the shipment of the semiconductor integrated circuit is an erased state (for example, a state of a logic value with a high threshold voltage “0”). 1), the trimming position when the trimming adjustment information is all-bit logical value “1” and the trimming position when the trimming adjustment information is all-bit logical value “0” are selected to be adjacent to each other. By adopting such selection logic, it is possible to prevent the trimming state between the writing state and the erasing state from becoming extreme, so that there is no large difference in the output voltage of the voltage clamp means.

By realizing the management for starting writing or erasing after obtaining the specified boosted voltage by the boosting means by software by the central processing unit using the write setup bit and the erase setup bit, hardware such as a timer is realized. Can be reduced.

The control register is provided with a rewrite enable bit for instructing a preparation state for the boosting operation by the boosting means. On condition that the rewrite enable bit is a true value, an instruction by the erase setup bit and the write setup bit is provided. By making it possible to accept, a write or erase operation can be performed on condition that the rewrite enable bit is a true value. Help prevent.

The control register adds a protect bit to which a value according to the state of the external terminal is set, and the protect bit can set the boost enable bit to a true value on condition that it is a true value. When the interlock is performed, the reliability of preventing undesired rewriting of the nonvolatile memory can be further improved.

If the applied voltage is switched after the word line or the like is once set to the ground potential, it is possible to reduce the load on the internal circuit due to the application of the high voltage necessary for erasing or writing.

[Brief description of the drawings]

FIG. 1 is a block diagram schematically showing a main part of a power supply circuit.

FIG. 2 is a block diagram showing a comparative example of FIG.

FIG. 3 is a block diagram of a microcomputer according to an example of the present invention.

FIG. 4 is an overall block diagram of a flash memory built in the microcomputer.

FIG. 5 is a circuit diagram showing a configuration example of a memory cell array.

FIG. 6 is a circuit diagram showing an example of a voltage application state of an erase operation.

FIG. 7 is a circuit diagram showing an example of a voltage application state of a write operation.

FIG. 8 is a block diagram showing an operation power supply in each section of the flash memory.

9 is an explanatory diagram showing the meaning of various operation power supplies shown in FIG.

FIG. 10 is an explanatory diagram showing a relationship between voltages of various operation power supplies shown in FIG. 8 and operations.

FIG. 11 is an explanatory diagram that arranges and shows voltages that can be taken by various operation power supplies in FIG. 8;

FIG. 12 is an example circuit diagram of a voltage clamping unit.

FIG. 13 is an example circuit diagram of first and second positive booster circuits.

FIG. 14 is an example circuit diagram of a negative and positive booster circuit.

FIG. 15 is an explanatory diagram of a circuit that enables selective monitoring of a positive boosted voltage.

FIG. 16 is an explanatory diagram of a trimming resistance circuit of the first constant voltage generation circuit.

FIG. 17 is a detailed example circuit diagram of a first constant voltage generation circuit.

FIG. 18 is an explanatory diagram of a waveform of a boost operation clock signal.

FIG. 19 is an example circuit diagram of a charge pump circuit and a clock driver for boosting a negative voltage.

20 is an explanatory diagram of waveforms of a clock signal and a drive signal generated by the logic configuration of the clock driver shown in FIG. 19;

FIG. 21 is a block diagram schematically showing a configuration for switching the substrate bias voltage of the charge pump circuit.

FIG. 22 is an explanatory diagram showing a transition state of a boosted voltage in a negative voltage boosting operation.

FIG. 23 is a conceptual diagram of a trimming method in a trimming resistor circuit.

FIG. 24 is an explanatory diagram of a method of transferring trimming adjustment information from a flash memory to a control register in synchronization with a reset operation of a microcomputer.

FIG. 25 is an example format diagram of a control register.

FIG. 26 is a flowchart showing a part of the erase operation control by the CPU.

FIG. 27 is a flowchart showing the rest of the erase operation control by the CPU.

FIG. 28 is a flowchart showing a part of write operation control by the CPU.

FIG. 29 is a flowchart showing the rest of the write operation control by the CPU.

FIG. 30 is an explanatory diagram of a calculation method of rewrite data.

FIG. 31 is a timing chart showing an example of a word line drive voltage switching process in order to reduce a load on an internal circuit due to application of a high voltage necessary for writing.

[Explanation of symbols]

Reference Signs List 1 microcomputer 2 central processing unit 3 flash memory 4 control register for flash memory FLMCR1 rewrite control register TRMR1 reference voltage trimming register TRMR2 boost voltage trimming register Vcc external single power supply voltage Vss ground voltage Pvcc Vcc external terminal Pvss Vss external terminal VppMON VssMON monitor terminal Pfwe write protect terminal RES reset terminal 30 memory cell array 31 X decoder 31Y Y decoder 33 word driver 40 power supply circuit 41 power supply control unit 42 trimming control unit 44 voltage clamp unit 45, 46 positive boosting charge pump circuit 47 negative boosting Charge pump circuit 48 Ring oscillator 300 Main bit line 301 Sub-bit line 302 Non-volatile Memory cell 304 source line 305 word line 400 reference voltage generation circuit 401 first constant voltage circuit 402 second constant voltage circuit 403 third constant voltage circuit FBR1 feedback resistance circuit (trimming resistance circuit) FBR2, FBR3 feedback resistance circuit Vref reference Voltage Vrefa, VfixA, VfixB Clamp voltage CLK Clock signal 420, 421, 434 Clock driver 436 Trimming resistor circuit 444, 445 Delay circuit VPP6, VPP9 Positive boost voltage 460 Switching means for substrate bias voltage VPPMNS9 Negative boost voltage 461 SR flip-flop 464 Comparator NP Boosting node Q10, Q11, Q12 Negative boosting p-channel type MO
S transistor C1, C2 Negative boost capacitance element DS1 to DS4 Drive signal 470 Selector 330 Trimming information storage area in flash memory FWE protect bit SWE rewrite enable bit ESU erase setup bit PSU write setup bit E erase enable bit P write enable bit

Continued on the front page (72) Inventor Naoki Yada 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. No. 1 In the Semiconductor Division, Hitachi, Ltd.

Claims (17)

[Claims] 1. A single power supply including an electrically erasable and writable non-volatile memory and a central processing unit accessible to the non-volatile memory on a single semiconductor substrate, and supplied to an external power supply terminal A semiconductor integrated circuit using a voltage as an operation power supply, wherein the non-volatile memory clamps an output voltage to a first voltage lower than the single power supply voltage using a reference voltage having a small power supply voltage dependency. A voltage clamping unit, a boosting unit capable of boosting an output voltage of the voltage clamping unit to a positive high voltage and a negative high voltage, and erasing and writing using the positive and negative high voltages output from the boosting unit. A semiconductor integrated circuit, comprising: a plurality of nonvolatile memory cells to be performed. 2. The boosting means has a charge pump circuit that has a p-channel MOS transistor and a capacitor coupled to a boosting node that forms a negative high voltage, and that generates a negative high voltage by a charge pumping action thereof. And the MO
Switching means for switching the substrate bias voltage common to the S transistors from the output voltage of the voltage clamping means to a second voltage lower than the output voltage on the way;
2. The system according to claim 1, wherein the second voltage is a voltage having a higher level than a boosted voltage at the time of the switching.
A semiconductor integrated circuit as described in the above. 3. The switching means according to claim 2, wherein said substrate bias voltage is changed to said second voltage even if the boosted voltage fluctuates up and down after said switching.
3. The semiconductor integrated circuit according to claim 2, wherein the semiconductor integrated circuit has a hysteresis characteristic for maintaining the voltage at a predetermined voltage. 4. A negative boosting charge pump circuit for generating a negative high voltage by a charge pumping operation of a MOS transistor and a capacitor coupled to a boosting node for forming a negative high voltage, A positive boosting charge pump circuit that generates a positive high voltage by a charge pumping action of a MOS transistor and a capacitor coupled to a boosting node that forms a high voltage; 2. The semiconductor integrated circuit according to claim 1, wherein the MOS transistor and the MOS transistor included in the negative boosting charge pump circuit have different phases during an ON operation period. 5. The voltage clamp means includes: a reference voltage generation circuit having a small power supply voltage dependency; and negative feedback control of an output circuit to the first voltage using a reference voltage output from the reference voltage generation circuit as a reference voltage. A first constant voltage generating circuit, and a second constant voltage generating circuit that performs negative feedback control of the output circuit to the first voltage using a voltage output from the first constant voltage generating circuit as a reference voltage. 2. The semiconductor integrated circuit according to claim 1, wherein an output voltage of said second constant voltage generating circuit is supplied to said boosting means. 6. A third circuit for performing negative feedback control on an output circuit using a voltage output from the first constant voltage generation circuit as a reference voltage.
6. The semiconductor integrated circuit according to claim 5, further comprising a constant voltage generation circuit of claim 5, wherein an output voltage of the third constant voltage generation circuit is used as an operation power supply voltage of a reading system. 7. The voltage clamp means has a trimming circuit for finely adjusting an output voltage, a trimming control means for controlling the trimming circuit according to trimming adjustment information, and a trimming adjustment to be supplied to the trimming control means. Register means for setting information,
2. The semiconductor integrated circuit according to claim 1, wherein said register means receives the transfer of said trimming adjustment information from a specific area of said nonvolatile memory. 8. The semiconductor integrated circuit according to claim 7, wherein said register means receives the transfer of said trimming adjustment information in synchronization with a reset operation of said semiconductor integrated circuit. 9. The semiconductor integrated circuit according to claim 8, wherein said central processing unit can access said register means in a test mode. 10. The trimming control means determines a trimming position of the trimming circuit according to a value of the trimming adjustment information, wherein the trimming position and the trimming adjustment when the trimming adjustment information is a logical value “1” of all bits. There is a selection logic for selecting the trimming position when the information is all bits logical value “0” so as to be adjacent to each other. When the nonvolatile memory is set to the writing state in the wafer completed state, and when the nonvolatile memory is shipped, 10. The semiconductor integrated circuit according to claim 8, wherein a difference between output voltages of said voltage clamping means is minimized both in the erased state and in the erased state. 11. A control register for controlling the nonvolatile memory, wherein the control register includes a write setup bit for instructing the booster to start a boost operation for writing, and a write using a boost voltage. It has a write enable bit for instructing the start of operation, an erase setup bit for instructing the boosting means to start a boosting operation for erasing, and an erase enable bit for instructing start of an erasing operation using a boosted voltage. 2. The semiconductor integrated circuit according to claim 1, wherein: 12. The control register further includes a rewrite enable bit for instructing a preparation state for a boosting operation by the boosting means, and the erase setup bit and the write-in bit are provided on condition that the rewrite enable bit is a true value. The semiconductor integrated circuit according to claim 11, wherein the semiconductor integrated circuit receives an instruction by a setup bit. 13. The control register further includes a protect bit in which a value corresponding to a state of an external terminal is set, wherein the protect bit is a true value of the rewrite enable bit on condition that it is a true value. 13. The semiconductor integrated circuit according to claim 12, wherein an interlock is performed to enable setting of the semiconductor integrated circuit. 14. A single semiconductor substrate comprising: a flash memory which can be electrically erased and written; and a central processing unit which can access the flash memory, and a single power supply voltage supplied to an external power supply terminal. A microcomputer serving as an operation power supply, wherein the flash memory outputs a voltage lower in level than the single power supply voltage using a reference voltage having a small power supply voltage dependency as a reference potential; Boosting means for boosting the output voltage of the voltage generating circuit; and switching means for switching the substrate bias voltage common to the MOS transistors connected to the boosting node of the boosting means during the boosting operation. Characteristic microcomputer. 15. A single semiconductor substrate comprising: a flash memory electrically erasable and writable; and a central processing unit accessible to said flash memory, wherein a single power supply voltage supplied to an external power supply terminal is provided. A microcomputer serving as an operation power supply, wherein the flash memory comprises: a constant voltage generation circuit using a reference voltage having a small power supply voltage dependency as a reference potential; and an output voltage of the constant voltage generation circuit being boosted in absolute value. A booster circuit for generating a high voltage for writing and erasing operations; the constant voltage generating circuit having a trimming circuit for finely adjusting an output voltage; and a trimming control for controlling the trimming circuit in accordance with trimming adjustment information. Means for transferring trimming adjustment information to be supplied to the trimming control means from a specific area of the flash memory. A microcomputer further comprising a control register to be executed. 16. A single semiconductor substrate comprising: a flash memory electrically erasable and writable; and a central processing unit accessible to the flash memory, wherein a single power supply voltage supplied to an external power supply terminal is provided. A microcomputer serving as an operation power supply, wherein the flash memory has a power supply circuit for generating a high voltage for writing and erasing operations by a boosting operation, and has a control register for controlling the flash memory; The control register includes a rewrite enable bit and a protect bit, wherein the rewrite enable bit enables erasing or writing on condition that it is a predetermined value, and the protect bit has a value corresponding to a state of an external terminal. Is set, and the rewrite enable is performed on condition that it is a predetermined value. A microcomputer capable of setting a bit to a predetermined value. 17. A single semiconductor substrate comprising: a flash memory electrically erasable and writable; and a central processing unit accessible to the flash memory, wherein a single power supply voltage supplied to an external power supply terminal is provided. A microcomputer serving as an operation power supply, wherein the flash memory comprises: a memory cell array having a plurality of memory cell transistors having a control gate connected to a word line, a drain connected to a bit line, and a source connected to a source line; A booster circuit for generating a high voltage for writing and erasing operations on a cell transistor; an address decoder for forming a word line selection signal based on an address signal; And the word line selection level at the time of writing is set to the second polarity with respect to the ground potential. A word driver circuit, and forcing all word lines to ground potential at the start and end of the write operation, switching the operation power supply of the word driver to ground potential, and logically determining the polarity of the selection level of the selection signal of the address decoder. And a timing control means for switching the operation power supply of the word driver.