JP2000331489A - Semiconductor device and microcomputer - Google Patents

Semiconductor device and microcomputer

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Publication number
JP2000331489A
JP2000331489A JP13658799A JP13658799A JP2000331489A JP 2000331489 A JP2000331489 A JP 2000331489A JP 13658799 A JP13658799 A JP 13658799A JP 13658799 A JP13658799 A JP 13658799A JP 2000331489 A JP2000331489 A JP 2000331489A
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JP
Japan
Prior art keywords
circuit
charge pump
voltage
power supply
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13658799A
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Japanese (ja)
Inventor
Masamichi Fujito
Yozo Kawai
Yutaka Shinagawa
Kazufumi Suzukawa
Toshihiro Tanaka
裕 品川
洋造 河合
利広 田中
正道 藤戸
一文 鈴川
Original Assignee
Hitachi Ltd
Hitachi Ulsi Systems Co Ltd
株式会社日立製作所
株式会社日立超エル・エス・アイ・システムズ
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Priority to JP13658799A priority Critical patent/JP2000331489A/en
Publication of JP2000331489A publication Critical patent/JP2000331489A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To reduce ripple of boosting voltage without increasing a layout area of a boosting power source circuit by controlling clock supply operation based on boosting voltage of plural charge pump circuits to which clock signals of which phases are different respectively are supplied. SOLUTION: Plural charge pump circuits 2, 3, 4 inputs power source voltage Vcc synchronizing with clock signals P1, P2, P3 respectively, performs boosting operation, and outputs it to a common connection node Nout. A ring oscillator 5 supplies clock signals P1, P2, P3 having different phases respectively to the plural charge pump circuits 2, 3, 4. Also, a resistor voltage dividing circuit 7 and a comparing circuit 6 constitute a control circuit controlling operation in which clock signals P1, P2. P3 are supplied to the plural charge pump circuits 2, 3, 4 from the ring oscillator 5 based on boosting voltage formed by plural charge pump circuits 2, 3, 4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a charge pump type booster power supply circuit, and further relates to a microcomputer, for example, a flash memory having a booster power supply circuit, and a microcomputer having the flash memory together with a central processing unit. To apply to effective technology.

[0002]

2. Description of the Related Art A flash memory is a type of semiconductor memory device that is electrically erasable and writable. This flash memory has an array of electrically erasable and writable nonvolatile memory cells. For example, the nonvolatile memory cell is set to an erased state or a written state in accordance with a state where a high voltage is applied to a control gate or a source, and the threshold voltage seen from the control gate is different.

There is a semiconductor memory device having a built-in boosting power supply circuit for forming the high voltage. In the boost power supply circuit,
Charge pump circuits are widely applied. As the charge pump circuit, Dicks as illustrated in FIG.
The on type is common, and many improvements have been proposed.

[0004] For example, a circuit for reducing the rise time of a boosted voltage, which is used in a boosted power supply circuit for a rewrite voltage of a flash memory (nonvolatile semiconductor memory device), is Sy.
posium on VLSI Circuits
Digest of Technical Paper
spp 65-66 1994. Further, in order to improve the boosting efficiency of the boosting power supply circuit, the clock signal supplied to the charge pump circuit is set to four phases,
Furthermore, as a report of a charge pump circuit in which generation of a boosted voltage at the time of reading and generation of a boosted voltage at the time of writing are shared, Symposium on VLS has been reported.
I Circuits Digest of Tech
natural Papers pp63-64 1997
There is.

[0005]

In the charge pump circuit shown in FIG. 3, five diode-connected MOS transistors are connected in series, and a charge pump capacitor C0 is connected to the series connection node. At the other end of the pump capacity C0, signals Vc1 and Vc2 generated from the output clock signal P1 of the ring oscillator are provided.
Is supplied. The pulse-like waveforms of the signals Vc1 and Vc2 are complementary clock waveforms (two-phase clocks). As a result, the boosted voltage Vcpo is applied to the output terminal of the charge pump circuit.
ut is obtained. Note that a smoothing capacitor Cs is connected to the output terminal of the charge pump circuit for the purpose of suppressing ripples (undesired voltage fluctuations) of the boosted voltage Vcpout. However, if the parasitic load capacitance to which the boosted voltage is supplied is large, it may not be necessary to add a smoothing capacitance.

In order to keep the level of the output voltage of the charge pump circuit constant, the level of the voltage output from the charge pump circuit is detected, and the detected level is compared with a reference voltage Vref by a comparison circuit. The operation of the charge pump circuit is controlled based on this. That is, when the output voltage of the charge pump circuit exceeds a predetermined voltage value,
The operation of the charge pump circuit is controlled by stopping the supply of the signals Vc1 and Vc2 to the charge pump circuit.

The value of boosted output voltage Vcpout in FIG. 3 is (R1 + R2) / R2 times reference voltage Vref.

When the boosted output voltage of the charge pump circuit is used for the rewriting (erasing / writing) operation of the flash memory, the rewriting speed is, for example, several microseconds, so that the load switching speed is slow for the boosting power supply circuit. On the other hand, the oscillation cycle of the clock signal for driving the charge pump circuit is, for example, several tens of nanoseconds. Therefore, the boosted voltage of the boosted power supply circuit hardly fluctuates when the load is switched due to rewriting.

However, the load may be switched at a cycle equal to or shorter than the oscillation cycle of the clock signal of the charge pump circuit. For example,
In a flash memory, a boosted voltage is often used as a word line drive voltage in order to maximize a read signal amount from a memory cell. Such a read operation cycle is much shorter than a rewrite operation cycle. Therefore, when the boosted voltage of the read word line for the flash memory is formed by the boosted power supply circuit, if the load switching such as the switching of the drive word line frequently occurs at intervals shorter than the oscillation cycle of the clock signal P1, the word line drive is performed. A voltage fluctuation (i.e., ripple) that cannot be ignored is generated in the boosted voltage of the boosted power supply circuit that generates the voltage. In particular, the reading operation of the flash memory on-chip in the microcomputer together with the central processing unit tends to be speeded up in synchronization with the operation clock signal inside the microcomputer, and the ripple in that case is further increased.

FIG. 8 shows a relationship between a voltage of a read word line of a nonvolatile memory cell (flash memory cell) and a read operation frequency in a flash memory. It can be seen that by increasing the word line voltage, a large amount of memory cell current flows and the read operation frequency is improved. now,
When the target read operation frequency is 40 MHz (the read speed is 25 ns), a boosted output voltage of 3.6 V or more is required.

In addition, due to the limitation of the flash memory cell device, when a high voltage is applied to the word line at the time of reading, the threshold voltage of the memory cell cannot be maintained at a low value due to generation of hot electrons and changes to a high value. A disturb phenomenon occurs. If a memory cell is read in this state, an erroneous logical value is read. Therefore, the read word line voltage is in a range where this disturb phenomenon does not occur, which is 4.0 V or less in FIG.
Needs to be

In consideration of this disturb phenomenon, it is necessary that the voltage fluctuation (ripple) of the boosted voltage generated in the charge pump circuit be suppressed to a range that does not cause the disturb.

In order to suppress the ripple voltage to a certain target value, it is general to provide the smoothing capacitor at the output terminal of the boosted voltage. FIG. 7 shows the relationship between the ripple voltage value and the smoothing capacitance value. The ripple can be suppressed by increasing the value of the smoothing capacitance. However, there is a limit in increasing the smoothing capacitance in relation to the chip area of the semiconductor device.

An object of the present invention is to provide a semiconductor device having a boosted power supply circuit capable of reducing a boosted voltage ripple without increasing the layout area of the boosted power supply circuit.

Another object of the present invention is to provide a semiconductor device capable of suppressing a ripple of a boosted output even if a load of an output of a boosted power supply circuit fluctuates at a frequency close to an operation clock frequency of a charge pump circuit, and a micro device. To provide a computer.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0017]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

[1] A boosting power supply circuit provided in a semiconductor device according to the present invention includes a plurality of charge pump circuits each performing a boosting operation in synchronization with a clock signal and having an output node commonly connected, and the plurality of charge pump circuits. A clock supply circuit that supplies clock signals having different phases to the circuit; and a control circuit that controls a clock supply operation from the clock supply circuit to the charge pump circuit based on a boosted voltage generated by the charge pump circuit. Is done.

According to the above, since the plurality of charge pump circuits perform the boosting operation in synchronization with the clock signals having different phases, the plurality of charge pump circuits are respectively provided at different timings in one cycle of one clock signal. The boosting operation can be performed once each. In other words, the number of boosting operations that can be performed in one cycle of one clock signal as a whole of the boosting power supply circuit is a multiple of the number of parallel operation of the charge pump circuit, and the boosting capability that one charge pump circuit should have is one charge pump circuit. As compared with a booster power supply circuit having only one power supply circuit, the number of parallel power supplies is reduced to one-fourth. For example, when n charge pump circuits are provided, the boosting capability of one charge pump circuit may be 1 / n. Therefore, the ripple when the boosted voltage changes to the boosted side when the boosting operation is started is greatly reduced as compared with the boosted power supply circuit having only one charge pump circuit.

Further, as described above, the interval at which any one of the charge pump circuits starts the boosting operation in the entire boosting power supply circuit is shorter than when one charge pump circuit is used. Therefore, when the boosted voltage falls below the desired value, the response time at which the charge pump circuit starts the boosting operation again becomes earlier, so that the level at which the polarity of the boosted voltage changes to the opposite side is also reduced. This opposite polarity ripple can also be reduced.

Since the ripple is reduced or suppressed,
It is only necessary to adopt a small value of the smoothing capacity.

Further, as is apparent from the above description, since the outputs of a plurality of charge pump circuits are commonly connected,
The boosting capability of each charge pump circuit for obtaining a boosted voltage required as a boosted power supply circuit may be low according to the number of parallel charge pump circuits. This means that the chip occupied area by the pump capacitance and the diode MOS transistor constituting the charge pump circuit becomes substantially the same between the case where one charge pump circuit is provided and the case where a plurality of charge pump circuits are arranged in parallel. Means that. Therefore, even if a plurality of charge pump circuits are arranged in parallel, the area occupied by the chip of the boosting power supply circuit does not greatly increase.

[2] When the clock supply circuit is constituted by a ring oscillator in which a plurality of delay stages are arranged in an oscillation loop, if clock signals having different phases are output from different delay stages, such a clock can be output. Signals can be easily formed.

[3] The charge pump circuit includes a series circuit of a plurality of MOS transistors each diode-connected, and a pump capacitance element having one end coupled to a connection point of the MOS transistors. If an internal clock signal that is changed so that the ON operation periods of adjacent MOS transistors are different from each other is supplied to the other end of the element, a positive or negative boosted voltage can be easily obtained.

[4] In the above [3], a second pump capacitance element, which is different from the pump capacitance element and boosts a gate voltage of the MOS transistor, is further provided. A second internal clock signal that is different from the internal clock signal and that changes so as to make the boost operation of the adjacent second pump capacitance element different from the internal clock signal; And the second internal clock signal is a four-phase clock signal having different phases from each other,
Individual charge pump circuits can be configured. The phase pressure operation is further smoothed or stabilized as compared with the case where an internal clock signal which is a complementary clock signal is used.

[5] The control circuit includes a comparison circuit for comparing the divided voltage of the boosted voltage with a reference voltage, and uses the comparison result of the comparison circuit to transfer the clock from the clock supply circuit to the charge pump circuit. By controlling the supply and stop of the supply of the clock signal, the boosted voltage can be maintained at a predetermined level. When the supply of the clock signal is started, ripples are likely to occur. However, as described above, the configuration in which a plurality of charge pump circuits are operated with their phases shifted to alleviate or suppress the occurrence of ripples.

[6] The circuit for obtaining the divided voltage of the boosted voltage can be easily realized by using a plurality of MOS transistors as a series resistor.

[7] If the first backflow prevention means for preventing the backflow of the current from the common output node to the charge pump circuit in response to the stop of the supply of the clock signal to the charge pump circuit is employed, The voltage can be further stabilized. Further, a second backflow prevention unit for preventing a backflow of a current from the charge pump circuit to a power supply voltage in response to the stop of the supply of the clock signal to the charge pump circuit may be employed.

[8] When the semiconductor device further includes a plurality of memory cells arranged in a matrix, a plurality of word lines coupled to selection terminals of the memory cells, and a selection circuit for selecting a word line. In the case where the selection circuit uses the boosted voltage of the boosted power supply circuit as the word line selection level in the read operation, the ripple increases even if the word line selection operation cycle (memory read cycle) is shorter than the clock signal cycle of the charge pump circuit. Can be alleviated.

[0030]

[9] If the memory cell is an electrically rewritable nonvolatile memory cell, the occurrence of the ripple of the boosted voltage which is the word line selection level in the read operation is reduced or suppressed. The disturb phenomenon in which the threshold voltage of the cell changes undesirably can be reduced.

[10] If a microcomputer including a central processing unit capable of accessing the memory cell by executing an instruction to the semiconductor device is configured, the read access of the memory cell by the central processing unit is performed by the operation of the central processing unit. Even if the speed is further increased in synchronization with the clock, the ripple and the disturbance can be alleviated.

[11] In particular, the microcomputer to which the boost power supply circuit is applied connects a central processing unit for executing instructions, an electrically rewritable nonvolatile memory, and the nonvolatile memory and the central processing unit. Including bus. The nonvolatile memory includes a memory cell array in which electrically erasable / writable nonvolatile memory cells are arranged in a matrix, and a memory that performs a read operation and an electrical erase / write operation on a memory cell in response to an external instruction. A control circuit; and a boosting power supply circuit for generating a boosted voltage used for the read operation and the erase / write operation. As described above, the booster power supply circuit can reduce or suppress the occurrence of ripples by operating a plurality of charge pump circuits with shifted phases.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 schematically shows a booster power supply circuit applied to a semiconductor device according to the present invention. In FIG. 1, a boost power supply circuit 1 includes charge pump circuits 2, 3,
4, a ring oscillator 5, a comparison circuit 6, a resistive voltage dividing circuit 7, and a smoothing capacitor 8.

Each of the charge pump circuits 2, 3, and 4 performs a boosting operation by inputting a power supply voltage Vcc in synchronization with a clock signal, and an output node of the boosted voltage is commonly connected. Nout is a common connection node. The smoothing capacitor 8 is arranged between the common connection node Nout and the ground terminal Vss of the circuit. Vcpout is a boosted voltage (boosted output voltage) of the boosted power supply circuit 1. The ring oscillator 5 includes the plurality of charge pump circuits 2, 3, 4,
An example of a clock supply circuit that supplies clock signals P1, P2, and P3 having different phases from each other is realized. The resistor voltage dividing circuit 7 and the comparing circuit 6 are connected to the charge pump circuits 2 and
The clock signal P is sent from the ring oscillator 5 to the charge pump circuits 2, 3, 4 based on the boosted voltage formed by
A control circuit for controlling the operation of supplying P1, P2 and P3 is configured.

FIG. 2 shows the principle configuration of the boosting power supply circuit shown in FIG. 1 in more detail. The charge pump circuit 2 includes a series circuit in which a plurality of diode-connected MOS transistors 20 each having a gate electrode coupled to its own drain electrode are arranged in series. The MOS
One capacitance electrode of a pump capacitance element (first pump capacitance element) 21 is coupled to a connection point of the transistor 20.
The other capacitive electrode of the pump capacitive element 21 is
A clock signal changed so as to make the ON operation period of the S transistor 20 different, for example, a complementary clock signal (first clock signal)
Is supplied via the NAND gate 22 and the inverters 23, 24, 25. The other charge pump circuits 3 and 4 have the same circuit configuration. The drain electrode of the MOS transistor 20 arranged at the left end of each of the charge pump circuits 2, 3, and 4 is coupled to the power supply voltage Vcc via a p-channel MOS transistor 35. MO arranged at the right end of each charge pump circuit 2, 3, 4
The source electrode of the S transistor 20 is a p-channel type M
Commonly connected to the node Nout via the OS transistor 34.

To the NAND gates 22 of the charge pump circuits 2, 3, and 4, the boost start signal CNTN and the comparison result signal CPS are commonly input, and the separate clock signals P1, P2, and P3 are input. The charge pump circuits 2, 3, and 4 perform the boosting operation in synchronization with the rising of the clock signals P1, P2, and P3 while the comparison result signal CPS is at the high level after the boosting start signal CNTN is at the high level. I do.

The resistance voltage dividing circuit 7 has p-channel type MOS transistors 70 and 71 connected in series. The MOS transistor 70 is fixed in a diode connection mode, and the MOS transistor 71 is in a diode connection state when the activation signal CNT is at a low level (ground voltage Vss level). Both MOS transistors 7
0, 71 in the diode connection mode,
The divided voltage Vd is connected to the connection point between the OS transistors 70 and 71.
As iv, a half level of the voltage Vcpout is formed.

The comparison circuit 6 is configured by connecting p-channel type current mirror load transistors 62 and 63 to n-channel type differential input MOS transistors 60 and 61. The reference voltage Vref is supplied to the gate electrode of one differential input transistor 61, and the divided voltage Vdiv of the resistance voltage dividing circuit 7 is input to the gate electrode of the other differential input transistor 61. The comparison result signal CPS is at a high level until the divided voltage Vdiv reaches the reference voltage Vref, and is at a low level when the divided voltage Vdiv exceeds the reference voltage Vref. 67 is an n-channel type power switch transistor, and 64 is a p-channel type initialization transistor. When the boosting operation is instructed by the low level of the activation signal CNT, the power switch transistor 67 is turned on and the comparison circuit 6 is activated.
When the standby state is instructed to the boost power supply circuit by the high level of the start signal CNT, the initialization transistor 64
Is turned on, and the comparison result signal CPS is pulled up to a high level.

MO for regulating voltage Vcpout to power supply voltage Vcc in the standby state of the boosted power supply circuit
S transistors 40 to 44 are provided. 44 is p
It is a channel type pull-up MOS transistor,
The gate voltage is formed via a level conversion circuit including MOS transistors 40 to 43. In the standby state (CNT: high level) of the boost power supply circuit, the MOS
The transistor 44 is turned on.

The MOS transistors 30 to 35 constitute a backflow prevention circuit for preventing backflow of current to the charge pump circuits 2, 3, and 4. That is, the MOS transistor 30
33 to 33 constitute a level conversion circuit, in which the MOS transistor 30 is turned off and the MOS transistor 30 is turned off in response to a state in which the charge pump circuit is stopped by the low level of the comparison result signal CPS in the operable state of the boosted power supply circuit By turning on 31, MOS transistors 34 and 35 are cut off, and MOS transistor 34 prevents backflow of current from common output node Nout to charge pump circuits 2, 3 and 4.
The MOS transistor 35 prevents the current from flowing backward from the capacitance element 21 in the charge pump circuit to the power supply voltage Vcc as the voltage supply power supply.

The ring oscillator 5 has an odd number of inverters in the oscillation loop. In the example of FIG. 2, three inverters 50, 51, and 52 are representatively shown as delay stages. The three-phase clock signals P1, P2, and P3 have different phases due to different output positions from the oscillation loop.

The boost power supply circuit can be applied to, for example, an operation power supply for driving a read word line of a flash memory mounted on a microcomputer. In this case, the switching of the load of the boosting power supply circuit is determined according to the word line selection operation cycle, in other words, the memory access cycle, and is often the same as or shorter than the oscillation cycle of the ring oscillator. FIG. 4 shows an example of the operation timing of the boosting power supply circuit assuming such a case.

In FIG. 4, WL is a word line selection timing signal during a read operation in the flash memory. The word line selection operation at the time of the read operation is performed in synchronization with the cycle of the timing signal WL. Therefore, the boosted voltage Vcpout is consumed every time the word line is selected, and the level is lowered. When the level of the boosted voltage Vcpout becomes lower than twice the voltage (2 × Vref) of the reference voltage Vref, the comparison result signal CPS is set to the high level. During this time, the rising edge of the clock signals P1, P2, and P3 is synchronized. The charge pump circuits 2, 3, and 4 perform a boosting operation.
In the example of FIG. 4, the charge pump circuit 4 performs a boosting operation in synchronization with the rising of the clock signal P3. As a result, if the boosted voltage Vcpout exceeds twice the voltage (2 × Vref) of the reference voltage Vref, the comparison result signal CPS
Is negated to a low level.

As is apparent from FIG. 4, the three charge pump circuits 2, 3, and 4 are provided with clock signals P having different phases.
Since the boosting operation is performed in synchronization with 1, P2, and P3, the three charge pump circuits 2, 3, and 4 can perform the boosting operation once at different timings in one cycle of one clock signal. is there. In other words, the number of times of boosting operations that can be performed in one cycle of one clock signal in the entire boosting power supply circuit is three times that is the number of parallel operations of the charge pump circuit. Therefore, the boosting capability of one charge pump circuit is only 1/3, which is 1 / the number of parallel circuits, as compared with a booster power supply circuit having only one charge pump circuit as shown in FIG. . That is, the transistor sizes of the diode-connected MOS transistors 20 and the inverters 23, 24, and 25 constituting the individual charge pump circuits 2, 3, and 4, and the size of the pump capacitance element 21 are 1/1 of the charge pump circuit of FIG. 3 is sufficient. As a result, the ripple when the boost voltage changes to the boost side when the boost operation is started is greatly reduced as compared with FIG. 5 showing the operation waveform of the boost power supply circuit having only one charge pump circuit.

Further, as described above, the interval at which any one of the charge pump circuits 2, 3, and 4 starts the boosting operation as a whole of the boosting power supply circuit is shorter than the case where one charge pump circuit as shown in FIG. 3 is used. Is reduced to 1/3. For example, in the case of the boosting power supply circuit of FIG. 3 having only one charge pump circuit, as illustrated in FIG.
The boosting operation can be performed only once in one cycle.
In the case of FIG. 4, the boost power supply circuit outputs 1 of the clock signal P1.
There is an opportunity to be able to perform the boost operation up to three times in a cycle. Therefore, in FIG. 4, when the boosted voltage Vcpout falls below the desired value (2 × Vref) at time t0, the response time at which the charge pump circuit starts the boosting operation again becomes earlier, so that the opposite side to the boosted voltage is used. The level at which the polarity is to be changed is also reduced. This opposite polarity ripple can also be reduced.

Since the ripple is reduced or suppressed,
The capacitance value of the smoothing capacitance 8 can be reduced.

As is apparent from the above description, since the outputs of the plurality of charge pump circuits 2, 3 and 4 are commonly connected, each of the charge pump circuits is required to obtain a boosted voltage required as a boosted power supply circuit. The boosting capacity to be provided by 2, 3, and 4 may be low according to the number of parallel charge pump circuits. This means that all charge pump circuits 2,
3 and 4, the pump capacity 21 and the diode MO
This means that the area occupied by the chip by the S transistor 20 and the like is almost the same as the case where one charge pump circuit is provided. Therefore, even if a plurality of charge pump circuits 2, 3, and 4 are arranged in parallel, the chip occupation area of the boosting power supply circuit does not increase significantly.

FIG. 6 illustrates the relationship between the ripple voltage value and the smoothing capacitance value in the boost power supply circuit 1 of the present invention. FIG. 7 illustrates the relationship between the ripple voltage value and the smoothing capacitance value in the boosting power supply circuit of FIG. 7 and FIG. 6,
It is clear that the use of the boost power supply circuit 1 of the present invention can reduce the value of the smoothing capacitance that affects the layout area. When the allowable value of the ripple voltage value is 0.2 V, the value of the smoothing capacitance can be reduced by half.

FIG. 9 shows an electrically rewritable flash memory 90 as a semiconductor memory device as an example of the semiconductor device according to the present invention.

The memory array 100 includes electrically rewritable (erasable / writable) nonvolatile memory cells (flash memory cells) arranged in a matrix. Although not specifically shown, the flash memory cell has a control gate, a floating gate, a source, and a drain, and holds data corresponding to, for example, a state of a threshold voltage viewed from the control gate. The control gate of the flash memory cell is connected to a word line, the drain is connected to a bit line, and the source is connected to a source line. There are various known forms of applying the erase / write voltage to the flash memory cell. In short, the threshold voltage of the flash memory cell is controlled by injecting / emitting electrons into / from the floating gate. One flash memory cell is 2
It can hold multi-value data such as values or four values.

An externally supplied row address signal (X
Address signal) AX is a row address buffer (XADB)
At 102B, the signal is converted into an internal complementary address signal, which is decoded by a row address decoder (XDCR) 102D to generate a word line selection signal and the like. WL (i) is a word line representatively shown. On the bit line side of the memory array 100, a data latch circuit (DL) 103, a sense amplifier circuit (SA) 104, a first column gate array circuit (YG-Gate) 105, and a second column gate array circuit (YW- Gate) 106, a third column gate array circuit (YT-Gate) 107, a column address buffer (YA)
D) 109B and column address decoder (YDCR) 10
9D is provided. Column address buffer (YAD)
109B converts the column address signal (AY) into an internal complementary address signal. The internal complementary address signal is decoded by a column address decoder (YDCR) 109, and the first column gate array circuit (YG-Ga
te) 105 is made to select a bit line connected to the sense amplifier 104 or the data input buffer 111. Although not particularly limited, the data latch circuit 103 holds write data when performing writing in word line units.
Second column gate array circuit (YW-Gate) 106
Turns on the gate only during a write operation, and supplies write data (voltage) to the memory cell. At the time of reading, it is turned off. Third column gate array circuit (YT-G
a) 107 is in an on state (a high voltage may be applied) during a data latch input operation and a read operation other than the write operation, and is in an off state during the write operation. Column gate array circuit (Y
(T-Gate) 107 and thereafter are cut off. By separating, the first column gate array circuit (YG-Gate) 1
Since 2005, a high-speed low-withstand-voltage device can be used.

Source / channel potential switching circuit (SV
C) 110 switches the source line potential or the like of the flash memory cell to an erasable potential via the source line during the erasing operation. Although not particularly limited, a high voltage is applied to a word line, and erasing is performed in combination with a source line potential. Input buffer circuit (DIB) 111 and output buffer circuit (DOB) 112 for inputting / outputting data to / from the outside
And a multiplexer circuit (MP) 113. I /
O is a data input / output terminal. The operation mode of the flash memory depends on the control signal buffer circuit (CSB) 1
15 and is controlled by an output of a mode control circuit (MC) 114. The built-in power supply circuit (VS) 116 generates an internal operation power supply such as a high voltage for an erase / write operation or a boosted voltage for selecting a word line at the time of reading based on an external power supply voltage Vcc. Vss is the ground voltage of the circuit.

The control signal buffer circuit 115
Although not particularly limited, a chip enable signal CEb, an output enable signal OEb, a write enable signal WEb, a serial clock signal SC, and the like are input as memory control signals, and internal control is performed according to these signals. A signal timing signal is generated, and the mode control circuit 114 supplies an external terminal R / Bb.
Ready / busy signal is output.

In the built-in power supply circuit 116, although not particularly limited, for example, a power supply voltage Vcc is input from the outside, and a read word line voltage Vrw, a write word line voltage Vww, a write drain terminal voltage Vwd, Transfer voltage Vwt of write drain voltage, write verify word line voltage Vwv corresponding to low threshold voltage (VthL) of memory cell, erase word line voltage Vew, erase verify corresponding to high threshold voltage (VthH) of memory cell A word line voltage Vev, an erase channel / source voltage Vec, a sense amplifier circuit voltage VSA, and the like are generated.

The voltages generated here are Vrw, Vw
w, Vwv, Vew, Vev, and Vvt are applied to a row address decoder (XDCR) 102D, Vec is applied to a source / channel potential switching circuit (SVC) 110, Vwd is applied to a data latch circuit (DL) 103, and VSA is applied to a sense amplifier circuit ( SA) 104, Vwt is applied to the gate array circuit (Y
(W-Gate, YT-Gate) 106 and 107, respectively.

In this semiconductor memory device, a row / column address buffer (XADB / YADB) 102 receiving a row / column address signal AX / AY supplied from an external terminal.
B, 109B is applied to a row / column address decoder (XDCR / YDCR) 102D, 1
09D. Row address decoder (XDCR)
102D forms a word line selection signal of a memory cell group according to an address signal. Column address decoder (YD
CR) 109D forms a selection signal of a bit line of a memory cell group according to an address signal. As a result, in the memory array 100, an arbitrary word line and bit line are designated, and a desired memory cell is selected.

The boost power supply circuit 1 has a built-in power supply circuit (V
S) 116 and used for generating a high voltage such as the read word line voltage Vrw. Read word line voltage Vr
w is given to the word line selected by the row address decoder 102D.

FIG. 10 shows a single-chip microcomputer as an example of the semiconductor device according to the present invention. The single-chip microcomputer 200 shown in the figure is formed on one semiconductor substrate (semiconductor chip) such as single crystal silicon. The single-chip microcomputer 200 includes the flash memory 90 on a chip.

In FIG. 10, reference numeral 201 denotes a central processing unit (C
PU), 90 is the flash memory described in FIG.
2 is a read-only memory (ROM) for storing programs to be executed by the CPU 201 and fixed data;
Stores the calculation result of the CPU 201,
A random access memory (RAM) 204 for providing a work area for the U 201 is a direct access memory (RAM) for controlling the transfer of data between the memories 202 and 203 and an external main memory (not shown) in a predetermined block unit. It is a memory access controller (DMAC).

The microcomputer 200 has a serial communication interface circuit (SCI) 2 for performing serial communication with an external device as a peripheral circuit.
06, a timer 207, an oscillation circuit, and a clock pulse generation circuit (CPG) 208 for generating a system clock on the clock line CK.

The outside of the chip means an input / output port (IOP1
IIOP9) 211 to 219.

The microcomputer 200 includes a CPU 201, a flash memory 90, a ROM 202,
The RAM 203, the DMAC 204, and some of the input / output ports (IOP1 to IOP5) 211 to 215 are connected by a main address bus IAB and a main data bus IDB. Peripheral circuits such as the SCI 206 and the timer 207 and input / output ports (IOP1 to IOP9) 211 to 2
A peripheral address bus PAB and a peripheral data bus PDB are provided for connection with the N.19. Further, the above IAB
And a bus sequence controller (BSC) 220 for controlling the transfer of signals between the IDB, the PAB and the PDB, and controlling the state of each bus.

Next, for example, the read word line voltage Vr in the built-in power supply circuit 116 in the flash memory 90 built in the single-chip microcomputer 200
The operation of the boost power supply circuit 1 for boosting v will be described.

In FIG. 5 schematically showing signal waveforms in the configuration of FIG. 3 having one charge pump circuit, when the boosted output voltage Vcpout falls below 2 × Vref, the comparison circuit output CPS rises, but the output P1 of the ring oscillator Since the boosting is performed after the rise, the boosted output voltage Vcpout further decreases by switching the load. In FIG. 5, when the output CPS of the comparison circuit rises and the output P1 of the ring oscillator rises, the boosted output voltage Vcpou is boosted again. When the boosted output voltage Vcpou exceeds 2 × Vref, the output P1 of the ring oscillator falls, but the boosted output voltage Vcpou is reduced by 2 ×
The voltage is raised to a voltage value higher than Vref. Therefore, as illustrated in FIG. 5, a large fluctuation ripple occurs in the boosted output voltage.

Referring to FIG. 4, which schematically shows the signal waveform and the boosted output voltage waveform in the circuit of FIG. 2, the charge pump circuits 2, 3, and 4 are different from the signal waveform of FIG. The boosting operation is enabled in synchronization with the rising edges of the output clock signals P1, P2, and P3 of the oscillator 5. When the boosted output voltage Vcpout falls below 2 × Vref, the output signal CPS of the comparison circuit 6 rises. In the case of FIG. 4, the rising timing of the output of the ring oscillator 5 (P3 in FIG. 4) comes immediately, so that the boosting operation is started earlier.

Since the value of the charge pump capacitance 21 is one third of the capacitance C0 in FIG. 3, the boosted output voltage Vcpo
The lifting voltage (ripple voltage) value of u decreases.
Therefore, even if a ripple occurs in the boosted output voltage, the value becomes a suppressed value. Even if the read word line of the flash memory 90 is driven by the boosted voltage, the ripple voltage range falls within the range of the boosted lower limit voltage and the boosted upper limit voltage in FIG.

As a general method, the ripple can be suppressed by increasing the value of the smoothing capacitance. Referring to FIGS. 7 and 6 showing the relationship between the smoothing capacitance value and the ripple voltage value, the value of the smoothing capacitance 8 which affects the layout area by using the boost power supply circuit 1 of FIG. 2 according to the present invention. Can be reduced. When the ripple voltage value is 0.2 V, the value of the smoothing capacitance can be reduced to half.

FIG. 11 shows an example of a charge pump circuit in a boosted power supply circuit that uses a boosted voltage as a negative voltage. There is no particular limitation on the number of charge pump circuits connected in parallel.
FIG. 11 shows an example in which three charge pump circuits are connected in parallel. The three charge pump circuits 2a, 3a, 4a receive the outputs P1, P2, P3 of the ring oscillator 5. Each of the charge pump circuits 2a, 3a, and 4a includes nine P-channel type diode-connected MOS transistors 20a connected in series, and the output nodes of the charge pump circuits are commonly connected. MOS transistor 2
The gate width of 0a, the size of the charge pump capacitance 21a and the size of the driver for driving the charge pump capacitance 21a are 1 / of those of the boost power supply circuit having one charge pump circuit.

In the same figure, as the backflow prevention circuit, N
A channel type MOS transistor 35a is employed. The boost start voltage is the ground voltage Vss, and a negative voltage is boosted as the boost output voltage Vcpout.

The operation clock signal of the charge pump circuit described with reference to FIGS. 2 and 11 is a two-phase complementary clock signal. The clock system for driving the charge pump circuit is not limited to the complementary clock system, and a four-phase clock system for boosting the gate voltage of the MOS transistor forming the charge pump circuit may be employed.

FIG. 12 shows a circuit in which the present invention is applied to a positive voltage boosting power supply circuit using a four-phase clock system. Although the number of parallel connection of the charge pump circuits is not particularly limited, it is set to three, and three charge pump circuits 2b,
This is an example in which 3b and 4b are connected in parallel. The waveforms of the outputs P1, P2, and P3 of the ring oscillator 5 are processed and controlled, and the waveforms CPiP1, CPiP2, CPiP3, and CPiP4 (i
= 1, 2, 3) and supplied to the charge pump capacitance elements 21b, 21c of the three charge pump circuits 2b, 3b, 4b arranged in parallel. The charge pump capacitance element 21b corresponds to the charge pump capacitance element 21, and another charge pump capacitance element (second charge pump capacitance element) 21c includes a charge pump circuit 2b,
Capacitors for boosting the gate voltage of the N-channel diode-connected MOS transistors 20b constituting the transistors 3b and 4b. These capacitor elements are arranged so that the boost operation by the adjacent second charge pump capacitor 21c is different. Internal capacitor signals (second internal clock signal) CPiP3, CPiP4
Is supplied. The clock signals CPiP1 and CPiP2 are supplied to the capacitance electrode of the capacitance element 21b. Signal CP1P
The phases of j, CP2Pj, and CP3Pj are shifted by 120 degrees (j = 1, 2, 3, 4).

The circuit configuration and the clock waveform in the four-phase clock system are not particularly limited, and are characterized in that the charge pump circuits 2b, 3b, and 4b supply waveforms having different clock phases. The waveform is exemplified in FIG. The four-phase clock method is naturally applicable to the case of negative voltage boosting.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

For example, the number of parallelly connected charge pump circuits is not limited to three, but may be four or more. As the number of parallel circuits increases, the boosted voltage further stabilizes, but the chip occupied area tends to gradually increase because the isolation region of each circuit element increases.

The voltage value of the boosted output voltage Vcpout is not limited to a value obtained by doubling the reference voltage Vref, but can be changed as appropriate.

Although the power supply voltage Vcc in FIG. 2 is used as the ring oscillator and charge pump circuit start voltage, for example, a voltage obtained by stepping down and stabilizing the power supply voltage Vcc may be adopted in consideration of fluctuations in the power supply voltage. .

In the above description, the case where the invention made by the present inventor is mainly applied to a flash memory, which is the field of application as the background, has been described. However, the present invention is not limited to this, and the boosted voltage ( The present invention can be widely applied to a semiconductor device requiring a positive high voltage and a negative high voltage) and a microcomputer mounted with the semiconductor device.

[0078]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, since the plurality of charge pump circuits perform the boosting operation in synchronization with the clock signals having different phases, when the boosting operation is started, the ripple when the boosted voltage changes to the boosting side is reduced. 1 charge pump circuit
This can be greatly eased as compared with a single boosting power supply circuit. Further, the ripple of the opposite polarity can be reduced.

Since the ripple can be reduced, it is possible to contribute to the reduction of the smoothing capacitance. Since the outputs of the plurality of charge pump circuits are commonly connected, the boosting capacity required for each charge pump circuit to obtain the boosted voltage required as the boosting power supply circuit may be low according to the number of parallel charge pump circuits. . Therefore, even if a plurality of charge pump circuits are arranged in parallel, the area occupied by the chip of the boosting power supply circuit does not greatly increase.

Further, a booster voltage is further stabilized by adopting a backflow prevention circuit for preventing a backflow of current from the common output node to the charge pump circuit in response to the stop of the supply of the clock signal to the charge pump circuit. Can be done. Further, power consumption of the semiconductor device can be reduced.

When the boosted voltage of the boosted power supply circuit is used as the word line selection level in the memory read operation, even if the word line selection operation cycle (memory read cycle) is shorter than the clock signal cycle of the charge pump circuit, an increase in ripple is prevented. Can be eased.

If the memory cell is an electrically rewritable nonvolatile memory cell, the occurrence of the ripple of the boosted voltage which is the word line selection level in the read operation is reduced or suppressed. It is also possible to alleviate the disturb phenomenon in which the threshold voltage of the cell changes undesirably.

If the boosting power supply circuit is applied to the microcomputer built-in memory, the above ripples and disturbances can be similarly reduced even if the read access of the memory cell by the central processing unit is further speeded up in synchronization with the operation clock of the central processing unit. You can do it.

[Brief description of the drawings]

FIG. 1 is a circuit diagram schematically showing a boost power supply circuit applied to a semiconductor device according to the present invention.

FIG. 2 is a circuit diagram showing a detailed example of a boost power supply circuit.

FIG. 3 is a circuit diagram illustrating an example of a boost power supply circuit including one charge pump circuit.

FIG. 4 is a waveform chart showing an example of a boost operation in the boost power supply circuit of FIG. 2;

FIG. 5 is a waveform diagram illustrating an operation of a booster power supply circuit as a comparative example including one charge pump circuit.

FIG. 6 is a characteristic diagram illustrating a relationship between a ripple voltage value and a smoothing capacitance value in the boost power supply circuit of FIG. 2;

FIG. 7 is a characteristic diagram illustrating a relationship between a ripple voltage value and a smoothing capacitance value in the boost power supply circuit of FIG. 3;

FIG. 8 is an explanatory diagram illustrating a relationship between a boosted voltage of a read word line and a read operation frequency in a flash memory.

FIG. 9 is a block diagram showing an electrically rewritable flash memory as a semiconductor memory device which is an example of a semiconductor device according to the present invention.

FIG. 10 is a block diagram showing a single-chip microcomputer as an example of a semiconductor device according to the present invention.

FIG. 11 is a circuit diagram illustrating an example of a charge pump circuit in a boosted power supply circuit that uses a boosted voltage as a negative voltage.

FIG. 12 is a circuit diagram showing an example of a charge pump circuit in a positive voltage boosting power supply circuit using a four-phase clock method.

FIG. 13 is a waveform diagram showing an example of the four-phase clock waveform of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Boost power supply circuit 2, 3, 4 Charge pump circuit 2a, 3a, 4a Charge pump circuit 2b, 3b, 4b Charge pump circuit 5 Ring oscillator P1, P2, P3 Clock signal 6 Comparison circuit 7 Divider circuit 8 Smoothing capacitor 20 Diode Connection MOS transistor 20a Diode connection MOS transistor 20b Diode connection MOS transistor 21 Pump capacitance 21a Pump capacitance 21b Pump capacitance 34, 35 Backflow prevention MOS transistors 50, 51, 52 Inverter 70, 71 Voltage dividing circuit configuration MOS transistor 90 Flash memory 116 Built-in power supply circuit 200 Single chip microcomputer 201 Central processing unit IAB Main address bus IDB Main data bus

Continuing on the front page (72) Inventor Hiroshi Shinagawa 5-2-2-1, Kamimizu Honcho, Kodaira-shi, Tokyo Inside Hitachi Super LSI Systems Co., Ltd. (72) Inventor Kazufumi Suzukawa On Kodaira-shi, Tokyo 5-22-1, Mizumotocho Within Hitachi Ultra-LII Systems Co., Ltd. (72) Inventor Masamichi Fujito 5-2-2-1, Kamimizu-Honcho, Kodaira-shi, Tokyo Hitachi, Ltd.・ Inside I-Systems (72) Inventor Hirozo Kawai 5-22-1, Kamizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Super LSI Systems Co., Ltd. 5B025 AA00 AB00 AC00 AD02 AD03 AD10 AD15 AE08 5H430 BB01 BB05 BB09 BB11 BB20 EE06 EE09 EE12 EE17 EE18 EE19 FF03 FF13 GG08 HH03 JJ07

Claims (12)

[Claims]
1. A booster power supply circuit for boosting an input power supply voltage is included in a semiconductor chip. The booster power supply circuit performs a boosting operation in synchronization with a clock signal, and has a plurality of charge nodes to which output nodes are commonly connected. A pump circuit, a clock supply circuit that supplies clock signals having different phases to the plurality of charge pump circuits, and a clock supply operation from the clock supply circuit to the charge pump circuit based on a boosted voltage generated by the charge pump circuit. And a control circuit for controlling the operation of the semiconductor device.
2. The clock supply circuit includes a ring oscillator having a plurality of delay stages disposed in an oscillation loop.
2. The semiconductor device according to claim 1, wherein clock signals having different phases can be output from different delay stages.
3. The charge pump circuit includes a series circuit of a plurality of MOS transistors each diode-connected, and a pump capacitance element having one end coupled to a connection point of the MOS transistors. 3. The semiconductor device according to claim 1, wherein an internal clock signal which is changed so as to make ON operation periods of adjacent MOS transistors different is supplied to the other end of the semiconductor device.
4. The semiconductor device according to claim 1, further comprising a second pump capacitance element that is different from the pump capacitance element and boosts a gate voltage of the MOS transistor, wherein the second pump capacitance element includes the internal clock. A second internal clock signal that is different from the signal and that changes so that the boost operation of the adjacent second pump capacitance element is different, and the internal clock signal and the second internal clock signal are supplied. 4. The semiconductor device according to claim 3, wherein the clock signals are four-phase clock signals having different phases.
5. The control circuit includes a comparison circuit that compares a divided voltage of the boosted voltage with a reference voltage, and uses a comparison result of the comparison circuit to send a signal from the clock supply circuit to the charge pump circuit. 3. The semiconductor device according to claim 1, wherein the boosted voltage is maintained at a predetermined level by controlling the supply and stop of the supply of the clock signal.
6. The semiconductor device according to claim 5, wherein the circuit for obtaining the divided voltage of the boosted voltage uses a plurality of MOS transistors as a series resistor.
7. A circuit according to claim 1, further comprising first backflow prevention means for preventing a backflow of current from said common output node to said charge pump circuit in response to stopping supply of a clock signal to said charge pump circuit. The semiconductor device according to claim 5.
8. A circuit according to claim 1, further comprising second backflow prevention means for preventing a backflow of a current from said charge pump circuit to a power supply voltage in response to a stop of a supply of a clock signal to said charge pump circuit. Item 8. The semiconductor device according to item 7.
9. A semiconductor device further comprising: a plurality of memory cells arranged in a matrix; a plurality of word lines coupled to a selection terminal of the memory cells; and a selection circuit for selecting a word line. 3. The semiconductor device according to claim 1, wherein the boosted voltage of the boosted power supply circuit is used for a word line selection level.
10. The semiconductor device according to claim 9, wherein said memory cell is an electrically rewritable nonvolatile memory cell.
11. The semiconductor device according to claim 9, further comprising a central processing unit capable of executing an instruction to access said memory cell.
12. A central processing unit for executing an instruction, an electrically rewritable nonvolatile memory, and a bus connecting the nonvolatile memory and the central processing unit. A memory cell array in which nonvolatile memory cells that can be erased and written are arranged in a matrix, a memory control circuit that performs a read operation and an electrical erase / write operation on the memory cells in response to an instruction from the outside, A boost power supply circuit for generating a boosted voltage used for the erase / write operation, wherein the boosted power supply circuit performs a boost operation of the power supply voltage in synchronization with a clock signal, and a plurality of charges to which output nodes are commonly connected. A pump circuit and a clock supply circuit for supplying clock signals having different phases to the plurality of charge pump circuits, respectively. A microcomputer, characterized in that and a control circuit for controlling the clock supply operation to the charge pump circuit from the clock supply circuit on the basis of a boost voltage, wherein the charge pump circuit is formed, those made.
JP13658799A 1999-05-18 1999-05-18 Semiconductor device and microcomputer Pending JP2000331489A (en)

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831500B2 (en) 2002-10-25 2004-12-14 Elpida Memory, Inc. Noise-reduced voltage boosting circuit
JP2006107575A (en) * 2004-10-01 2006-04-20 Sanyo Electric Co Ltd Power source circuit and semiconductor memory apparatus using the same
US7075357B2 (en) 2004-02-19 2006-07-11 Elpida Memory, Inc. Boosting circuit and semiconductor device using the same
US7554386B2 (en) 2007-02-12 2009-06-30 Samsung Electronics Co., Ltd. High voltage generation circuit and method for reducing peak current and power noise for a semiconductor memory device
US7564717B2 (en) 2006-10-30 2009-07-21 Kabushiki Kaisha Toshiba Semiconductor memory device
US7567118B2 (en) 2004-03-31 2009-07-28 Panasonic Corporation Booster circuit
US7697342B2 (en) 2006-05-16 2010-04-13 Samsung Electronics Co., Ltd. Flash memory device and related high voltage generating circuit
US7750613B2 (en) 2006-09-29 2010-07-06 Samsung Electronics Co., Ltd. Regulator and method for regulating
CN106059288A (en) * 2015-04-01 2016-10-26 力旺电子股份有限公司 Charge pump regulator and control method thereof

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6831500B2 (en) 2002-10-25 2004-12-14 Elpida Memory, Inc. Noise-reduced voltage boosting circuit
US7075357B2 (en) 2004-02-19 2006-07-11 Elpida Memory, Inc. Boosting circuit and semiconductor device using the same
US7567118B2 (en) 2004-03-31 2009-07-28 Panasonic Corporation Booster circuit
JP2006107575A (en) * 2004-10-01 2006-04-20 Sanyo Electric Co Ltd Power source circuit and semiconductor memory apparatus using the same
JP4669688B2 (en) * 2004-10-01 2011-04-13 三洋電機株式会社 Power supply circuit and semiconductor memory device using the same
US7697342B2 (en) 2006-05-16 2010-04-13 Samsung Electronics Co., Ltd. Flash memory device and related high voltage generating circuit
US7750613B2 (en) 2006-09-29 2010-07-06 Samsung Electronics Co., Ltd. Regulator and method for regulating
US7564717B2 (en) 2006-10-30 2009-07-21 Kabushiki Kaisha Toshiba Semiconductor memory device
US7554386B2 (en) 2007-02-12 2009-06-30 Samsung Electronics Co., Ltd. High voltage generation circuit and method for reducing peak current and power noise for a semiconductor memory device
CN106059288A (en) * 2015-04-01 2016-10-26 力旺电子股份有限公司 Charge pump regulator and control method thereof
JP2016195527A (en) * 2015-04-01 2016-11-17 イーメモリー テクノロジー インコーポレイテッド Charge pump regulator and method of controlling the same

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