JPS63239692A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To shorten a time required for a reliability test relating to rapid rewriting or data holding characteristics at the time of system operation by controlling the supplying time of a rewriting voltage in response to control data set in a timer control means. CONSTITUTION:The titled device is provided with the timer control means TMCONT for programmably controlling the supplying time of rewriting voltages Vwr, Ver outputted from a rewrite control means WEC for supplying a voltage required for data rewriting to an electrically rewritable semiconductor non- volatile memory element based on control data stored in a prescribed semiconductor non-volatile memory element or control data supplied from the external through an exclusive pad not bonded by a wire. Since the supplying time of the rewriting voltages Vwr, Ver is controlled in response to the control data set in the timer control means TMCONT, the time of a reliability test relating to the rapid rewriting or data holding characteristics at the time of system operation can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically rewritable semiconductor non-volatile memory device, such as an EEPROM (electronically rewritable memory device).
It relates to technology that is effective when applied to (erasable and programmable read-only memory).

[Prior art]

+?The memory cell is composed of an electrically rewritable semiconductor non-volatile memory element such as MNOS (Metal Nitride Oxide Semiconductor). :EI
'In ROM, the memory cell is
As described in Microcomputer Handbook J P266 published by Ohmsha on May 25th, *When writing, if a high positive voltage is applied to the gate and the substrate side is grounded, electrons will flow through the gate due to the tunnel effect. It is injected into the trap portion of the insulating film, and its threshold voltage becomes a relatively large positive value.On the other hand, during erasing, a positive voltage is applied to the substrate and a ground potential is supplied to the gate. On the contrary, holes are injected into the trap part to reduce the threshold voltage to a small value.When reading data from a memory cell programmed in this way, it is coupled to the data line connected in series to the MNOS. Turn on the selected MO8FET, and turn on the MNOS
A ground potential is supplied to the gate m-pole of. Then, drain current does not flow to memory cells that are programmed for writing, and drain current flows to memory cells that are programmed for erasure, and depending on the presence or absence of the drain current, the memory cell is programmed. The condition is determined.

By the way, as mentioned above, when changing the program state of a memory cell composed of MNOS, the supply time or period of the write or erase voltage supplied to the memory cell depends on the retention characteristics of the programmed data of the EEPROM. It must be determined so that it can be maintained in a functionally desirable state. Therefore, in conventional EEPROMs, the voltage supply time for writing and erasing is set to a fixed time by an internal timer circuit, due to the relationship between the maximum number of times a memory cell can be rewritten and the maximum retention period of programmed data. It was designed to be controlled. Normally, the rewrite time is controlled to a certain level that can guarantee data retention time of 10 years.

[Problem that the invention seeks to solve]

However, depending on the system configuration to which EEPROM is applied, the maximum data retention time may not be so necessary, and under such circumstances, it is essentially possible to shorten the rewriting time of memory cells. However, the conventional EEPROM, which internally controls the voltage supply time for writing and erasing to a constant value, cannot satisfy the demand for high-speed data rewriting. Furthermore, in data retention characteristic tests and the like, since the rewrite time of conventional EEPROMs is controlled to be constant, it is not possible to perform accelerated tests by controlling the rewrite time.

There was a problem that screening took a long time and test efficiency was low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can programmably control data rewrite time for an electrically rewritable semiconductor nonvolatile memory element.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, the supply time of the rewriting voltage to be output from the rewriting control means that supplies the voltage necessary for rewriting data to the electrically rewritable semiconductor nonvolatile storage element is determined by the time period for which the rewriting voltage is stored in the predetermined semiconductor nonvolatile storage element. A timer control means is provided for programmable control based on control data and control data supplied from the outside via a dedicated pad that is not wire-bonded.

[For production]

According to the above means, the supply time of the rewriting voltage is controlled in response to the control data set in the timer control means, thereby enabling high-speed rewriting during system operation and reliability tests regarding data retention characteristics, etc. This achieves time savings.

〔Example〕

FIG. 1 is a block diagram showing the main parts of an EEPROM that is an embodiment of the present invention. EEPR shown in the figure
Although not particularly limited, the OM is formed on one semiconductor substrate by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the functional blocks other than the EEPROM rewriting circuit WRC are representatively shown as one functional block M, and although the details are not particularly shown, the functional block M is an electrical A memory cell array in which memory cells including rewritable semiconductor non-volatile memory elements are arranged in a matrix, a selection circuit for selecting a predetermined memory cell from the memory cell array, and data externally transmitted from the selected memory cell. It includes a data readout circuit for reading data, a timing generator for receiving external control signals and forming internal timing signals, and the like.

First, the structure of the Moricell included in the functional block M will be explained based on FIG. 3.

The memory cell MC includes, but is not particularly limited to, an N-channel type selection MO8FET QI, an electrically rewritably programmed N-channel type MNoS transistor Q2 . And MO8FE”TQ for N-channel type separation
3 are sequentially connected in series, and the selected MO8FE
The drain itt pole of TQI is coupled to the representatively shown data line DAL, and is also connected to one isolation MO8FETQ3.
The source electrode of is coupled to the circuit ground terminal. The gate electrode of the selected MO3FET QI is coupled to the representatively shown word line WOL, and the gate electrode of the MNOS transistor Q2 is coupled to the representatively shown write line W.
RL, and the gate electrode of the isolation MO5FET Q3 is coupled to the representatively shown control mcOL. still.

In reality, a plurality of the data lines are provided in the column direction, memory cells in the same column in the memory cell array are commonly connected to the data line in the column, and the word line, write line, and control line are connected in the row direction. A plurality of lines are provided in the memory cell array, and memory cells in the same row in the memory cell array are commonly connected to each line in the row.

Selection of a memory cell when programming (rewriting data) or reading data from a memory cell is performed based on an address signal supplied from the outside to the selection circuit included in the functional block M. The program operation for the memory cell that has been
This is an operation for selectively programming the NOS transistor Q2 into two states: a write state of logic "1" and an erase state of logic "0". During the program operation, the selection MO5FETQI is turned on, and the isolation MO8FETQ3 is turned off. Basically, during writing, a high positive voltage (write voltage) is applied to the gate electrode of one selected MNOS transistor Q2, and its threshold voltage is programmed to a relatively large positive value. On the other hand, during the erase operation, a low voltage (erase voltage) is applied to the gate electrode of the selected MNOS transistor Q2, and its threshold voltage is programmed to a small value. In addition, when reading data from a memory cell programmed in this way, the selection MO8FETQ1 of the selected memory cell and the isolation MO8FE
Both transistors TQ3 are turned on, and although not particularly limited, the ground potential is supplied to the gate electrode of the selected MNOS transistor Q2. In this case, no drain current flows to memory cells that are programmed for writing, and drain current flows to memory cells that are programmed for erasure, and the presence or absence of this drain current is detected by a sense amplifier (not shown). By doing so,
Data is read according to the program state of the selected memory cell.

Note that even during EEPROM standby, the gate electrode of the MNOS transistor Q2 is set to the ground level from the viewpoint of data destruction;
In order to make it possible to selectively supply a ground potential to the gate electrode of the circuit, each write line WRL is connected to the ground terminal of the circuit via an N-channel MO8FETQ4 as shown in FIG. If a P-channel MO8FET is used instead of MO8FETQ4, the write line wRL cannot be forced to the ground level due to the substrate effect simply by supplying the ground potential to its gate electrode, and the negative voltage generation circuit through the P-channel type MO3
By applying a negative voltage to the gate electrode of the FET, the MNO
Data destruction and retention failure in the S transistor Q2 must be prevented. When configured with an N-channel MO8FETQ4 as in this embodiment, if a relatively higher power supply voltage is supplied to the gate electrode of the MO3FETQ4, a ground potential can be supplied to the gate electrode of the MNOS transistor Q2. Therefore, a negative voltage generating circuit is not required, and thereby power consumption during standby can be reduced.

As shown in FIG. 1, the rewriting circuit WRC has the following features:
It has a voltage forming circuit V PG that boosts the power supply voltage to form a predetermined write high voltage VPP. This voltage forming circuit vPG boosts the power supply voltage to a certain level using a built-in Zener diode or the like to form a high voltage Vpp for writing, but the voltage forming circuit VPG of this embodiment is not wire-bonded. By receiving a voltage at a desired level from an external terminal vPP dedicated to testing, which is not available, the level of the high voltage VPP for writing can be arbitrarily controlled. Therefore, in the test mode or the like, by supplying a desired voltage to the external terminal vPP and controlling the write voltage, it is possible to arbitrarily control the write depth to the memory cell.

As a result, the write voltage, which is one parameter of the data retention characteristic, can be set arbitrarily, and the reliability of the data retention characteristic test can be improved.

In FIG. 1, WEC is a rewrite control circuit that controls supply of a write voltage Vwr or erase voltage Ver necessary for rewriting data to a predetermined memory cell. The rewriting control circuit WEC includes, but is not particularly limited to, a high voltage for writing VPP formed by the voltage forming circuit VPG, an external control signal and a signal WE, an output enable signal OE, and a function block M that responds to write data. The six rewrite control circuits WEC to which the write/erase instruction signal W/E detected by the timer circuit TM and the rewrite voltage supply timing signal (determining the rewrite time) φWe supplied from the timer circuit TM are not particularly limited; The chip enable signal GE is set to low level, which is the chip selection level, and the output enable signal O
E is set to high level, which is the data input instruction level,
Furthermore, when the write enable signal WE is set as a clock of a predetermined period, a rewrite operation is instructed. At this time,
When a write operation is instructed by the write/erase instruction signal W/E, the write voltage Vwr is supplied to the functional block M at a time determined by the rewrite voltage supply timing signal φwe. Further, when an erase operation is instructed by the write/erase instruction signal W/E, the erase voltage Ver is supplied to the functional block M at a time determined by the rewrite voltage supply timing signal φwe. Note that the write enable signal WE, which is a clock with a predetermined period at this time, is as follows.

Although not particularly limited, a change to the low level indicates the input timing of the rewrite address, and a change to the high level indicates the input timing of the rewrite data, and the write voltage Vwr and the erase voltage V
The supply start timing of er is set to a predetermined timing corresponding to this clock cycle.

The timer circuit TM receives a rewrite voltage supply timing signal φwe that determines the supply time of the rewrite voltage (Vwr, Ver) to be output from the rewrite control circuit WEC.
The rewriting voltage supply time is
It is controlled by the operation of the timer control circuit TMCONT.

The timer circuit TM may be an oscillation circuit such as a ring oscillator, but not limited to it, as shown in FIG.
5C1 and a counter CUNT that divides its oscillation frequency
Consisted of. The output of the counter CUNT is configured to be selectable via switch elements Qa to Qn so that different division ratios can be obtained for each oscillation frequency. Switch elements Qa to Qn are connected to a decoder circuit DEC.
One of them is controlled to be on based on the output signal of the. Therefore, switch element Qa
A desired frequency division ratio, that is, a desired rewriting time can be set by controlling which of Qn to Qn is turned on.

The data supplied to the decoder circuit DEC, that is, the control data Dcont that controls the rewrite voltage supply time, is not particularly limited, but may be a semiconductor nonvolatile memory element (not shown) similar to a memory cell included in the functional block (not shown).
A predetermined number of bits is programmably stored in a storage area Econt including MNOS). Such storage area Eco
Data rewriting for nt is performed in the same way as processing for a memory cell array (not shown), and at that time, normal address signal input terminals and data input/output terminals are multiplexed so that necessary address signals and rewriting data can be supplied. Can be configured.

In particular, in this embodiment, the control data Dcont can be directly supplied from the outside via a dedicated pad P that is not wire-bonded. Such a dedicated pad P, although not particularly limited, cannot be used when operating the EET"ROM on a predetermined system, so it is connected exclusively to a tester for performing reliability tests such as data retention characteristics. In the case of an EEPROM that is used and positioned as requiring control data Dcont solely for such test purposes, the control data Dcont
The cont input method is extremely effective in cases where external terminal compatibility is to be achieved with other semiconductor memory devices.

Next, the operation of the above embodiment will be explained.

For example, the rewrite voltage supply timing signal φWC when the switch element Qa shown in FIG. 2 is turned on
The rewrite time obtained by this is not particularly limited, but corresponds to a standard rewrite time that allows data retention for 10 years. On the other hand, when any of the switch elements Qb to Qn is turned on, the rewriting time is sequentially made shorter than the standard rewriting time.

For example, when long-term data retention is required, control data Dcont that can select the ON operation of the switch element Qa is set in the semiconductor nonvolatile storage area Econt with a predetermined number of bits. By supplying the setting data to the decoder circuit DEC at all times or during rewriting, the rewriting voltage supply timing signal φwe corresponding to the standard rewriting time is supplied to the rewriting control circuit WEC. In this state, data programmed into a predetermined memory cell (not shown) can be retained for the longest time guaranteed by the EEPROM.

When long-term data retention is not required, control data Dcont for selecting a short rewriting time corresponding to the required data retention time is stored in the semiconductor non-volatile storage area Eco.
Set a predetermined number of bits to nt. By supplying the setting data to the decoder circuit DEC at all times or during rewriting, a rewriting voltage supply timing signal φwe corresponding to a time shorter than the standard rewriting time is supplied to the rewriting control circuit WEC. When programming a predetermined memory cell (not shown) in this state, high-speed rewriting is possible as the time required for rewriting is shortened, and the programmed data is changed according to the shortened rewriting time. Therefore, the data can be retained for a period shorter than the maximum time guaranteed by the EEPROM.

The above rewriting time control can also be executed based on control data Dcont directly supplied from the outside via the dedicated pad P. In particular, since the dedicated pad P is not bonded to an external terminal, unlike when using the semiconductor non-volatile storage area Econt, it cannot be used for rewriting time control when operating an EEPROM on a predetermined system. Can not. Therefore, it is used exclusively when connected to a tester for performing reliability tests such as data retention characteristics.

According to the above embodiment, the following effects can be obtained.

(1) Rewrite voltage (Vwr) to be output from the rewrite control circuit WEC that supplies the voltage necessary to rewrite data to the MNOS transistor.

The supply time of the semiconductor non-volatile storage area Eco
Since the timer control circuit TMCONT is provided which performs programmable control based on the control data Dcont stored in the timer control circuit TMCONT, the supply time of the rewriting voltage can be controlled in response to the control data Dcont set in the timer control circuit TMCONT. Therefore, if long-term data retention performance is not required on a given system.

The rewrite time can be made shorter than the standard rewrite time to satisfy the requirement for high-speed rewriting.

(2) From the above effects, it is possible to perform accelerated tests by controlling the rewriting time in data retention characteristics tests, etc., which reduces the time required for screening and further improves overall test efficiency. improvement can be achieved.

(3) Since the data rewriting time can also be controlled based on the control data Dcont supplied from the outside via the dedicated pad P that is not wire-bonded, reliability such as data retention characteristics is particularly important. An FEP that requires control data Dcont for the sole purpose of being connected to a tester for testing.
In the case of ROM, the input method of the control data depends on the compatibility of external terminals with other semiconductor storage devices.
This is extremely effective in cases where a semiconductor nonvolatile storage area Econt is specifically provided.

(4) The voltage forming circuit VPG of this embodiment has an external terminal ■P
By receiving a desired level of voltage from P, the level of high voltage VPP for writing can be arbitrarily controlled.
By controlling the write voltage by supplying a desired voltage to PP, it is possible to arbitrarily control the write depth to the memory cell. Therefore, the reliability of the data retention characteristic test can be further improved by making it possible to perform the test by arbitrarily setting the write voltage, which is one of the parameters that determine the data retention characteristic.

Although the invention made by the present inventor has been specifically described above based on Examples, the present invention is not limited to the above-mentioned Examples, and various changes can be made without departing from the gist thereof.

For example, in the above embodiment, in the timer means constituted by a counter that divides the oscillation frequency of the oscillation circuit, switch elements are selected so that the outputs of the counters can each take a different division ratio with respect to the oscillation frequency. Although the case where the rewrite time is controlled is explained in 1, the present invention is not limited to this, and the rewrite time may be controlled by controlling the oscillation frequency in the oscillation circuit. It can be configured to control the resistance value and capacitance that determine the oscillation frequency.

Furthermore, in the above embodiment, the case where the control data for controlling the rewriting time is stored in a semiconductor non-volatile storage area such as MNOS, and the case where it is directly received from the outside via a dedicated pad that is not wire-bonded, was explained. However, the present invention is not limited thereto, and may be modified to a configuration in which control data is stored in other data storage means, or a configuration in which control data is directly obtained via an external terminal.

Furthermore, the memory cells in EEPROM are not limited to those made of MNOS as in the above embodiment, but can be of various types such as silicon gate N-channel type 5NO8 (silicon nitride oxide semiconductor) and floating gate type. Can be changed.

In the above explanation, the invention made by the present inventor was mainly applied to EEPROM, which is the background field of application, but the invention is not limited thereto. non-volatile semiconductor storage devices such as NVRAM (non-volatile random access memory), which has memory cells formed by combining static memory cells and non-volatile memory cells such as MNOS; , and can be applied to microcomputers that include them.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, the supply time of the rewriting voltage to be output from the rewriting control means that supplies the voltage necessary for rewriting data to the electrically rewritable semiconductor nonvolatile storage element is determined by the time period for which the rewriting voltage is stored in the predetermined semiconductor nonvolatile storage element. Since we have provided a timer control means that performs programmable control based on control data and control data supplied from the outside via a dedicated pad that is not wire-bonded, the timer control means can be controlled in a programmable manner in response to the control data set in the timer control means. By controlling the supply time of the rewriting voltage, it is possible to achieve high-speed rewriting during system operation, shortening the time for reliability tests regarding data retention characteristics, etc., and improving reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an EEPROM that is an embodiment of the present invention. FIG. 2 is a block diagram showing a detailed example of a timer circuit and a timer control circuit. FIG. 3 is an example of a memory cell in an EEFROM. Figure 4 shows an N-channel MO8FET as a circuit element to force the EEPOM memory gate to ground level.
This is an explanatory diagram when using 6M...E E P R
Machine block containing the main parts of OM, WRC... Rewriting circuit, Econt... Semiconductor non-volatile storage area,
Dcont...Control data, TMCONT...Timer control circuit, TM...Timer circuit, WEC...Rewrite control circuit, OSC...Oscillation circuit, CUNT...
Counter, DEC...decoder circuit, Qa to Qn.
...Switch element, P...dedicated pad, Q2...M
NOS transistor. 4th v! J Figure 3

Claims (1)

[Claims] 1. An electrically rewritable semiconductor non-volatile memory element, a rewrite control means for supplying a voltage necessary for rewriting data to the semiconductor non-volatile memory element, and an output from the rewrite control means. 1. A semiconductor memory device comprising: timer means for determining the supply time of the rewrite voltage to be applied; and timer control means for programmably controlling the rewrite voltage supply time determined by the timer means. 2. The semiconductor memory according to claim 1, wherein the timer control means controls the rewriting voltage supply time based on control data stored in a predetermined semiconductor nonvolatile memory element. Device. 3. Claim 1, characterized in that the timer control means controls the rewriting voltage supply time based on control data supplied from the outside via a dedicated pad that is not wire-bonded. The semiconductor storage device described above. 4. The rewriting control means arbitrarily controls the rewriting voltage based on a voltage supplied from the outside via a dedicated pad that is not wire-bonded, as set forth in claim 1. semiconductor storage device.