JP2719775B2 - Information processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system, and more particularly to an information processing system such as a microcomputer system using a batch erase EEPROM (electrically erasable and programmable read only memory). And effective technology.

[0002]

2. Description of the Related Art As a semiconductor nonvolatile memory device, an EPROM (erasable & programmable read only memory) capable of erasing stored information by ultraviolet rays,
There is an EEPROM capable of electrically erasing stored information.
EPROM is suitable for large storage capacity because the area of memory cells for storing information is relatively small.
In order to erase the stored information, it is necessary to irradiate the memory cells with ultraviolet rays, and thus the memory cells are sealed in a relatively expensive package with a window. To write or rewrite information by a programmer,
EPRO when writing or rewriting new information
M has to be removed from the system in which it is mounted.

[0003] On the other hand, the stored information of an EEPROM can be electrically rewritten while it is mounted on a system. However, in an EEPROM, the area of a memory cell constituting the EEPROM is relatively large, for example, about 2.5 to 5 times as large as the EPROM. Therefore, it is difficult to say that the EEPROM is suitable for increasing the storage capacity. Therefore, recently, an electrical erasing type EEP has been used as a semiconductor nonvolatile memory device intermediate between the two.
A so-called ROM has been developed. The electric batch erasing type EEPROM has a function of electrically erasing all memory cells formed on a chip at once or a group of memory cells among memory cells formed on a chip at once. Is a semiconductor nonvolatile memory device having In the electrically erasable EEPROM, the size of the memory cells can be reduced to that of an EPROM.

[0004] Regarding such a batch erase type EEPROM, an IEEE INTERNATIONAL SOLID-STATE CIRCUITS conference in 1980 was conducted.
CONFERENCE), pages 152-153, 1987, EE, International, Solid-State Circuits Conference (IEEE INTERNATIONAL)
SOLID-STATE CIRCUITS CONFERENCE), pages 76-77,
EE Journal of Solid State Circuits, Vol. 23, No. 5 (1988) No. 1157
Page to page 1163 (IEEE, J. Solid-State Cicuits, vol.23
(1988) pp. 1157-1163).

FIG. 16 is a schematic diagram showing a cross-sectional structure of a memory cell of an electrically erasable EEPROM, which was announced at the International Electron Device Meeting in 1987. The memory cell shown in the figure has a structure very similar to that of a normal EPROM memory cell. That is, a memory cell is an insulated gate field effect transistor (hereinafter, referred to as a MOS) having a two-layer gate structure.
FET or transistor). In the figure, 8 is a P-type silicon substrate, 11 is a P-type diffusion layer formed on the silicon substrate 8, 10 is a low-concentration N-type diffusion layer formed on the silicon substrate 8, 9
Are N-type diffusion layers formed on the P-type diffusion layer 11 and the N-type diffusion layer 10, respectively. 4 is a floating gate formed on the P-type silicon substrate 8 via a thin oxide film 7; 6 is a control gate formed on the floating gate 4 via an oxide film 7;
3 is a drain electrode and 5 is a source electrode. That is,
The memory cell shown in the figure is constituted by an N-channel type MOSFET having a two-layer gate structure, and information is stored in this transistor. Here, the information is substantially held in the transistor as a change in the threshold voltage.

Hereinafter, unless otherwise specified, a case where a transistor for storing information (hereinafter, referred to as a storage transistor) in a memory cell is of an N-channel type will be described. The operation of writing information to the memory cells shown in FIG. 16 is similar to that of the EPROM. That is, the write operation is performed by injecting hot carriers generated near the drain region 9 connected to the drain electrode 3 into the floating gate 4. Due to this write operation, the threshold voltage of the storage transistor as viewed from the control gate 6 becomes higher than that of the storage transistor which has not performed the write operation.

On the other hand, in the erasing operation, a high electric field is generated between the floating gate 4 and the source region 9 connected to the source electrode 5 by grounding the control gate 6 and applying a high voltage to the source electrode 5. Then, electrons accumulated in the floating gate 4 are drawn out to the source electrode 5 through the source region 9 by utilizing a tunnel phenomenon through the thin oxide film 7. As a result, the stored information is erased. That is, the threshold voltage of the storage transistor as viewed from its control gate 6 is lowered by the erase operation. In the read operation, the voltage applied to the drain electrode 3 and the control gate 6 is set so that weak writing to the memory cell, that is, undesired carrier injection into the floating gate 4 is not performed. Limited to relatively low values. For example, a low voltage of about 1 V is applied to the drain electrode 3 and a low voltage of about 5 V is applied to the control gate 6.
By detecting the magnitude of the channel current flowing through the storage transistor based on these applied voltages, “0” and “1” of the information stored in the memory cell are determined.

In general, in electrical erasing, if erasing is continued for a long time, the threshold voltage of the storage transistor may be a negative value unlike the threshold voltage of the storage transistor in a thermal equilibrium state. On the other hand, when erasing stored information with ultraviolet rays as in an EPROM, the threshold voltage of the storage transistor, which is changed by the erasing operation, settles to the threshold voltage when the storage device was manufactured, that is, The threshold voltage of the storage transistor after the erasing operation can be controlled by manufacturing conditions or the like when manufacturing the storage device. However, when the stored information is electrically erased, the stored information is erased by extracting the electrons accumulated in the floating gate to the source electrode. During the operation, more electrons are extracted than the amount of electrons injected into the floating gate. Therefore, if electrical erasure continues for a relatively long time,
The threshold voltage of the storage transistor becomes a value different from the threshold voltage when manufactured. In other words,
When the erasing operation is performed, the threshold voltage is not settled according to the manufacturing conditions at the time of manufacturing, in contrast to the EPROM. The present inventors measured a change in threshold voltage of a storage transistor due to electrical erasure.

FIG. 8 shows the relationship between the erasing time and the threshold voltage of the storage transistor which is changed by erasing, obtained by this measurement. In the figure, the horizontal axis represents the erase time, and the vertical axis represents the threshold voltage of the storage transistor.
s indicates that the threshold voltage is a positive voltage, and -Vths indicates that the threshold voltage is a negative voltage. Vthv indicates a variation in the threshold voltage after erasing due to a variation in manufacturing conditions and the like. From this figure, it will be understood that the threshold voltage changes to a negative voltage when erasing is continued for a relatively long time.

It will also be understood that the threshold voltage obtained by the erasing operation may vary from storage transistor to storage transistor due to variations in manufacturing conditions and the like.
It can also be understood from the figure that the variation of the threshold voltage increases with the erasing time. That is, as the erase time becomes longer, the difference in threshold voltage between the two storage transistors becomes larger. As described above, when the threshold voltage of the storage transistor becomes negative, the read operation is adversely affected.

This will be described with reference to FIG. Now, consider a case where stored information is read from the written memory cell 12. Reference numeral 17 in the figure denotes a sense amplifier.
In order to bring the memory cell 12 into the selected state, a selection voltage at the time of a read operation, for example, a power supply voltage Vcc (5 V) is applied to the word line 13 to which the memory cell 12 is coupled, and the selected voltage is applied to other memory cells 14 and the like. In order to set the non-selected state, the word line 15 and the like are set to a non-selected voltage at the time of a read operation, for example, the circuit ground potential 0V. If the threshold value of the non-selected memory cell 14 connected to the data line 16 corresponding to the memory cell 12 from which the storage information is to be read is negative, the voltage of the word line 15, that is, , Even if the voltage of the control gate of the memory cell is set to 0 V, the data line 16 via the memory cell 14 in the non-selected state.
An undesired current (non-selective leak current) flows through the memory cell, causing a delay in the read time and an erroneous read.

Also, during a write operation, there is an adverse effect if the threshold voltage of the storage transistor in the memory cell is negative. Normally, in a write operation using hot carriers, a high voltage (V
pp) is applied to the drain region of the storage transistor in the memory cell via the MOSFET. The above MOSFET
The voltage drop at depends on the current flowing through it. Therefore, under the condition where the threshold voltage of the storage transistor becomes a negative value as described above, the voltage drop in the MOSFET becomes too large and the voltage applied to the drain of the storage transistor in the memory cell becomes , The voltage drop. As a result, the time required for writing increases. Therefore, E
In the EPROM, the value of the threshold voltage after erasing must be controlled with high accuracy.

In order to realize electrical erasure of stored information,
In conventional EEPROMs, such as those described on pages 152-153 of the IEE, International, Solid-State Circuits Conference of 1980 above, each of the memory cells is comprised of a storage transistor and a serially connected storage transistor. And a selection transistor for blocking non-selective leakage current. In this EEPROM, a program line is connected to the control gate of the storage transistor, and a select line is connected to the gate of the select transistor. That is, the storage transistor and the selection transistor are coupled to different word lines.

FIG. 18 shows a diagram of the IEE, INTERNATIONAL, Solid-
A cross-sectional view of a memory cell of an electrically erasable EEPROM described in pages 76 to 77 of the State Circuits Conference is shown. The operation of this memory cell is almost the same as that of the memory cell shown in FIG. 16, except that the storage information is erased differently from the memory cell of FIG. This is done using phenomena. In this memory cell, there is only one gate electrode to be connected to the word line, but it can be considered that the memory cell is substantially composed of two transistors. That is, it can be considered that a memory cell is constituted by a selection transistor and a storage transistor in which a gate electrode and a control gate electrode are integrated.

Since the memory cell substantially has the selection transistor as described above, the problem of the non-selection leakage current at the time of reading is solved. However, the write operation is performed by hot carriers that require a larger amount of current than when the tunnel phenomenon is used.
The adverse effect at the time of the write operation described above is not improved.

EEPROM, eg, page 152 of the IEE, International, Solid-State Circuits Conference of 1980 mentioned above.
153, one memory cell is formed by a storage transistor and a selection transistor connected to different word lines. On the other hand, the memory cell of the electrically erasable EEPROM shown in FIGS. 16 and 18 is constituted by one storage transistor connected to one word line.

This becomes clearer when the memory cells and the like shown in FIGS. 16 and 18 are represented by circuit diagrams. Therefore, FIGS. 19A and 19B are circuit diagrams of the above memory cells. In FIG. 19B,
A schematic diagram of the memory cell published by IEE, International, Solid-State Circuits Conference, 1980, is shown. In the figure, W1 and W2 indicate different word lines, and D indicates a data line. Qs indicates a selection transistor, and Qm indicates a storage transistor.

FIG. 19 (A) shows the state shown in FIGS.
3 shows a circuit diagram of the memory cell shown in FIG. As can be understood from the figure, one memory cell has its control gate connected to one word line and one data line D.
, And one storage transistor Qm whose source is connected to one source line S. During read and write operations,
In order to select a desired one memory cell from a plurality of memory cells, in FIG.
When one data line is selected, one memory cell connected to the selected word line W and connected to the selected data line D can be selected. In other words, one word line and one data line make one word line.
Memory cells can be defined. Note that FIG.
In (A), the source line S is common to the source lines S of all the other storage transistors formed on the chip, or the source line S is common to a predetermined number of memory cells forming one memory block. Is done.

Since the memory cell shown in FIG. 19A can be constituted by one storage transistor, the area on the chip required to form the memory cell is reduced by EPROM.
Can be made as small as that of. However, it is indispensable to be able to control the threshold voltage of the storage transistor after erasing in order to realize electrical batch erasure of stored information.

In order to do this, it is necessary to repeat the operation of performing erasure several times, reading each time erasure is performed, confirming whether erasure is sufficient, and erasing again if not sufficient. There is. IEE Journal of Solid State Circuits,
Vol. 23, No. 5, (1988), pp. 1157 to 1163, proposes an algorithm for controlling the threshold voltage after such erasure. In the above-mentioned document, it is described that this algorithm is executed by an external microprocessor provided separately from the electrically erasable EEPROM. Also, in order to secure the lower limit voltage Vccmin of the operable power supply voltage during normal reading,
At the time of reading during the above algorithm (at the time of erase verify)
Describes that a verify voltage is generated in an EEPROM chip.

[0021]

In the above prior art,
Since the above-mentioned algorithm is executed by the microprocessor, the electrical erase-type EEPR
It is complicated to execute the erasing operation while the OM is mounted on the system. Further, since a relatively long time is required for erasing the stored information, the microprocessor is occupied by the erasing operation of the EEPROM for a relatively long time, and the system is virtually stopped. Have a problem.

An object of the present invention is to provide an information processing system in which electrical erasure is substantially realized while an EEPROM is mounted on a system without lowering the throughput of the system. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0023]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, after an erasing operation is performed in accordance with an external erasing instruction in an electrically erasable EEPROM having a memory array in which storage transistors (nonvolatile storage elements) electrically erasable are arranged in a matrix, An erase control circuit that performs at least one read operation on the nonvolatile memory element that has performed the erase operation and controls the continuation and stop of the erase operation based on the read information is incorporated. In accordance with an erasing instruction from the microprocessor in that state, the erasing operation is automatically performed by the erasing control circuit in the EEPROM in a state electrically disconnected from the microprocessor. I do.

According to the above-described means, the EEPROM itself has an automatic erasing function accompanied by reading for confirming whether or not stored information has been erased. The control from the microprocessor to the EEPROM takes only a short time to instruct the start of erasure, and the load on the microprocessor is significantly reduced, and as a result, the throughput of the system can be improved.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 20 shows an electrically erasable EEPROM (hereinafter referred to as a flash EEPROM) to which the present invention is applied.
(Also referred to as a ROM). Each circuit block shown in FIG. 1 is not particularly limited, but is formed on one semiconductor substrate by a well-known semiconductor integrated circuit technology. Further, in the same figure, a mark “○” indicates an external terminal provided in the flash EEPROM.

In the present application, in the drawings, the notation of logical symbols follows a general notation in order to facilitate understanding of the invention. For example, a signal whose low level is an active level is overwritten with an alphabet indicating a control signal, but in the specification, a signal corresponding to the signal is represented by ending with B (meaning a bar). For example, the chip enable signal is represented as CEB.

In the figure, M-ARY-0 to M-AR
Each of Y-7 is a memory array having the same configuration as each other, and is not particularly limited, but includes a plurality of word lines, a plurality of data lines arranged to intersect these word lines, And a memory cell provided at each intersection of the data line.

XADB is a row address buffer which receives an external row address signal AX supplied via an external terminal and forms an internal complementary row address signal corresponding to the row address signal AX. XDCR is a row address decoder, and the row address buffer XADB
And decodes the internal row address signal. Although not particularly limited, in this embodiment, the row address buffer XADB and the row address decoder XDCR are common to the memory arrays M-ARY-0 to M-ARY-7. That is, the row address decoder XDCR decodes the internal complementary row address signal, thereby providing the memory arrays M-ARY-0 to M-ARY-0.
A word line selection signal for selecting one word line specified by the external row address signal AX is formed from a plurality of word lines in each of the ARY-7. Thereby, one word line is selected from each of the memory arrays M-ARY-0 to M-ARY-7.

In the figure, YADB is a column address buffer which receives an external column address signal AY supplied via an external terminal and forms an internal complementary column address signal according to the external column address signal AY. YDCR is a column address decoder which decodes the internal complementary column address signal formed by the column address buffer YADB and forms a data line selection signal according to the external column address signal AY. Although not shown in the figure, the memory array M-ARY-
Each of 0 to M-ARY-7 receives the data line selection signal and receives one of the plurality of data lines in the memory array designated by the external column address signal AY.
A column switch is provided for coupling the data lines to a common data line (not shown) corresponding to the memory array.

Thus, the memory array M-ARY
In each of −0 to M-ARY-7, one word line and one data line are selected according to the external row address signal AX and the external column address signal AY, and the selected word line and data line are selected. The memory cell provided at the intersection with is selected. That is, a memory cell coupled to the selected word line and data line is selected from a plurality of memory cells in all memory arrays. As a result, one memory cell is selected from each memory array.

Although not particularly limited, in the present embodiment, a write operation or a read operation is performed on a memory cell selected from each memory array almost simultaneously. That is, the writing or reading operation of information is performed in units of 8 bits. For this purpose, the EEPROM of this embodiment has eight external input / output terminals I / O.
0 to I / O7, and the memory array M-AR
A data input buffer DIB, a data output buffer DOB, and a sense amplifier SA are provided between Y-0 to M-ARY-7 and the corresponding external input / output terminals I / O0 to I / O7.
And MOSFETs Q18 and Q16 for switches.

Taking the memory array M-ARY-0 as an example, in the case of a write operation, the selected memory cell is turned on by the write control signal wr.
Data input buffer DIB- via OSFET Q18
0 for the read operation.
MOS turned on by read control signal re
It is coupled to the input node of sense amplifier SA-0 via FET Q16. The input node of the data input buffer DIB-0 is coupled to the external input / output terminal I / O0, and the output node of the sense amplifier SA-0 is coupled via the data output buffer DOB-0. The remaining memory arrays M-ARY-1 to M-ARY-7 are also coupled to the external input / output terminals I / O1 to I / O7 in the same manner as the above-mentioned memory array M-ARY-0.

In the figure, LOGC is an internal circuit for performing an automatic erase control operation, and will be described later in detail. Reference numeral CNTR denotes a timing control circuit, which responds to an external signal or voltage supplied to the external terminals CEB, OEB, WEB, EEB, and Vpp and a signal from the internal circuit LOGC to control the above-described control signals wr, re. And the like. In the figure, Vcc is an external terminal for supplying a power supply voltage Vcc to each timing block, and Vss is an external terminal for supplying a circuit ground potential Vss to each circuit block. In the above description, the word line is divided for each memory array, but the word line may be shared for each memory array.

FIG. 1 shows one memory array M-AR in the flash EEPROM shown in FIG.
Y, peripheral circuits thereof, a row address buffer, a column address buffer, a row address decoder, a column address decoder, a timing control circuit CNTR, and an internal circuit L
A detailed block diagram of the OGC is shown. As can be easily understood from the above description, each circuit element shown in FIG. 1 is not particularly limited. It is formed on such a semiconductor substrate. In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by adding an arrow to its channel (back gate) portion. This is the same in other drawings.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. The N-channel MOSFET includes a source region, a drain region formed on the surface of the semiconductor substrate, and a polysilicon layer formed on the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film. It consists of such a gate electrode. P-channel MOSFET
Are formed in an N-type well region formed on the surface of the semiconductor substrate. Thus, the semiconductor substrate forms a common substrate gate of the plurality of N-channel MOSFETs formed thereon, and is supplied with the ground potential Vss of the circuit. N
The mold well region has a P-channel MO formed thereon.
Construct the substrate gate of the SFET. P channel MOS
The power supply voltage Vcc is supplied to the substrate gate of the FET, that is, the N-type well region. However, the N-type well region where the P-channel MOSFET is formed, which constitutes a circuit for processing a high voltage higher than the power supply voltage Vcc, is not particularly limited, but a high voltage applied from outside via the external terminal Vpp is used. Vpp or a high voltage generated inside the EEPROM is supplied.

Alternatively, the integrated circuit may be formed on a semiconductor substrate made of single-crystal N-type silicon. In this case, the N-channel MOSFET and the nonvolatile memory element are P
A P-channel MOSFET is formed on an N-type semiconductor substrate.

The flash EEPROM according to this embodiment will be described below.
Will be described in more detail with reference to FIG. 1. However, in order to facilitate understanding, the following description may overlap the description of FIG. 20 described above.

Although not particularly limited, the flash EEPROM of this embodiment has X (row) and Y (column) address signals AX and AY externally supplied through external terminals.
An internal complementary address signal is formed by the address buffers XADB and YADB receiving the data.
It is supplied to DCR and YDCR. Although not particularly limited,
The address buffers XADB and YADB are activated by the internal chip select signal ceB, take in the external address signals AX and AY supplied from the external terminals, and have a phase opposite to that of the external address signals supplied from the external terminals. And a complementary address signal composed of the internal address signal. The address buffer XAD
B and YADB include a signal ES indicating an erase mode and an internal address signal A in addition to the chip selection signal ceB described above.
XI, AYI, etc. are supplied. However, these signals ES, AXI, YAI, etc. are used in an erase mode described later, and in a normal write or read mode, the address buffer AXD is used.
It does not affect the operation of B and YADB.

The row (X) address decoder XDCR is
The selection signal is activated by the address decoder activation signal DE and selects one word line according to the complementary address signal from the corresponding address buffer XADB from a plurality of word lines in the memory array M-ARY. .

Column (Y) address decoder YDCR
Is also activated by the address decoder activation signal DE, and connects one data line according to the complementary address signal from the corresponding address buffer YADB to the memory array M-.
A selection signal for selecting from a plurality of data lines in ARY is formed.

The memory array M-ARY includes a plurality of word lines, a plurality of data lines arranged to intersect the word lines, and a plurality of memories provided at each intersection of the word lines and the data lines. And a cell. FIG. 1 exemplarily shows a part of the memory array M-ARY as a representative. That is, in FIG. 1, the word lines W1, W2 of the plurality of word lines, the data lines D1, D2, Dn of the plurality of data lines, and the intersections between these data lines and the word lines are provided. Memory cells are illustrated by way of example. Each of the memory cells is shown in FIG.
As described above, the memory cell is constituted by one storage transistor (nonvolatile storage element). That is, each of the memory cells is constituted by one storage transistor having a stacked gate structure having a control gate and a floating gate. The memory cell exemplarily shown in FIG. 1 includes storage transistors (nonvolatile storage elements) Q1 to Q6. As described above, the storage transistor is not particularly limited.
It has a structure similar to that of a storage transistor of a ROM.
However, the point that the erasing operation is electrically performed by utilizing the tunnel phenomenon between the floating gate and the source region coupled to the source line CS as described above or later will be described below. It differs from the EPROM erasing method that was used.

In the memory array M-ARY, the storage transistors Q1 to Q3 (Q4 to
The control gate (selection node of the memory cell) of Q6) is connected to a corresponding word line W1 (W2), and storage transistors Q1 and Q4 arranged in the same column.
To Q3 and Q6 (input / output nodes of memory cells) are connected to corresponding data lines D1 to Dn, respectively. The source region of the storage transistor is coupled to a source line CS.

In this embodiment, although not particularly limited, an N-channel MOSFET Q10 and a P-channel MOSFET Q17, which are switch-controlled by the erase circuit ERC, are connected to the source line CS. The erase circuit ERC turns on the N-channel MOSFET Q10 in the write mode and the read mode so that the ground potential Vss of the circuit is applied to the source line CS. On the other hand, in the erase mode, the P-channel MOSFET Q17 is turned on so that the high voltage Vpp for erasing is applied to the source line CS.

In order to enable partial erasure of the memory array M-ARY, storage transistors arranged in a matrix are vertically divided into M blocks, and each block corresponds to the source line. Source lines are provided for each. As described above, each of the source lines CS provided in each block is provided with the above-described erase circuit ERC and MOSFETs Q10 and Q17. In this case, it is necessary to specify each erase circuit by an address signal in order to determine which block of a plurality of blocks is to be erased. In the above embodiment, the memory array M-AR
The storage information of all the memory cells constituting Y is erased collectively. In this case, the number of source lines CS is one, and the erase circuit ERC and MOSFETs Q10 and Q17 are provided correspondingly.

In the EEPROM of this embodiment, although there is no particular limitation, since writing / reading is performed in units of a plurality of bits such as 8 bits, the memory array M-ARY is configured as shown in FIG. 8 sets in total (M
-ARY-0 to M-ARY-7). When writing or reading information in units of 16 bits, for example, 16 sets of the memory array M-ARY are provided.

Each of the data lines D1 to Dn constituting the one memory array M-ARY is connected via a column (column) selection switch MOSFET Q7 to Q9 (column switch) for receiving a selection signal formed by the column address decoder YDCR. And selectively connected to the common data line CD. The common data line CD has an output terminal of a write data input buffer DIB for receiving write data input from an external terminal I / O connected to a switch MOSFET Q18.
Connected via Similarly, for the remaining seven memory arrays M-ARY, as described in FIG.
A column selection switch MOSFET similar to the above is provided, and a selection signal is supplied from the column address decoder YDCR. A different column address decoder is provided for each memory array, and a column selection switch MOS
The FETs may be switch-controlled by a selection signal from a corresponding column address decoder.

The common data line CD provided corresponding to the memory array M-ARY has a switch MOSFET Q
16 is coupled to an input terminal of a first-stage amplifier circuit constituting an input-stage circuit of the sense amplifier SA. For convenience, the MOSFET constituting the above-mentioned first-stage amplifier circuit
A circuit composed of Q11 to Q15 and cascaded CMOS inverter circuits N1 and N2 is called a sense amplifier SA. During normal reading, a relatively low power supply voltage Vcc is applied to the sense amplifier SA.
A power is supplied to the power supply voltage terminal Vcc / Vcv as a power supply, and the voltage Vcv having a potential lower than the value of the power supply voltage Vcc is supplied as the power supply to the power supply power supply voltage terminal Vcc / Vcv at the time of the erase verify described later.

The common data line C shown as an example above
D is M which is turned on by the read control signal re.
N-channel type amplification MO through OSFET Q16
Connected to the source of SFET Q11. This amplification MOS
Between the drain of the FET Q11 and the power supply voltage terminal Vcc / Vcv of the sense amplifier SA, a P-channel load MOSFE having a gate to which the ground potential Vss of the circuit is applied.
TQ12 is provided. The above load MOSFET Q1
2 performs an operation of flowing a precharge current to the common data line CD for a read operation.

In order to increase the sensitivity of the amplification MOSFET Q11, the voltage of the common data line CD via the switch MOSFET Q16 is changed to an N-channel drive MOSFET.
A driving MOSFET Q which is an input of an inverting amplifier circuit including a TQ13 and a P-channel type load MOSFET Q14.
13 gates. The output voltage of the inverting amplifier circuit is supplied to the gate of the amplifying MOSFET Q11. Further, in order to prevent the sense amplifier SA from consuming unnecessary current during the non-operation period of the sense amplifier SA, an N-channel MOSFET is provided between the gate of the amplification MOSFET Q11 and the ground potential point Vss of the circuit.
An ETQ 15 is provided. The operation timing signal scB of the sense amplifier is commonly supplied to the gates of the MOSFET Q15 and the P-channel MOSFET Q14.

At the time of reading data from the memory cell, the sense amplifier operation timing signal scB is set to the low level. As a result, the MOSFET Q14 is turned on,
OSFET Q15 is turned off. A storage transistor forming a memory cell has a threshold voltage that is higher or lower than a selection level of a word line at the time of a read operation, in accordance with previously written data.

In the read operation, the memory array M is controlled by the address decoders XDCR and YDCR described above.
-1 selected from a plurality of memory cells constituting ARY
When the memory cells are in the off state despite the word line being at the selected level, the common data line CD is limited to a relatively low potential by the current supplied from the MOSFETs Q12 and Q11. Become high level. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to the low level limited to a relatively high potential.

In this case, the high level of the common data line CD is set to the inverting amplifier circuit (MO) receiving this high level potential.
The relatively low level output voltage formed by the SFETs Q13 and Q14) is supplied to the gate of the MOSFET Q11, whereby the voltage is limited to a relatively low potential as described above. On the other hand, the low level of the common data line CD is an inverting amplifier circuit (MOSFE) receiving this low level potential.
By supplying the relatively high level voltage formed by TQ13, Q14) to the gate of MOSFET Q11, the voltage is limited to a relatively high potential as described above.
The data line discharge MOSFETs Q19 to Q21 provided between each of the data lines D1 to Dn and the source line have the gate bias signal DS supplied to their gate at an intermediate level as described later, so that the column address decoder YD
The data lines not selected by the CR, that is, the data lines in the non-selected state are discharged.

The amplification MOSFET Q11
Performs an amplifying operation of a gate-grounded source input, and transmits its output signal to the input of the CMOS inverter circuit N1.
The CMOS inverter circuit N2 has a signal S0 obtained by shaping the output signal of the CMOS inverter circuit N1 (the memory array M-ARY in FIG.
RY-0) and transmit it to the input of the corresponding data output buffer DOB # 0. Data output buffer DO
When B # 0, the signal S0 is amplified and transmitted from the external terminal I / O0.

The data output buffer is provided with the following functions in addition to the read data output function described above. As will be described later with reference to FIG. 11, data output buffers DOB-0 to DOB-6 corresponding to I / O0 to I / O6 among the eight external input / output terminals are provided with data output buffer activation signals DO and DOB. Performs a three-state output operation including high impedance. On the other hand, the data output buffer DOB corresponding to the external input / output terminal I / O7
-7 is controlled by data output buffer activating signal signals DO7 and DO7B different from the signals DO and DOB. This data output buffer DOB-7 has an EEPR
It is used in a data polling mode in which the internal erase state of the OM is read out.

The write data supplied from the external input / output terminal I / O is transmitted to the common data line CD via the data input buffer DIB. As shown in FIG. 20, even between a common data line corresponding to another memory array M-ARY and an external input / output terminal, a read operation including the same input stage circuit, sense amplifier SA, and data output buffer DOB is performed. And a write circuit including a data input buffer DIB.

Although the timing control circuit CNTR is not particularly limited, the external terminals CEB, OEB, WEB, EEB
(Hereinafter sometimes simply referred to as signals CEB, OEB, WEB and EEB), and a chip enable signal CEB and an output enable signal OE supplied to Vpp.
B, a write enable signal WEB, an erase enable signal EEB, a write / erase high voltage Vpp, a prewrite pulse PP supplied from an internal circuit LOGC for controlling an automatic erase operation as described later, and a signal ES indicating an erase mode. , Decoder control signal DC, erase verify signal E
V, an internal timing signal such as an internal control signal ceB, an operation timing signal scB of the sense amplifier, etc., are formed in accordance with the automatic erase mode setting delay signal AED, the sense amplifier activation signal VE at the time of verification, and the like, and are selected by an address decoder or the like. The voltage is switched between a low voltage Vcc for reading, a low voltage Vcv for erasure verification, and a high voltage Vpp for writing, and any one of these voltages is selectively output.

Each of the signals PP, ES, DC, EV, AED, VE, etc., formed by the internal circuit LOGC is used in a timing control circuit CNTR in a mode other than the erase mode.
Does not affect the operation of. That is, the signals PP, ES, DC, EV, AED, VE, etc. are made valid only in the erase mode, and various signals for the erase operation corresponding to these signals are generated by the timing control circuit CNTR. You.

FIGS. 6 and 7 are circuit diagrams of an embodiment of a main part of the timing control circuit CNTR. Table 1 below shows the flash EE via the external terminal.
Each external signal supplied to the PROM and an operation mode corresponding to the external signal are shown. Table 2 shows some internal timing signals among the internal timing signals formed based on each external signal. In these Tables 1 and 2, H is a high level, L is a low level, and Vpp is a voltage (for example, about 12 V) higher than the power supply voltage Vcc (for example, 5 V).
V). In the column of the external terminal I / O in Tables 1 and 2, Hz indicates a high impedance state,
Indicates data input and output indicates data output.
output (I / O7) indicates that the external input / output terminal I / O7 is a data output.

In Tables 1 and 2, * indicates that the signal may be at a high level (H) or a low level (L), and O indicates that the signal is supplied from the internal circuit LOGC to the timing control circuit CNTR. It indicates that the level changes. How to read Tables 1 and 2 will be described by taking a read mode as an example. The same applies to other modes, so that it can be easily understood from the following example.

[0060]

[Table 1]

[0061]

[Table 2]

A low level (L) chip enable signal CEB, an output enable signal OEB, a high level (H) write enable signal WEB, and an erase enable signal EE are externally supplied to the flash EEPROM.
When B is supplied and a low voltage such as the power supply voltage Vcc is applied to the external terminal Vpp of the flash EEPROM, it is determined that the read mode is instructed by the timing control circuit CNTR, and the timing control circuits CNTR and CNTR The internal circuit LOGC includes internal signals VP, E
V, wp, wr, AED, DC, ES, POLM, PP
Are set to low level (L), and the internal signals SC, r
e and DE are set to a high level (H). Then, the data held in the memory cell designated by the address signal is transferred to the external input / output terminals I / O0 to I / O0.
Output from I / O7.

In this specification, the same signal or the same terminal is denoted by the same symbol. Further, in the drawings, a signal represented by a symbol having a letter “─” at the top of an alphabetic character is represented by a signal represented by the same alphabetic letter, and a signal represented by a signal without a letter “─” at the top. 3 shows a signal whose phase has been inverted. For example, the symbol vpB is a signal whose phase is inverted with respect to the signal represented by the symbol vp. Note that this signal v
p becomes a high level (Vcc) when the high voltage Vpp is applied to the external terminal Vpp, and becomes a low level (Vss) otherwise.

The operation of the circuits shown in FIGS. 6 and 7, which constitute the main part of the timing control circuit CNTR, will not be described in detail one by one. It will be easily understood.

When the chip enable signal CEB is set to the high level and a high voltage is not supplied to the external terminal Vpp, the flash EEPROM is in a non-selected state.

The chip enable signal CEB is set to low level, the output enable signal OEB is set to low level, the write enable signal WEB is set to high level, the erase enable signal EEB is set to high level, and a high voltage is supplied to the external terminal Vpp. Otherwise, the read mode is set as described above, the internal chip enable signal ceB goes low, the address decoder activation signal DE and the operation timing signal s of the sense amplifier are turned on.
Each of c and the read signal re is set to a high level.

At this time, the address decoder XDC
R, YDCR and data input circuit DIB
A low voltage Vcc (about 5 V) is supplied from the timing control circuit CNTR as the operation voltage. As a result, the sense amplifier SA enters an operating state, and the above-described read operation is performed. At this time, the data line discharge MOSFET inactivation signal SB is set to the low level by the circuit shown in FIG. In response to this, N-channel MOSFET (FIG. 7) receiving inactivation signal SB is turned off, and P-channel MO also receiving inactivation signal SB is turned off.
The SFET (FIG. 7) is turned on. At this time, since the sense amplifier operation timing signal sc is set to the high level, the N-channel MOSFET receiving this signal sc
(FIG. 7) is turned on, and P receives the signal sc.
The channel MOSFET (FIG. 7) is turned off.
Therefore, the data line discharge MOSFET gate bias signal DS is connected to two P-channel MOSFETs in series.
According to the conductance ratio between ET (FIG. 7) and the three N-channel MOSFETs (FIG. 7), the voltage becomes an intermediate voltage. Of the data line is discharged.

The chip enable signal CEB is set to low level, the output enable signal OEB is set to high level, the write enable signal WEB is set to low level, the erase enable signal EEB is set to high level, and a high voltage (for example, If about 12 V) is supplied, the writing mode is set. At this time, the internal chip enable signal ceB goes low, and the address decoder activation signal DE and the write mode signal W
P, the write control signal wr, and the write pulse PG are each set to the high level, and the gate bias signal DS, the sense amplifier operation timing signal scB, the read control signal re, the data output buffer activation signals DO and DO7 are provided.
Are each set to a low level.

Each of the address decoders XDCR and YDCR is activated by the high level of the signal DE, and the external address signals AX, AX,
One word line and one data line specified by AY are selected. At this time, the address decoder XDC
The high voltage Vpp is applied to the R, YDCR and data input buffer DIB as the operating voltage of the timing control circuit C.
Supplied from NTR. As described above, since the read control signal re is set to the low level at this time,
The FET Q16 is turned off, and the gate bias signal D
The discharge MOSFETs Q19 to Q21 are also turned off by the low level of S, and the sense amplifier SA is deactivated by the low level of the sense amplifier operation timing signal scB. At this time, since data output buffer activation signals DO and DO7 are at the low level, each of data output buffers DOB-0 to DOB-7 is inactivated. The configuration of the data output buffer DOB will be described later with reference to FIG.

The potential of the word line to which the selected node of the memory cell to be written is coupled, in other words, the potential of the selected word line is changed by the address decoder XDCR supplied with the high voltage Vpp as its operating voltage. A high voltage according to the high voltage Vpp, for example, a high voltage such as about 12V is set. On the other hand, the selected data line is set to a high voltage or a low potential by the data input buffer DIB according to the information to be written.

As described above, the memory cell is constituted by the storage transistor shown in FIG. In the memory cell whose selected node is coupled to the selected word line and whose input / output node is coupled to the selected data line, that is, in the selected memory cell, the floating gate of the storage transistor constituting the selected memory cell is Is implanted, the potential of the selected data line is turned on in response to the high level of the write control signal wr.
High voltage V via TQ18 and data input buffer DIB
High voltage according to pp. As a result, a channel saturation current flows through the storage transistor, and electrons accelerated by a high electric field are ionized in a pinch-off region near the drain region coupled to the data line, generating electrons having high energy, so-called hot electrons.

On the other hand, the potential of the floating gate of this storage transistor depends on the voltage of the control gate to which the word line is coupled and the voltage of the drain region, the capacitance between the semiconductor substrate and the floating gate, and the capacitance between the floating gate and the control gate. Is determined by
As a result, hot electrons are attracted to the floating gate, and the potential of the floating gate becomes negative. By setting the potential of the floating gate to be negative, the threshold voltage of the storage transistor into which electrons are injected rises and becomes higher than before the injection of electrons.

On the other hand, in the selected memory cell, when electrons are not injected into the floating gate of the storage transistor constituting the selected memory cell, the threshold voltage of the storage transistor does not increase and is kept at a relatively low value. You.
In order to prevent electrons from being injected into the floating gate of the storage transistor that constitutes the selected memory cell, the selected data line is turned on in the drain region of the storage transistor. What is necessary is just to apply a low voltage via the MOSFET Q18 and the data input buffer DIB such that hot electrons are not generated in the pinch-off region near the drain region.

Whether the above-described high voltage is applied to the drain region of the storage transistor of the selected memory cell,
Whether to apply a low voltage as described above is determined by information to be written. The data input buffer DIB, which will be described later with reference to FIG. 22, forms the above-described high voltage or low voltage according to the information supplied through the external input / output terminal I / O, and the formed voltage is set as described above. It is transmitted to the selected data line.

In the storage transistor whose threshold voltage is increased by injection of electrons into the floating gate, a selection signal of a selection level (for example, 5 V) is supplied to its control gate in the read mode. That is, even if the word line to which the selected node is coupled is selected, the conduction state is not established but the conduction state is established. On the other hand, in the storage transistor in which the electron injection has not been performed, the threshold voltage thereof is held at a relatively low voltage. Therefore, when the selection signal of the selection level is supplied in the read mode, That is, by the operation of selecting the word line, the conductive state is established, and the current flows.

In a write mode, a high voltage is not applied to a control gate and / or a drain region of a storage transistor constituting a memory cell which is not selected. Therefore, electrons are not injected into the floating gate, and the threshold voltage of the storage transistor does not change.

The chip enable signal CEB is set to low level, the output enable signal OEB is set to low level, the write enable signal WEB is set to high level, the erase enable signal EEB is set to high level, and the high voltage Vpp is applied to the external terminal Vpp. If supplied, the mode is set to the write verify mode. External terminal Vpp
Except that the high voltage Vpp is supplied to the read mode. Address decoder XDCR, Y
The operating voltage is switched from the high voltage Vpp to the low voltage Vcc and supplied to each of the DCR and the data input circuit DIB.

The writing / writing shown in Tables 1 and 2 above
In the inhibit mode, each decoder is activated, but the high voltage Vpp for writing / erasing is not supplied to each decoder. In this mode, the gate bias signal DS is set to the high level, and the data line is discharged.

When the chip enable signal CEB and the erase enable signal EEB are set to low level, the output enable signal OEB and the write enable signal WEB are set to high level, and the high voltage Vpp is applied to the external terminal Vpp, the erase mode is set. Be started. Later in FIG.
The start of the erase mode is instructed by a combination of the voltages of these external signals.
If this state is not maintained, it does not mean that the erasing mode ends.

The erasing mode in the flash EEPROM of this embodiment is shown in the operation flowchart of FIG. 2 showing an example of the algorithm, a specific circuit diagram of the main part of the internal circuit LOGC shown in FIGS. FIG.
The operation will now be described in detail with reference to the operation timing chart shown in FIG. The internal circuit LOGC functions as an erase control circuit.

Since the circuits shown in FIGS. 3 and 4 perform the sequence control for executing the algorithm shown in the flowchart of FIG. 2, the operation timing chart of FIG. Will be easily understood from the description of the erase operation mode with reference to FIG.

In the flowchart of FIG. 2, a series of pre-write operations as shown by the dotted lines in FIG. 2 are executed prior to the actual erase operation. This is because the storage information of the memory cell in the memory array M-ARY before erasing, in other words, the threshold voltage of the storage transistor is determined by the presence or absence of writing as described above (the presence or absence of injection of electrons into the floating gate). To be performed according to the high and low. That is, the memory array M-AR before erasing
Y is executed because a storage transistor whose threshold voltage is increased and a storage transistor whose threshold voltage is maintained at a relatively low value are mixed in Y.

The above-described pre-write operation is to write data to all the storage transistors prior to the electrical erase operation. Thus, the internal automatic erasing according to this embodiment is performed for an unwritten memory cell (in which electrons are not substantially injected into the floating gate of the storage transistor constituting the memory cell) in a so-called erased state. By performing the operation, the threshold voltage of the storage transistor in the unwritten memory cell is prevented from becoming a negative threshold voltage.

In the prewrite operation, first, in step (1), an address is set. That is,
The address counter circuit is set so that an address signal for selecting each memory cell is generated by the address counter circuit. By the address setting, although not particularly limited, an address signal indicating an address of a memory cell to be written first is generated by the address counter circuit.

In step (2), a write pulse is generated, and write (prewrite) is performed on the memory cell designated by the address signal generated by the address counter circuit.

After this writing, step (3) is executed. In this step (3), the address increment is performed such that the address counter circuit is operated by an increment (+1).

Then, in step (4), it is determined whether or not the address signal generated by the address counter circuit indicates the final address. When the above pre-write has not been performed up to the last address (NO)
Returns to the step (2), and the prewriting is performed.
This is repeated until the last address. After the step (3) of performing the address increment as described above, it is determined whether or not prewriting has been performed up to the final address. Therefore, the actually determined address is the final address + 1. Of course, the step (3) of address increment may be provided after the step (4) of determining the final address. In this case, when the determination is NO, step (3) is provided on the path returning from step (4) to step (2) so that the address increment is performed. When the above pre-writing is performed up to the final address (YES), the following erasing operation is executed next.

In step (5), the initial setting of the address for the erase operation is performed. That is, the initial design of the address signal is performed for the address counter circuit. In this embodiment, since all the memory cells in the flash EEPROM are erased collectively, the initial setting of this address has no special meaning in the erase operation itself. This address setting is required for a verify operation (erase verify) performed after the erase operation.

In step (6), an erase pulse for batch erase is generated, and an erase operation is performed. Thereafter, a verify operation is performed in step (7) according to the address setting. In this verify operation, as will be described later, the operating voltage is lower than a low power supply voltage Vcc (for example, 5 V) supplied via the external terminal Vcc (for example, 5 V), and is lower than a low voltage Vcv such as 3.5 V. Such a read operation is performed. That is, the address decoder X
The DCR, YDCR and sense amplifier SA have the low voltage Vcv described above instead of the power supply voltage Vcc as their operating voltages.
Is supplied.

At this time, the power supply voltage V is applied to the internal circuit LOGC and the timing control circuit CNTR as their operating voltages.
cc is supplied. In this read operation, if the read signal is "0", that is, if the storage transistor is turned on, it is recognized that the threshold voltage of the storage transistor is in the erased state of 3.5 V or less. Then, step (8) is executed. In this step (8), the address of the address counter circuit is incremented.

Then, as in the case of the prewrite operation, it is determined in step (9) whether or not the address signal generated by the address counter circuit indicates the final address. If not the last address (N
In O), the process returns to step (7), and the same erase verify operation as described above is performed. By repeating this until the address counter circuit indicates the final address,
The erasing operation ends.

As described above, in the present embodiment, since the storage information of the memory array M-ARY is erased collectively, in the above-described erase operation, the threshold value is most likely to be determined by the write operation among all the memory cells. The number of erasures is determined by the storage transistor whose voltage has been increased. That is, the erasing pulse is applied (erasing operation) in step (6) until the memory transistor having the highest threshold voltage can be read out at 3.5V, that is, has a low threshold voltage. Then, whether or not the storage transistor has the low threshold voltage is detected by the erase verify operation in step (7). That is, whether or not the erase pulse is applied (erase operation) in step (6) is determined based on the verification result in step (7).

The above-described erasing operation mode will be described in detail with reference to the operation timing chart of FIG. 5 and the concrete circuits of FIGS. In the following description, FIGS. 6 and 7 and Tables 1 and 2 described above are also referred to.

A state in which the chip enable signal CEB is set to the low level, the output enable signal OEB is set to the high level, the write enable signal WEB is set to the high level, and the high voltage Vpp (for example, about 12 V) is supplied to the external terminal Vpp. In this case, as apparent from the specific circuit of the timing control circuit CNTR shown in FIG. Therefore, when the erase enable signal EEB changes from the high level to the low level, the flip-flop circuit FF1 is set accordingly.

As a result, the signal ES indicating the erasing mode changes from the high level to the low level to enter the erasing mode. The internal signal ES2B changes to a low level with a delay of a fixed time determined by the delay time of the delay circuit D1. When the signal ES indicating the erase mode changes to a high level, it is fed back to the NOR gate circuit NOR1. Therefore, the erase mode signal ES is held by this feedback operation until the erase mode signal ER is generated. Therefore, during the erase mode, the NOR gate circuit NOR1 thereafter sets CEB, OEB, WE represented by the internal signal ec.
B and EEB signal changes are no longer accepted. That is, the erase control circuit LOGC does not accept the external control signal as described above, and executes the erase sequence. In other words, the erase mode signal ES prevents a change in the external control signal from affecting the internal operation. For example, in FIG. 6, the circuit for forming the decoder activation signal DE is not affected by the signal ceB based on the chip enable signal CEB when the erase mode signal ES is set to the high level.

Before the erase operation is performed, the prewrite operation is performed. In order to perform a pre-write operation in which writing is performed for all bits for a fixed time, an address increment start signal AIS and an oscillator control signal OSC
Starts the oscillation circuit O1. The output signal of the oscillation circuit O1 is divided by a 4-bit binary counter circuit BCS1 to generate a prewrite pulse PP. The generation of the prewrite pulse PP is not limited to the one generated from the frequency-divided signals OS3 and OS4 obtained by the above-described frequency division and the prewrite control signal PC, and various modifications can be adopted. Needless to say,

The output signal of the counter circuit BCS1 is
It is supplied to a binary counter circuit BCS2. The counter circuit BCS2 operates as an address counter circuit and generates internal address signals A5I, A6I,.
Occurs. These address signals A5I, A6I.
A2I is input to the address buffers XADB and YADB. These address buffers XADB, YADB
The above-mentioned erase mode signal ES is used for switching the input of the erase mode. Each of the address buffers XADB and YADB is configured by a plurality of unit circuits having the same configuration.

FIG. 9 shows the unit circuit.
As shown in the drawing, the input of the unit circuit is changed from the external address signals AX and AY supplied via the external terminals AX and AY to the internal address signals AXI and AYI, respectively, according to the high level of the erase mode signal ES. Switched,
Internal complementary address signals ax, axB and ay, ayB to be transmitted to the address decoders XDCR, YDCR are formed. That is, due to the high level of the signal ES, the unit circuits of the address buffers XADB and YADB are not allowed to receive the external address signals AX and AY from the external terminals, and the internal address signals A5I, A6I.
-Accept internal address signals AXI and AYI corresponding to A2I.

Although not particularly limited, the above counter circuit B
CS2 forms the same number of internal address signals AXI and AYI as the external address signals AX and AY. This allows
One memory cell is selected from each memory array M-ARY by the internal address signals AXI and AYI. Information is supplied to the selected memory cell from the data input buffers DIB-0 to DIB-7 and written (pre-write). In this case, the data input buffers DIB-0 to DIB-7 are connected to external terminals I / O0 to I / O
Information is formed based on the prewrite pulse PP instead of the data from / O7.

When pre-writing is completed for all addresses of the memory array, the final address signal END goes high, and the flip-flop circuit FF2 is set. As a result, the automatic erase mode setting signal AE becomes high level, and the erase period starts. By the internal signal PSC,
Address increment signal AIS and oscillator control signal O
SC is changed to low level, and the oscillation circuit O1 and the counter circuits BCS1 and BCS2 are reset. Delay circuit D
The delay time set by 2 is a preparation period for performing erasing, and is used for setting all the word lines in a non-selected state or discharging the data lines.

Thereafter, the erase start signal ST is supplied to the delay circuit D4.
Becomes high level for a certain period of time set, and the flip-flop circuit FF3 is set. After a time set by the delay circuit D5, the erase pulse EPB goes low. By the low level of the erase pulse EPB,
The high voltage Vpp is applied to the source of the memory cell via the erase circuit ERC as described above.

Although not particularly limited, the erasing circuit ERC includes:
This is the circuit shown in FIG. The signal EPB is basically supplied to the gate of the P-channel MOSFET Q17 via an inverter circuit using the low voltage Vcc as an operating voltage and an inverter circuit having a level shift function using the high voltage Vpp as an operating voltage. Is transmitted to the gate of the N-channel MOSFET Q10 through two stages of inverter circuits having an operating voltage of. In the figure, the signal EXTE is different from the internal automatic erase mode in this embodiment,
This is an external erase mode signal that is set to a high level when the PROM performs a normal erase mode, that is, when an erase operation is performed for a period set by an external signal.

The structure and operation of the erasing circuit ERC are as follows. The NAND gate circuit receiving the erase pulse EPB substantially operates as an inverter circuit when the external erase mode signal EXTE is at a low level. Therefore, the signal EPB is supplied to the gate of the cut-off MOS transistor whose power supply voltage Vcc is constantly supplied via three inverter circuits.
A P-channel M constituting a CMOS inverter circuit using the high voltage Vpp as an operating voltage via a cutting MOSFET in which a high voltage Vpp is constantly supplied to the FET and the gate.
It is supplied to the gate of the OSFET. The output signal of the last-stage inverter circuit is supplied to the gate of the N-channel MOSFET constituting the CMOS inverter circuit.

Instead of this structure, an N-channel MOSF
The gate of ET may be connected to the gate of the P-channel MOSFET. A feedback P-channel MOSFET for receiving a level-converted output signal is provided between the gate of the P-channel MOSFET and the high voltage Vpp.
In the circuit of this embodiment, when the erasing pulse EPB is set to low level, the output of the last-stage inverter circuit is set to high level, so that the N-channel MOSFET is turned on and the output signal is set to low level. As a result, the feedback P-channel MOSFET is turned on, and the P-channel MOSFET constituting the CMOS inverter circuit is turned on.
This P-channel MOSFET is turned off to increase the gate voltage of the OSFET. Further, since the cutting MOSFET is turned off, a DC current is prevented from flowing from the high voltage Vpp to the final stage inverter circuit operating at the low voltage Vcc. As a result, the output signal is set to the low level, so that the MOSFET Q17 is turned on and the potential of the source region of the memory cell is raised to the high voltage V.
to pp.

At this time, the gate voltage of MOSFET Q10 is at a low level, so that MOSFET Q10 is turned off. When the erase pulse EPB is set to the high level, the output of the last-stage inverter circuit goes to the low level.
The OSFET is turned off and the P-channel MOSFET is turned off.
T is turned on. As a result, the output signal becomes high voltage V
high level like pp
The SFET Q17 is turned off. At this time, the feedback P-channel MOSFET is turned off by the high level of the output signal. At this time, the N-channel MOSFE
The gate voltage of TQ10 becomes high level. Thereby, MOSFET Q10 is turned on, and the source potential of the memory cell is set to the ground potential of the circuit.

Returning to FIG. 4, in FIG. 4, the oscillation circuit O2 and the binary counter circuit BCS3 output the erase pulse EPB
Is changed to the low level, and after the time determined by them has elapsed, the erase pulse end signal PE is changed from the low level to the high level, and the flip-flop circuit FF3 is reset. In response to this, the erase pulse EPB changes to the high level, so that the potential of the source of the memory cell is set to the high voltage V by the erase circuit ERC.
pp is switched to the circuit ground potential Vss.

After the delay time set by the delay circuit D7, the erase verify signal EV changes to a high level, and shifts to the erase verify mode. At this time, unlike the pre-write operation, the counter circuits BCS1 and BCS2 are electrically disconnected from each other by the automatic erase mode setting signal AE, and the counter circuit BCS1 is used to generate a reference pulse for verification. Circuit BCS2
Are used to generate an internal address signal for verification, not for prewrite.

That is, the output signal OS2 of the counter circuit BCS1 is a high-level signal in the first half of the cycle and a low-level signal in the second half of the cycle. During the low-level period, the output signals S0 to S7 (8 bits High-level / low-level determination of
Signal S of all bits output from sense amplifier SA
When 0 to S7 are at the low level, in other words, in the erased state where the threshold voltages of the eight storage transistors selected by the counter circuit BSC2 are lowered, the flip-flop circuit FF3 is not set. , Address increment signal EAI during verification
In response to the internal address signal AX indicating the next address.
I and AYI are formed by the counter circuit BSC2, and the determination is performed again during the low level period of the signal OS2.

In this manner, internal address signal A is applied in accordance with address increment signal EAI during verification.
XI and AYI are formed and the internal address signal AX
The determination of the memory cell according to I, AYI is performed. If one or more bits of the output signals S0 to S7 of the sense amplifier SA are at a high level, that is, if there is a memory cell in which even one bit has not been erased, the flip-flop circuit 3 is set by the NOR gate circuit NOR2. Then, a low-level erase pulse EPB is generated again. The above-described erase operation is performed again by the low-level erase pulse EPB, and thereafter, the above-described erase verify is executed again.

FIG. 5 shows an example in which it is determined that erasure has been performed at four addresses indicated by the internal signal OS2, and it has been determined that erasure has not been performed at the fifth address, and the verify period has ended. I have. At this time, the operation of the delay circuit D8 prevents the last pulse of the signal OS2 from appearing in the address increment signal EAI, indicating that the last pulse remains at the address determined not to be erased last. In other words, the counter circuit BSC2 holds an address signal indicating an address determined not to be erased. Therefore, although not particularly limited, the erase verify after the automatic erase is performed again is executed from the address where it was previously determined that the erase was not performed. Here, the basic pulse in the verify mode is the output signal OS2 of the frequency divider, but
Needless to say, the invention is not particularly limited to this.

When the memory cells corresponding to all the addresses are verified by repeating the above operation, the end address signal END goes high as in the case of the end of the prewrite, and the flip-flop circuit FF2 is reset. The automatic erase mode setting signal AE changes to low level in response to the reset of the flip-flop circuit FF2,
The erase mode end signal ER is set to the high level only during the delay time set by the delay circuit D9.

When the signal ER goes high, the flip-flop circuit FF1 is reset, and the delay circuit D1
After the delay time set by (1), the signal ES indicating the erase mode is changed to the high level, and the state in which the external signal is not accepted is released.

The binary counter circuit BCS4 counts the number of times the erase pulse EPB has occurred. A certain number of pulses E
If the erase mode does not end as described above even after counting PB, the abnormality detection signal FAIL is set to the high level, and the erase mode is forcibly ended. That is, an erase mode end signal ER is generated. The logic circuit forming the erase mode end signal ER includes an internal signal PSTOP.
And a gate circuit to which the end address signal END is inputted, because this mode can be terminated by an internal signal PSTOP generated by an external signal when it is not desired to perform erasing only by prewriting.

In the above description, the erase control circuit LOGC shown in FIGS. 3 and 4 will be mainly described with reference to the timing chart of FIG.
In practice, each signal generated by these erasure control circuits LOGC is transmitted to an address buffer, a decoder, and a memory through a timing control circuit CNTR.
It controls OSFET and the like.

Signals DE, SB, s shown in FIGS. 6 and 7
In the signal generation circuit for c, re, wr, PG, DO, etc., during the erase mode, the external terminal C is supplied by the signals ES, AED, etc.
The inputs of EB, OEB, WEB, EEB are invalidated and are controlled internally. For example, when the erase pulse EPB is at a low level, that is, during a period in which electrical erasing is performed,
The signal DC in FIG. 3 and FIG.
E is at a low level, and each decoder XDCR, YDCR
Becomes inactive. Therefore, all word lines and all data lines are in a non-selected state. In the other periods as well, the state is similarly determined by the output signal of the erase control circuit LOGC shown in FIGS.

The data polling mode is a mode for determining whether or not erasing is in progress. Therefore, EEPRO
It can be regarded as a mode for knowing the internal state of M, that is, a status polling mode. A state in which the chip enable signal CEB is set to low level, the output enable signal OEB is set to low level, the write enable signal WEB is set to high level, the erase enable signal EEB is set to low level, and the high voltage Vpp is supplied to the external terminal Vpp. To enter this mode. In this mode, the data polling control signal POLMB goes low in the circuits shown in FIGS. At this time, the data output buffer activation signal DO7 is set to high level, but the data output buffer activation signal DO
Is set to a low level by a data polling control signal POLMB.

FIG. 11 shows a specific circuit of the data output buffer DOB. Except for the data polling (status polling) control circuit DP, the external input / output terminal I
Data output buffer DOB corresponding to / O0 to I / O6
-0 to DOB-6 and the configuration of the data output buffer DOB-7 corresponding to the external input / output terminal I / O7 are the same in that they are three-state output circuits including a high impedance state, and read out first. As described in the mode, when the activation signals DO and DO7 become high level, the operation of inverting and outputting the output signals S0 to S7 from the sense amplifier SA is performed.

On the other hand, in the data polling mode (status polling mode), the activation signal PO
Since LMB is at the low level, the output signal S7 is invalidated, and the output signal of the terminal I / O7 is determined according to the level of the signal ES indicating the erase mode at that time. That is, during the erase mode, the signal ES indicating the erase mode is at the low level, so that a low-level signal is output from the external input / output terminal I / O7, and a high-level signal is output if the erase operation has been completed. You.

FIG. 12 shows a power supply circuit for generating the operating voltage Vcv in the erase verify mode supplied to the sense amplifier SA and the address decoders XDCR and YDCR. This circuit is configured using a known reference voltage generating circuit VREF using a silicon band gap and operational amplifier circuits OP1 and OP2. That is, the reference voltage VR formed by the reference voltage circuit VREF is amplified by the operational amplifier OP1 in accordance with the gain (R1 + R2) / R2 determined by the resistors R1 and R2 to form a voltage of about 3.5V. . This voltage is output through a voltage follower-type operational amplifier circuit OP2 to obtain the voltage Vcv.

The operational amplifiers OP1 and OP2 are activated by the automatic erase mode setting signal AE to generate the voltage Vcv. Thus, in the other operation modes, current consumption in the power supply circuit can be prevented. Note that, as the operational amplifier circuit OP2,
When an output circuit composed of a P-channel MOSFET and an N-channel MOSFET is used as the output circuit, when the operational amplifier circuit is deactivated by the signal AE, the P-channel MOSFET is turned on by the signal AE and a low voltage is applied. Is output. By employing this configuration, a function of switching between the voltages Vcc and Vcv can be added to the power supply circuit by the signal AE. As the above-mentioned reference voltage generation circuit VREF, for example, the one disclosed in British Patent No. 2081458B can be used.

In order to make the operating voltage during the above-mentioned erase verify substantially equal to the lower limit power supply voltage Vccmin at which the read operation can be performed on the flash EEPROM, the power supply voltage Vcc in the flash EEPROM in the read mode is set. It is desirable to set lower. Although it is assumed here that a power supply is built in as shown in FIG.
And a programmable power supply provided outside is controlled by this signal AE, and the voltage is applied to the voltage Vcv as in the sense amplifier SA and the address decoders XDCR and YDCR of the flash EEPROM. It may be configured to supply power to a power circuit. here,
The above-mentioned lower limit voltage Vccmin refers to the lowest power supply voltage Vcc (from the external terminal Vcc of the EEPROM) that enables reading of stored information from the memory cell having the highest threshold voltage among the memory cells constituting the EEPROM. Applied).

FIG. 23 shows an address decoder XDCR,
A circuit diagram of a unit circuit constituting the YDCR is shown.
Each address decoder is composed of a plurality of similarly configured unit circuits. However, the combination of the supplied internal address signals differs in each unit circuit. FIG. 23 shows one of these unit circuits as an embodiment.

In the figure, UDG is a unit decoder circuit, and is constituted by, for example, a NAND circuit receiving an internal address signal ax (ay) and an address decoder activating signal DE. The output signal of the NAND circuit is supplied to a level conversion circuit having the same configuration as the circuit shown in FIG. In the level conversion circuit of FIG. 23, the high voltage Vp is supplied from the timing control circuit CNTR to the node corresponding to the node to which the high voltage Vpp was supplied in FIG.
p, the power supply voltage Vcc, and the low voltage Vcv are selectively supplied. On the other hand, the power supply voltage Vcc is constantly supplied to the NAND circuit UDG.

As a result, at the time of a write operation or pre-write, the word line W (selection line C of the column switch MOSFET) designated by the internal address signal ax (ay) from the address buffer XADB (YADB).
L), the unit circuit outputs a selection signal having a voltage substantially equal to the high voltage Vpp. In the read operation, a selection signal having a voltage substantially equal to the power supply voltage Vcc is output to the word line W (selection line CL) specified by the internal address signal ax (ay). In the erase verify mode, the address buffers XADB (YAD
A selection signal having a voltage substantially equal to the low voltage Vcv is output to the word line W (selection line CL) designated by the internal address signal ax (ay) from B).

In the erase operation, the activation signal DE is set to the low level as described above, so that a voltage substantially equal to the ground potential Vss of the circuit is applied to the word line W (select line CL) from all the unit circuits. Supplied. Note that a voltage according to the ground potential Vss of the circuit is supplied to the unselected word lines W (selection lines CL). Also, as described above, at the time of pre-write and erase verify, the internal address signal AXI (AYI) formed by the counter circuit is taken into the address buffer XADB (YADB) instead of the external address signal AX (AY). An internal address signal ax (ay) corresponding to this is formed.

FIG. 22 is a circuit diagram showing one embodiment of the data input buffer DIB. The data input buffer DIB is commonly used for writing data from an external input / output terminal I / O to a memory cell and for writing predetermined data to a memory cell during prewriting. In the case of the write mode, as can be understood from Tables 1 and 2, the write mode signal wp is set to the high level, and the prewrite pulse PP is set to the low level.
Therefore, the data supplied to the external input / output terminal I / O is transmitted to the input node of the inverter via the two NOR circuits. After the data transmitted to the input node is inverted by an inverter, the data is supplied to a bias circuit composed of one P-channel MOSFET and two N-channel MOSFETs connected in series.

The data converted to a predetermined level by the bias circuit is a P channel M for writing.
It is supplied to the gate of OSFET QPI. The P-channel MOSFET QPI for writing has a common data line CD via a MOSFET QL having a predetermined bias voltage supplied to its gate and the MOSFET Q18 described above.
, And further coupled to the drain of a memory cell (storage transistor) to be written via a selected data line. The above P-channel MOSFET QP
I supplies a voltage according to the data to be written to the drain of the memory cell. As a result, data is written to the memory cells. However, if the threshold voltage of the storage transistor of the memory cell becomes negative,
The current Iw flowing through the MOSFET QL and the like increases,
The voltage drop in the MOSFET QL and the like becomes large, and sufficient writing cannot be performed as described above. On the other hand, according to the present embodiment, since the threshold voltage can be prevented from becoming negative, the current Iw can be prevented from increasing, and data can be reliably written.

At the time of the pre-write operation, since the signal wp is at a low level, data from the external input / output terminal I / O is not taken in. Instead, writing using the prewrite pulse PP as write data is performed.

FIG. 21 is a timing chart focusing on the external input signal and the external output signal in the above-described automatic erase mode. When the erase enable signal EEB changes from the high level to the low level at time t1, the latch provided inside the flash EEPROM operates to enter the automatic erase mode. Thereafter, until the erasure is completed at time t4, the flash E
The EPROM does not accept an external signal except for a combination of external signals indicating a data polling request.

After the erase enable signal EEB is kept at the low level for a certain period of time determined internally, CE
The external control signals of B, OEB, WEB, and EEB may be in any combination. In the automatic erasing mode of the present embodiment, erasing is not performed during the low level period of the erase enable signal EEB. Therefore, the above-mentioned fixed time is required for setting the latch circuit shown in FIG. 3 to a predetermined state and the like, and is sufficiently shorter than the time required for erasing the memory cell. Further, although the external address signal is not shown in this figure, it is not taken in internally, so any combination may be used.

FIG. 19 shows an example in which the data polling mode is entered at time t2. At time t3 determined by the internal signal delay, the data polling signal is
Appears at O7. Since the erasure has not been completed between the time t3 and the time t4, the output is at the low level. When the erasing ends at time t4, the level changes to a high level, and the erasing end can be detected from outside the flash EEPROM. In the automatic erase mode, the external input / output terminals I / O0 to I / O
/ O6 is in a floating state. The external input / output terminal I / O7 is also in a floating state in the automatic erase mode except for the polling mode.

FIG. 24 is a waveform diagram of the erase enable signal EE supplied from the outside when erasing the storage information of the memory cell. FIG. 24A shows the erase enable signal EE in the above-described automatic erase mode.
The waveform diagram of B is shown. FIG. 24B shows the waveform of the erase enable signal EEB when externally instructing the erase operation and the verify operation.
(C) shows a waveform when simply erasing the stored information is externally instructed by the erase enable signal EEB. These waveforms show the case of batch erasure.

In FIG. 24B, during a period EO (for example, 10 ms) during which the signal EEB is at a low level, an erase operation of a memory cell (for example, 1 byte) is actually performed, and the signal EEB is turned to a high level. Period V
At O, a verify operation involving a read operation from a memory cell (1 byte) is actually performed. FIG.
In 4 (C), during the period EO ′ (for example, 1 second) during which the signal EEB is at the low level, the erase operation is actually performed on all the memory cells on the chip.

On the other hand, in the above-described automatic erase mode, it is sufficient that the signal EEB is kept at the low level for the time required to set the latch circuit and the like shown in FIG. 3 to a predetermined state. Therefore, the erase enable signal EEB
24B is held at a low level, as shown in FIG.
It may be shorter than that shown in (C), for example, 50 ns.
Degree is fine. This is because in the automatic erasing mode, the actual erasing operation for the memory cells is not executed during the low level of the erase enable signal EEB.

In this embodiment, the internal configuration mainly for the automatic erase mode has been described.
The erasing mode shown in (C) may be executed together.

FIGS. 24D and 24E show the external address signals AX and AY and the output signal of the external input / output terminal I / O in the read cycle. To set the read mode, it is necessary to set each external signal as shown in Tables 1 and 2 above.
As described above, the external address signal and the output signal are shown. For example, from the standby mode, a desired address A
external address signals AX and AY indicating EE
By giving the data to the PROM, the data Di held at the address Ai is output from the external input / output terminal I / O. Thereafter, the EEPROM is again set to, for example, a standby mode. In this read cycle,
Since a memory cell selection operation, a sense amplifier activation, and the like are performed, the cycle time is, for example, 100 to 20
About 0 ns is required.

On the other hand, in the erase mode shown in FIG. 24A, the pulse width of the erase enable signal EEB may be as short as about 50 ns as described above. for that reason,
As will be described later with reference to FIGS. 14 and 15, it is possible to prevent a device (such as a CPU) for controlling the EEPROM from being exclusively used for the erasing operation of the EEPROM for a long time. This erase enable signal EEB [FIG.
(A)] may be shorter than the time required to actually erase the memory cell. This is because, as described above, this erase enable signal EEB does not cause an actual erase operation to be performed, but an EEPRO.
This is because an instruction of the erase operation is issued to M.

In this embodiment, the erase verify is performed for all the addresses. However, the present invention is not limited to this. It may be changed according to the required degree of control of the threshold voltage after erasing. For example,
Only one data line may be verified, or in an extreme case, only one representative bit (memory cell) may be verified. The power supply voltage V for verification
If cv can be set sufficiently lower than the required readable lower limit voltage Vccmin, a sufficiently readable lower limit power supply voltage Vccmin can usually be secured even with this method. In FIG. 5, PSTOP is a signal for a test.

FIG. 13 shows an EEP to which the present invention is applied.
A circuit diagram of another embodiment of the ROM is shown. In this embodiment, as in the embodiment of FIG. 1, only one memory array and the corresponding peripheral circuits are shown. See FIG. 20 above for the whole.

The memory cell of the EEPROM of this embodiment is configured such that electrical erasing is performed on the drain region side, instead of performing electrical erasing on the source region side as in the above embodiment. That is, in this embodiment, the memory array M-
The ARY source line CS is fixedly connected to the ground potential point Vss of the circuit.

The erasing circuit ERC and the output nodes of the P-channel MOSFET Q17 and the N-channel MOSFET Q10, which are switch-controlled by the erasing circuit ERC, are connected to a common data line CD by a P-channel type switch MOSFET Q25.
Connected via The switch MOSFET Q25 is
The erase pulse EPB as described above is applied to the gate. As a result, the switch MOSFET Q25 is turned on only during the period in which the erase pulse EPB is at the low level, and changes the high voltage Vpp output via the P-channel MOSFET Q17 that is turned on based on the low level of the erase pulse EPB to the common data. Tell the line CD. The address decoder YDCR is connected to the memory array M-A
In order to collectively erase all the memory cells in RY, the high voltage Vpp of the common data line CD is transmitted to the data lines.
For example, in response to the erase pulse EPB, all the column switch MOSFETs Q7 to Q9 are turned on.

Instead of this configuration, a column decoder YDCR
By forming a selection signal according to an internal or external address, erasing can be performed in units of data lines.
Therefore, in the EEPROM of this embodiment, the control of the address decoder YDCR at the time of the erase operation is performed by the control shown in FIG.
This is different from the embodiment. Other parts are the same as those in FIG. 1, and therefore, refer to FIG.

FIG. 14 is a block diagram showing one embodiment of a microcomputer system using a flash (FLASH) EEPROM according to the present invention.
The microcomputer system according to this embodiment includes a microprocessor CPU, a ROM (read only memory) storing programs and the like, a RAM (random access memory) used as a main memory device, and an input / output port I. / OPORT, the batch-erasable EEPROM according to the present invention, control circuit CONTROL
A liquid crystal display or a CRT (cathode ray tube) is used as a monitor connected via the LER.
S, a data bus DATA and a control signal C
They are mutually connected by a control bus for transmitting ONCONTROL.

In this embodiment, the display device LCD or C
The 12V power supply RGU required for RT operation is
It is also used as the high voltage Vpp of the ROM. For this reason, in this embodiment, the power supply RGU is supplied to the terminal Vpp during the read operation by the control signal from the microprocessor CPU.
Is switched to 5V such as Vcc. FIG. 15 shows a microprocessor CPU and an EEPROM.
The connection relation of each signal focusing on OM is shown.

Chip enable terminal CE of EEPROM
For B, an address signal indicating the address space allocated to the EEPROM among the system addresses is supplied to the decoder circuit DEC, and a chip enable signal CEB is generated. Further, the timing control circuit TC includes an R / W (read / write) signal from the microprocessor CPU,
Receiving a DSB (data strobe) signal and a WAIT (wait) signal, the output enable signal OEB, the write enable signal WEB, and the erase enable signal EEB
Generate. The data terminal of the microprocessor CPU is connected to external input / output terminals I / O0 to I / O7 of the EEPROM via a data bus, and the address terminals of the microprocessor CPU are partially connected to the EEPROM via the address bus. Are connected to the external address terminals AX and AY.

In the microcomputer system of this embodiment, since the EEPROM has the above-mentioned automatic erasing function, the microprocessor CPU has the EEPROM.
The PROM is addressed to generate the signal CEB, and the combination of the signals R / W, DSB and WAIT generates the signals OEB, WEB and EEB designating the erase mode as shown in FIG. Thereafter, the EEPROM enters an automatic erase mode internally as described above. When the EEPROM enters the erasing mode, the address terminal, the data terminal, and all the control terminals become free as described above, and the EEPROM is electrically separated from the microprocessor CPU. Therefore,
The microprocessor CPU only instructs the erasing mode to the EEPROM, and thereafter executes data processing involving the exchange of information with another memory device ROM or RAM, or an input / output port using the system bus. can do.

Thus, the batch erase type EEPROM can be replaced with a full-function (byte-by-byte rewritable) EEPROM without sacrificing the system throughput.
As in the case of the OM, erasing can be performed while being mounted on the system. After giving the instruction of the erasing mode as described above, the microprocessor CPU designates the data polling mode for the EEPROM at an appropriate time interval, and the level of the terminal I / O7 of the data bus becomes low level. It is determined whether the erasing operation has been completed by determining whether the erasing operation is completed. If the erasing is completed and there is data to be written in the EEPROM, the writing is instructed.

The operational effects obtained from the above embodiment are as follows. That is, (1) an EE including a memory array in which electrically erasable nonvolatile storage elements are arranged in a matrix
An erase control circuit that performs at least one read operation on a corresponding memory cell after performing an erase operation on a PROM in accordance with an external erase instruction, and controls continuation and stop of the erase operation based on the read information. Built-in, the EEPROM itself has an erasure confirmation function, that is, the above-described automatic erasure function involving reading, so that an erasing operation can be performed without placing a burden on the microprocessor while the microprocessor is placed in the system. Is obtained.

(2) As the erase control circuit, by adding a pre-write function of performing writing to all memory cells prior to the above-described erase operation, unwritten memory cells become negative by executing the erase operation. Is obtained.

(3) The above-mentioned memory cell is a MOSFET having a two-layer gate structure of a floating gate and a control gate, and information charges accumulated in the floating gate are drawn out to a source, a drain or a well by utilizing a tunnel phenomenon. As a result, the electrical erasure is performed, whereby the area occupied by the memory cell is reduced, and an effect that a large storage capacity can be obtained is obtained.

(4) As for the memory cells constituting the memory array, the source and drain of the entire memory array or a part of the memory cell group are shared, and electrical erasing is performed collectively for each shared memory cell. By performing the operation, the effect of reducing the size of the memory cell as described above can be obtained.

(5) By providing, as the erase control circuit, an address generation circuit for sequentially selecting memory cells, it is possible to carry out the prewrite and erase verification for all memory cells. Is obtained.

(6) At the time of verifying the memory cell for controlling the continuation and stop of the erasure, the word line selection potential transmitted to the control gate is set to about 3 which is lower than the low voltage Vcc and corresponds to the readable lower limit voltage Vccmin. .5V
By setting to such a low voltage Vcv as described above, it is possible to obtain an effect that necessary and sufficient erasing can be guaranteed.

(7) As a power supply circuit for generating the word line selection potential to a relatively low voltage Vcv, it receives a reference voltage formed by a reference voltage generation circuit and outputs a desired output voltage based on a gain setting resistor element. A first operational amplifier circuit for converting the first operational amplifier circuit into a first operational amplifier circuit, and an output terminal of a second operational amplifier circuit of a voltage follower type which receives the output signal of the first operational amplifier circuit and forms an output voltage. Thus, it is possible to obtain an arbitrary set desired voltage with high accuracy without being affected by the variation in the above.

(8) By providing the EEPROM with a data polling function of outputting an internal state such as continuation or stop of an erasing operation to an external device in accordance with an external instruction, the memory management by the microprocessor is simplified. Is obtained.

(9) The above-mentioned EEPROM is mounted on a microcomputer, and an erasing operation is automatically performed by an internal erasing control circuit while electrically disconnected from the microprocessor in accordance with an erasing instruction from the microprocessor. EEP without sacrificing the throughput of the microcomputer system.
The effect is obtained that the erasing of the ROM can be executed in an on-board state.

(10) A memory array in which electrically erasable nonvolatile memory elements selected by one gate signal line (word line) and one drain signal line (data line) are arranged in a matrix. The erase operation is started according to an external erase instruction, and thereafter, the erase operation is automatically performed regardless of the external address signal, input data, and control signal. A semiconductor nonvolatile memory device capable of performing a desired operation by the address signal, the input data, and the control signal is obtained.

(11) A memory array in which electrically erasable nonvolatile memory elements selected by one gate signal line (word line) and one drain signal line (data line) are arranged in a matrix. And starts an erase operation in accordance with an external erase instruction.After that, regardless of an external address signal, input data, and a control signal,
A semiconductor nonvolatile memory device in which a desired operation can be performed by an external address signal, input data, and a control signal after the erasure is automatically performed and the erasure is completed; and a microprocessor having a predetermined information processing function. A system bus connecting the semiconductor non-volatile memory device and a microprocessor, wherein the semiconductor non-volatile memory device is electrically disconnected from the microprocessor in accordance with an erasure instruction from the microprocessor and has internal erase control. An information processing system that performs an erasing operation automatically by the circuit is obtained.

(12) An electrically writable and erasable non-volatile memory composed of rows and columns and arranged in a matrix, wherein a single pulse for a read cycle period or less is input in the erasure. To start erasing, thereafter automatically perform erasing irrespective of the input of external address, data, and control signals. After the erasing is completed, the semiconductor nonvolatile memory accepts external addresses, data, and control signals. A device is obtained.

(13) In an information processing system including an electrically writable and erasable non-volatile memory arranged in a matrix consisting of rows and columns and connected by a microprocessor and a system bus, , The erasing is started by inputting a single pulse less than or equal to the read cycle period, thereafter erasing is performed automatically irrespective of the address, data and control signals from the system bus. , An information processing system including a semiconductor nonvolatile memory device for receiving a signal from the semiconductor memory device is obtained.

(14) Among the memory cells, the memory cell having the lowest threshold voltage is prevented from having a negative threshold voltage by the erasing operation, and has the highest threshold voltage. The effect is obtained that the erasing operation of the EEPROM is automatically controlled by the internal erasing control circuit so that the memory cell has a threshold voltage that can be read at the lower limit voltage Vccmin by the erasing operation.

The invention made by the inventor has been specifically described based on the embodiments. However, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example,
The signal FAIL or ER in FIG. 4 may have a function of outputting to the outside. In this case, in order to prevent an increase in the number of external terminals, it is desirable to output using the data polling function. For example, data input / output terminals I / O5 and I / O5
/ O6 may be the same circuit as the data output circuit corresponding to the data input / output terminal I / O7 in FIG. 11, and the gates to which the signal ES is supplied may correspond to the signals FAIL and ER. Thus, a signal indicating another internal operation sequence may be output to the outside as needed.

The erasing of the memory array M-ARY may be such that a source line and a word line are respectively divided, and a memory block to be erased is specified by a combination thereof. As a storage transistor constituting a memory cell, a stacked gate structure M used in an EPROM is used.
In addition to the OS transistor, a write operation may use a FLOTOX storage transistor using a tunnel phenomenon.

In the above embodiment, 1 shown in FIG.
Although one storage transistor is used as one memory cell, one storage transistor shown in FIG. 18 (in this case, substantially two transistors are regarded as one storage transistor) is replaced with one storage transistor. It may be used as a memory cell. That is, according to the present invention, EEPRO using one storage transistor shown in FIG.
Particularly suitable for M. However, the present invention can also be applied to an EEPROM having a memory cell as shown in FIG. 19B (one memory cell is formed of two transistors and defined by two word lines and one data line). .

The high voltage Vpp for writing / erasing is not limited to a high voltage supplied from the outside. That is, if the current flowing during writing / erasing is small,
A configuration may be used in which the voltage of the power supply voltage Vcc is boosted by a known charge pump circuit or the like inside the EEPROM. Further, the internal step-up power supply and the external high voltage Vpp may be used in combination.

The configuration of the circuit portion (CNTR) for controlling the normal writing / reading and the like and the circuit portion (LOGC) for controlling the erasing algorithm in the EEPROM are not limited as long as they perform the above-described operation sequence. Such a circuit may be used. 3 and 4,
In addition to a random logic circuit as shown in FIGS. 6 and 7, a programmable logic array (PLA), a microcomputer and software incorporated, or an asynchronous circuit in the above embodiment, a synchronous circuit may be used. As described above, the circuit for realizing the above operation sequence can adopt various embodiments.

The specific circuit configuration of the memory array constituting the EEPROM and its peripheral circuits can employ various embodiments. Furthermore, EEPROMs and the like
It may be built in a digital semiconductor integrated circuit device such as a microcomputer.

In the above description, a pair of regions of the storage transistor is defined as a source region and a drain region for the sake of simplicity, but the source and drain are determined by the value of the applied voltage. In a transistor, the present invention can be applied by replacing the above-described source region and drain region with one region (node) and the other region (node).

The present invention relates to a storage transistor having a stacked gate structure as used in an EPROM,
The present invention can be widely used for a semiconductor nonvolatile memory device using a TOX type storage transistor and an information processing system using the same.

[0170]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, after an erasing operation is performed in accordance with an external erasing operation instruction, a corresponding memory cell is stored at least once in an EEPROM including a memory array in which electrically erasable nonvolatile storage elements are arranged in a matrix. And a built-in erase control circuit for controlling the continuation and stop of the erase operation based on the read information. When such an EEPROM is mounted on an information processing system including a microprocessor, the In accordance with the instruction (1), the erasing operation is automatically performed by the internal erasing control circuit while being separated from the microprocessor. In this configuration, since the EEPROM itself has an automatic erasing function accompanied by reading of erasure confirmation, in the erasing operation with the EEPROM mounted in the system, the control from the microprocessor only instructs the erasing start. Time
The burden on the microprocessor is not significantly reduced and the throughput of the system is not sacrificed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a memory array unit and a block diagram of a peripheral circuit showing an embodiment of an EEPROM to which the present invention is applied.

FIG. 2 is a flowchart illustrating an example of an erasing algorithm according to the present invention.

FIG. 3 is a partial circuit diagram of a specific example of an erase control circuit LOGC;

FIG. 4 is another partial circuit diagram of a specific example of the erase control circuit LOGC;

FIG. 5 is a timing chart for explaining an erasing operation.

FIG. 6 is a partial circuit diagram of a specific example of a timing control circuit CNTR.

FIG. 7 is another partial circuit diagram of a specific example of the timing control circuit CNTR.

FIG. 8 is a characteristic diagram showing a relationship between an erasing time and a threshold voltage of a storage transistor.

FIG. 9 is a circuit diagram showing one embodiment of a unit circuit of the address buffers XADB and YADB.

FIG. 10 is a circuit diagram showing one embodiment of an erase circuit ERC.

FIG. 11 is a circuit diagram showing one embodiment of a data output buffer DOB.

FIG. 12 is a circuit diagram showing one embodiment of a power supply circuit for generating an erase verify voltage Vcv.

FIG. 13 is a circuit diagram of a memory array section showing another embodiment of the EEPROM.

FIG. 14 is a block diagram showing an embodiment of a microcomputer system using the EEPROM.

FIG. 15 shows the EEPROM and the microprocessor CP.
FIG. 4 is a block diagram illustrating connection of an embodiment with U.

FIG. 16 is a structural cross-sectional view for explaining an example of a conventional memory cell.

FIG. 17 is a schematic circuit diagram for explaining the read operation.

FIG. 18 is a structural cross-sectional view for explaining another example of a conventional memory cell.

FIG. 19 is a circuit diagram of a memory cell (A) and a conventional memory cell (B) in an EEPROM to which the present invention is applied.

FIG. 20 is an overall block diagram of an EEPROM according to an embodiment of the present invention.

FIG. 21 is a waveform diagram showing an example of an external signal of an EEPROM to which the present invention is applied.

FIG. 22 is a circuit diagram showing one embodiment of a data input buffer.

FIG. 23 is a circuit diagram showing one embodiment of an address decoder.

FIG. 24 shows erase enable signals (A), (B),
FIG. 3C is a waveform diagram showing (C) and read cycles (D) and (E).

[Explanation of symbols]

XADB, YADB ... address buffer, XDCR, Y
DCR: address decoder, UDG: unit decoder circuit, M-ARY: memory array, SA: sense amplifier,
DIB, DIB-0 to DIB-7 data input buffer, DOB, DOB-0 to DOB-7 data output buffer, CNTR timing control circuit, ERC erase circuit, LOGC erase control circuit (internal circuit), N1 , N2
... CMOS inverter circuit, CS ... source line, W1, W
2 Word line, D1 to Dn Data line, CD Common data line, O1, O2 Oscillator circuit, BCS1 to BCS4 2
Hex counter circuit, DP: Data polling control circuit, C
PU: microprocessor, ROM: read-only memory, RAM: random access memory, I /
OPORT: I / O port, EEPROM (FLAS
H)... Batch erase type semiconductor nonvolatile storage device, RGU.
2V power supply, LCD: liquid crystal display, CRT: cathode ray tube, ADDRESS: address bus, DATA: data bus, DEC: decoder circuit, TC: timing control circuit, 3: drain, 4: floating gate, 5:
Source, 6: Control gate, 7: Thin oxide film, 8
... P-type silicon substrate, 9 ... N-type diffusion layer, 10 ... Low-concentration N-type diffusion layer, 11 ... P-type diffusion layer, 12 ... Selected memory cell, 14 ... Unselected memory cell, 13 ... Selected word line, 1
5: unselected word line, 16: data line, 17: sense amplifier.

Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical display location H01L 29/792 (72) Inventor Masashi Mutoh 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi, Ltd. Inside the Musashi Factory (72) Inventor Yasuo Kubota 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-LSE Engineering Co., Ltd. (72) Inventor Kazuyoshi Shoji Waterworks in Kodaira-shi, Tokyo 5-20-1, Honmachi Inside Hitachi Super LSI Engineering Co., Ltd. (56) References JP-A-59-71195 (JP, A) Patent 2654596 (JP, B2)

Claims (14)

(57) [Claims] 1. An information processing system comprising: an address bus, a data bus, a microprocessor connected to the address bus and the data bus, for supplying an address signal to the address bus, and a microprocessor connected to the address bus and the data bus. The nonvolatile storage device includes a plurality of word lines, a control gate, a floating gate,
And a pair of semiconductor regions, the control gate is connected to each of the plurality of word lines, information is stored as a threshold voltage value, and a predetermined voltage is applied to the control gate by an erasing operation. A plurality of storage MOSFETs whose threshold voltages change in a direction from the first range to the second range; an address signal for designating a word line from the plurality of word lines; An address terminal received from the outside of the storage device; an address generating circuit for sequentially generating a verify address designating a word line from the plurality of word lines; and a word designated by the verify address generated by the address generating circuit. The threshold voltage of the storage MOSFET connected to the line is changed to the second range by the erase operation. Detecting the whether in running verify operation, in the verify operation, the memory MO
When it is detected that the threshold voltage of the SFET is not within the second range, the erase operation is performed, and in the verify operation, the threshold voltage of the storage MOSFET falls within the second range. An information processing system comprising: a control circuit for generating a different verify address from the address generation circuit when one is detected; 2. The information processing system according to claim 1, wherein said address generation circuit in said nonvolatile storage device is a counter circuit. 3. The information processing system according to claim 1, wherein said non-volatile storage device executes said erase operation and verify operation in response to a combination of external signals from said microprocessor. Processing system. 4. The information processing system according to claim 3, further comprising a peripheral device connected to the address bus and the data bus, wherein the address bus and the data bus are connected when the erase operation and the verify operation are being performed. , Wherein the system is released from the nonvolatile storage device. 5. The information processing system according to claim 2, wherein said non-volatile storage device further comprises: a first combination of an external signal from said microprocessor when said verify operation is being executed; An information processing system comprising an output circuit for outputting predetermined information relating to a result of the verify operation. 6. The information processing system according to claim 5, wherein the control circuit in the nonvolatile storage device executes the erase operation and the verify operation in response to a second combination of external signals from the microprocessor. An information processing system, comprising: 7. The information processing system according to claim 5, wherein the nonvolatile storage device is connected to the data bus,
Storage MOSFET specified by the address signal
An information processing system, comprising: a data terminal for transmitting data read out of the nonvolatile storage device to the outside of the nonvolatile storage device; and the predetermined information is output via the data terminal. 8. The information processing system according to claim 7, further comprising a peripheral device connected to the address bus and the data bus, wherein the address bus and the data bus are connected when the erase operation and the verify operation are being performed. And an information processing system released from the nonvolatile storage device. 9. The information processing system according to claim 8, wherein the pair of semiconductor regions is a source region and a drain region, and the storage MOSFET is configured to store electrons stored in its floating gate by the erasing operation. An information processing system, which is moved to a drain region. 10. The information processing system according to claim 9, wherein said predetermined information output from said nonvolatile storage device is supplied to said microprocessor. 11. The information processing system according to claim 2, wherein the storage MOSFET whose threshold voltage has changed to be within the second range is the first MOSFET in the verify operation.
Wherein the storage MOSFET whose threshold voltage is within the first range shows the second state in the verify operation. 12. The information processing system according to claim 11, wherein, in the verify operation, a storage MO connected to a word line specified by the verify address.
The SFET is set to a selected state, the first state is a conductive state of the selected storage MOSFET, and the second state is a non-conductive state of the selected storage MOSFET. An information processing system characterized by the following. 13. The information processing system according to claim 12, wherein said storage MOSFET is an N-channel MOSFET.
T, wherein the second range does not include a negative threshold voltage. 14. The information processing system according to claim 12, wherein said storage MOSFET is an N-channel MOSFET.
T, and the first state is a depletion type MOS
An information processing system, which does not include a conduction state of a storage MOSFET changed to an FET.