JP2004303420A - Device having nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a device having a nonvolatile memory improved in operability. <P>SOLUTION: The device is provided with a bus and a plurality of memories one of which is a nonvolatile memory, a processor and input output terminals. All of them are connected to the bus. The nonvolatile memory receives a plurality of control signals from the processor, executes erase and erase verify operations for the memory cells that are internally specified and automatically conducts erase operations when the erasing is insufficient. Having transmitted erasing signals to the nonvolatile memory, the processor conducts discrimination to determine whether the erasing mode is completed or not based on the information outputted to the bus from the nonvolatile memory. During the period, i.e., after the erase signals are transmitted to the nonvolatile memory and till the erasing mode is completed at the nonvolatile memory, accesses are made to the memories in order to input data from the external through the input output terminals. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a device having a non-volatile memory, and more particularly to a technology effective when used in a device having a batch erase EEPROM (electrically erasable & programmable read only memory).

  As semiconductor nonvolatile storage devices, there are an EPROM (erasable & programmable read only memory) capable of erasing stored information by ultraviolet rays and an EEPROM capable of electrically erasing stored information. EPROM is suitable for increasing the storage capacity because the area of the memory cell for storing information is relatively small, but it is necessary to irradiate the memory cell with ultraviolet rays in order to erase the stored information. Yes, and are therefore sealed in relatively expensive windowed packages. Further, in order to write or rewrite information by a programmer, there is a problem that it is necessary to remove the EPROM from a system in which the EPROM is mounted when writing or rewriting new information.

  On the other hand, an EEPROM can electrically rewrite stored information in a state where the EEPROM is mounted on a system. However, in an EEPROM, the area of a memory cell constituting the EEPROM is relatively large, for example, about 2.5 to 5 times as large as the EPROM. Therefore, it is difficult to say that the EEPROM is suitable for increasing the storage capacity. Therefore, recently, a so-called electrically erasable EEPROM has been developed as a semiconductor nonvolatile memory device intermediate between the two. The electric batch erasing type EEPROM has a function of collectively erasing all memory cells formed on a chip or a group of memory cells among memory cells formed on a chip. Is a semiconductor nonvolatile memory device having In the electrically erasable EEPROM, the size of the memory cells can be reduced to that of an EPROM.

  Regarding such a batch erase type EEPROM, see pages 152 to 153 of the IEEE International Solid-State Circuits Conference (IEE, 1980), and EE (IEEE International Solid State Circuits Conference), 1987. IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, pages 76-77, IEE Journal of Solid State Circuits, Vol. 23, No. 5, 1988. Pages 1157 to 1163 (IEEE, J. Solid-State Cicuits, vol. 23 (1988) pp. 1157-1163).

  FIG. 16 is a schematic diagram showing a cross-sectional structure of a memory cell of an electrically erasable EEPROM which was announced at the International Electron Device Meeting in 1987. The memory cell shown in the figure has a structure very similar to that of a normal EPROM. That is, the memory cell is configured by an insulated gate field effect transistor (hereinafter referred to as a MOSFET or simply a transistor) having a two-layer gate structure. In the figure, 8 is a P-type silicon substrate, 11 is a P-type diffusion layer formed on the silicon substrate 8, 10 is a low-concentration N-type diffusion layer formed on the silicon substrate 8, and 9 is the P-type diffusion layer. N-type diffusion layers formed on each of the layer 11 and the N-type diffusion layer 10. 4 is a floating gate formed on the P-type silicon substrate 8 via a thin oxide film 7; 6 is a control gate formed on the floating gate 4 via an oxide film 7; 3 is a drain electrode; 5 is a source electrode. That is, the memory cell shown in the figure is constituted by an N-channel type MOSFET having a two-layer gate structure, and information is stored in this transistor. Here, the information is substantially held in the transistor as a change in the threshold voltage.

  Hereinafter, a case where a transistor for storing information (hereinafter, referred to as a storage transistor) in a memory cell is an N-channel type, unless otherwise specified. The operation of writing information into the memory cells shown in FIG. 16 is similar to that of the EPROM. That is, the write operation is performed by injecting hot carriers generated near the drain region 9 connected to the drain electrode 3 into the floating gate 4. Due to this write operation, the threshold voltage of the storage transistor as viewed from the control gate 6 becomes higher than that of the storage transistor which has not performed the write operation.

  On the other hand, in the erasing operation, when the control gate 6 is grounded and a high voltage is applied to the source electrode 5, a high electric field is generated between the floating gate 4 and the source region 9 connected to the source electrode 5, and a thin electric field is generated. Electrons accumulated in the floating gate 4 are drawn out to the source electrode 5 through the source region 9 by utilizing a tunnel phenomenon through the oxide film 7. Thereby, the stored information is erased. That is, the threshold voltage of the storage transistor as viewed from its control gate 6 is lowered by the erase operation. In the read operation, the voltage applied to the drain electrode 3 and the control gate 6 is set so that weak writing to the memory cell, that is, undesired carrier injection into the floating gate 4 is not performed. Limited to relatively low values. For example, a low voltage of about 1 V is applied to the drain electrode 3 and a low voltage of about 5 V is applied to the control gate 6. By detecting the magnitude of the channel current flowing through the storage transistor based on these applied voltages, “0” and “1” of the information stored in the memory cell are determined.

  In general, in electrical erasing, when erasing is continued for a long time, the threshold voltage of the storage transistor may be a negative value, unlike the threshold voltage of the storage transistor in a thermal equilibrium state. On the other hand, when erasing stored information with ultraviolet rays as in an EPROM, the threshold voltage of the storage transistor, which is changed by the erasing operation, is settled to the threshold voltage when the storage device was manufactured. The threshold voltage of the storage transistor after the erasing operation can be controlled by manufacturing conditions or the like when manufacturing the storage device. However, when the stored information is electrically erased, the stored information is erased by extracting the electrons accumulated in the floating gate to the source electrode. During the operation, more electrons are extracted than the amount of electrons injected into the floating gate. Therefore, when the electrical erasing is continued for a relatively long time, the threshold voltage of the storage transistor becomes a value different from the threshold voltage when manufactured. In other words, when the erasing operation is performed, the threshold voltage is not settled according to the manufacturing conditions at the time of manufacturing, in contrast to the EPROM. The present inventors measured a change in threshold voltage of a storage transistor due to electrical erasure.

  FIG. 8 shows the relationship between the erasing time and the threshold voltage of the storage transistor that changes by erasing, obtained by this measurement. In the figure, the horizontal axis represents the erase time, the vertical axis represents the threshold voltage of the storage transistor, Vo is substantially zero threshold voltage, + Vths is the positive threshold voltage, -Vths indicates that the threshold voltage is a negative voltage. Vthv indicates a variation in the threshold voltage after erasing due to a variation in manufacturing conditions and the like. From this figure, it will be understood that the threshold voltage changes to a negative voltage when erasing is continued for a relatively long time.

  It will also be understood that the threshold voltage obtained by the erasing operation may vary from storage transistor to storage transistor due to variations in manufacturing conditions and the like. It can be further understood from the figure that the variation of the threshold voltage increases with the erasing time. That is, as the erase time becomes longer, the difference between the threshold voltages of the two storage transistors becomes larger. As described above, when the threshold voltage of the storage transistor becomes negative, the read operation is adversely affected.

  This will be described with reference to FIG. Now, consider a case where stored information is read from the written memory cell 12. Reference numeral 17 in the figure denotes a sense amplifier. In order to bring the memory cell 12 into a selected state, a selection voltage at the time of a read operation, for example, a power supply voltage Vcc (5 V) is applied to the word line 13 to which the memory cell 12 is coupled, and these are applied to other memory cells 14 and the like. In order to set the non-selected state, the word line 15 and the like are set to a non-selected voltage at the time of a read operation, for example, the circuit ground potential 0V. If the threshold value of the non-selected memory cell 14 connected to the data line 16 corresponding to the memory cell 12 from which stored information is to be read is negative, the voltage of the word line 15, that is, Even if the voltage of the control gate of the memory cell is set to 0 V, an undesired current (non-selection leak current) flows through the data line 16 through the memory cell 14 in the non-selected state. As a result, erroneous reading is caused.

  Also, during a write operation, there is an adverse effect if the threshold voltage of the storage transistor in the memory cell is negative. Normally, in a writing operation using hot carriers, a high voltage for writing (Vpp) externally applied is applied to the drain region of a storage transistor in a memory cell via a MOSFET. The voltage drop across the MOSFET depends on the current flowing through it. Therefore, under the condition that the threshold voltage of the storage transistor becomes a negative value as described above, the voltage drop in the MOSFET becomes too large and the voltage applied to the drain of the storage transistor in the memory cell becomes , The voltage drop. As a result, the time required for writing increases. Therefore, in the above-described EEPROM, the value of the threshold voltage after erasing must be accurately controlled.

  In order to realize electrical erasure of stored information, a conventional EEPROM, for example, an EEPROM described in IEE, International, Solid-State Circuits Conference, p. Each of the cells was composed of a storage transistor and a selection transistor connected in series with the storage transistor to prevent non-selective leakage current. In this EEPROM, a program line is connected to the control gate of the storage transistor, and a select line is connected to the gate of the select transistor. That is, the storage transistor and the selection transistor are coupled to different word lines.

  FIG. 18 is a cross-sectional view of a memory cell of an electrically erasable EEPROM described on pages 76 to 77 of the EE, International, Solid-State Circuits Conference of 1987. Have been. The operation of this memory cell is almost the same as that of the memory cell shown in FIG. 16, except that the storage information is erased differently from the memory cell of FIG. This is done using phenomena. Although this memory cell has only one gate electrode to be connected to the word line, it can be considered that the memory cell is substantially composed of two transistors. That is, it can be considered that a memory cell is constituted by a selection transistor and a storage transistor in which a gate electrode and a control gate electrode are integrated.

  Since this memory cell substantially has the selection transistor as described above, it solves the problem of non-selective leakage current at the time of reading. However, the write operation is performed by hot carriers that require a larger amount of current than when the tunnel phenomenon is used, so that the above-described adverse effect in the write operation is not improved.

  In EEPROMs, such as those disclosed in the aforementioned IEE, International, Solid State Circuits Conference, 1980, pp. 152-153, the storage transistors connected to different word lines are selected. One memory cell is formed by the transistor. On the other hand, in the memory cell of the electrical batch erasing type EEPROM shown in FIGS. 16 and 18, one memory transistor is connected to one word line.

  This becomes clearer when the memory cells and the like shown in FIGS. 16 and 18 are represented by circuit diagrams. Thus, FIGS. 19A and 19B are circuit diagrams of the above-described memory cells. FIG. 19 (B) shows a circuit diagram of a memory cell announced at the above-mentioned IEE, International, Solid-State Circuits Conference in 1980. In the figure, W1 and W2 indicate different word lines, and D indicates a data line. Further, Qs indicates a selection transistor, and Qm indicates a storage transistor.

  FIG. 19A shows a circuit diagram of the memory cell shown in FIGS. 16 and 18. As can be understood from the drawing, one memory cell has its control gate connected to one word line, its drain connected to one data line D, and its source connected to one source line S. It is constituted by one connected storage transistor Qm. In order to select a desired memory cell from a plurality of memory cells in a read operation and a write operation, in FIG. 19A, one word line and one data line are selected. , One memory cell connected to the selected word line W and connected to the selected data line D can be selected. In other words, one memory cell can be defined by one word line and one data line. Note that in FIG. 19A, the source line S is common to the source lines S of all the other storage transistors formed on the chip, or between the predetermined number of memory cells forming one memory block. S is made common.

  Since the memory cell illustrated in FIG. 19A can be formed using one storage transistor, the area on a chip required to form a memory cell can be reduced to be as small as that of an EPROM. However, it is indispensable to be able to control the threshold voltage of the storage transistor after erasing in order to realize electrical batch erasure of stored information.

To do this, it is necessary to repeat the operation of performing erasing in several times, reading each time erasing is performed, checking whether erasing is sufficient, and erasing again if not enough. The above-mentioned IEE Journal of Solid State Circuits, Vol. 23, No. 5, (1988), pp. 1157 to 1163, describes an algorithm for controlling the threshold voltage after such erasure. Proposed. In the above document, it is described that this algorithm is executed by an external microprocessor provided separately from the electrically erasable EEPROM. In addition, in order to secure the lower limit voltage Vccmin of the operable power supply voltage at the time of normal reading, it is described that a verify voltage is generated in the EEPROM chip at the time of reading (erasing verify) in the above algorithm. .
IEE, 1980, IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE, pages 152-153 1987 IEEE International Solid State Circuits, pages 76-77, EE, International, Solid-State Circuits Conference 1988 IEE Journal of Solid State Circuits (IEEE, J. Solid-State Cicuits, vol.23 (1988)), Vol. 23, No. 5, pp. 1157-1163

  In the above-described prior art, since the above-described algorithm is executed by the microprocessor, it is troublesome to execute the erasing operation while the electrical batch erasing type EEPROM is mounted on the system. Further, since a relatively long time is required for erasing the stored information, the microprocessor is occupied by the erasing operation of the EEPROM for a relatively long time, which substantially stops the system. Have a problem.

  An object of the present invention is to provide an apparatus having a nonvolatile memory with improved usability. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  The outline of a representative one of the inventions disclosed in the present application will be briefly described as follows. That is, it has a bus, a plurality of memories, a processor, and an input / output terminal connected to the bus, one of the memories is a nonvolatile memory, receives a plurality of control signals from the processor, and An erase control circuit for repeatedly performing an erase operation and an erase verify operation automatically until the erasure of a plurality of memory cells is completed, an address generation circuit for sequentially generating an address signal, A circuit that outputs information, and when receiving an erasure signal included in the control signal from the processor, the nonvolatile memory starts the erasure mode, and the erasure control circuit sends a plurality of memory cells to be erased. After performing the erase operation, the erase verify operation is performed on the memory cell designated by the address generation circuit. When the erasing is insufficient, the erasing operation is performed again, and the processor sends an erasing signal to the nonvolatile memory, and then, based on the information output from the circuit to the bus, sets the erasing mode to the erasing mode. It is determined whether or not the erasing mode has been completed, and after the erasing signal is sent to the nonvolatile memory and before the erasing mode in the nonvolatile memory ends, the other memory can be accessed. Data can be input from the outside via the output terminal.

  The load on the microprocessor is not significantly reduced and the throughput of the device is not sacrificed.

  FIG. 20 is a block diagram of an electrically erasable EEPROM (hereinafter also referred to as a flash EEPROM) to which the present invention is applied. Each circuit block shown in FIG. 1 is not particularly limited, but is formed on one semiconductor substrate by a well-known semiconductor integrated circuit technology. Further, in the same figure, a mark “○” indicates an external terminal provided in the flash EEPROM.

  In the present application, in the drawings, the notation of logical symbols follows a general notation in order to facilitate understanding of the invention. For example, a signal in which the low level becomes the active level is overwritten with an alphabet indicating the control signal, but in the specification, a signal corresponding to the signal is represented by ending with B (meaning a bar). For example, the chip enable signal is represented as CEB.

  In FIG. 1, each of M-ARY-0 to M-ARY-7 is a memory array having the same configuration as each other, and is not particularly limited. And a memory cell provided at each intersection of a word line and a data line.

  XADB is a row address buffer which receives an external row address signal AX supplied via an external terminal and forms an internal complementary row address signal corresponding to the row address signal AX. XDCR is a row address decoder that receives an internal complementary row address signal formed by the row address buffer XADB and decodes the internal row address signal. Although not particularly limited, in this embodiment, the row address buffer XADB and the row address decoder XDCR are common to the memory arrays M-ARY-0 to M-ARY-7. That is, the row address decoder XDCR decodes the internal complementary row address signal, and instructs the external row address signal AX from a plurality of word lines in each of the memory arrays M-ARY-0 to M-ARY-7. A word line selection signal for selecting one of the selected word lines is formed. As a result, one word line is selected from each of the memory arrays M-ARY-0 to M-ARY-7.

  In the figure, YADB is a column address buffer which receives an external column address signal AY supplied via an external terminal and forms an internal complementary column address signal according to the external column address signal AY. YDCR is a column address decoder that decodes the internal complementary column address signal formed by the column address buffer YADB and forms a data line selection signal according to the external column address signal AY. Although not shown in the figure, each of the memory arrays M-ARY-0 to M-ARY-7 receives the data line selection signal and receives the external column of the plurality of data lines in the memory array. A column switch is provided for coupling one data line designated by the address signal AY to a common data line (not shown) corresponding to the memory array.

  In this manner, in each of the memory arrays M-ARY-0 to M-ARY-7, one word line and one data line are selected according to the external row address signal AX and the external column address signal AY. Then, the memory cell provided at the intersection of the selected word line and data line is selected. That is, a memory cell coupled to the selected word line and data line is selected from a plurality of memory cells in all memory arrays. As a result, one memory cell is selected from each memory array.

  Although not particularly limited, in the present embodiment, a write operation or a read operation is performed almost simultaneously on the memory cells selected from the respective memory arrays. That is, the writing or reading operation of information is performed in units of 8 bits. For this purpose, the EEPROM of this embodiment is provided with eight external input / output terminals I / O0 to I / O7, and the memory arrays M-ARY-0 to M-ARY-7 and the corresponding external A data input buffer DIB, a data output buffer DOB, a sense amplifier SA, and MOSFETs Q18 and Q16 for switches are provided between the input / output terminals I / O0 to I / O7.

  Taking the memory array M-ARY-0 as an example, in the case of a write operation, the selected memory cell is connected to the output node of the data input buffer DIB-0 via the MOSFET Q18 turned on by the write control signal wr. In the case of a read operation, it is coupled to the input node of the sense amplifier SA-0 via the MOSFET Q16 turned on by the read control signal re. The external input / output terminal I / O0 is coupled to the input node of the data input buffer DIB-0 and the output node of the sense amplifier SA-0 via the data output buffer DOB-0. The remaining memory arrays M-ARY-1 to M-ARY-7 are also connected to the external input / output terminals I / O1 to I / O7 in the same manner as the memory array M-ARY-0.

  In the figure, LOGC is an internal circuit for performing an automatic erase control operation, and will be described later in detail. CNTR is a timing control circuit, which responds to an external signal or voltage supplied to the external terminals CEB, OEB, WEB, EEB, and Vpp, and a signal from the internal circuit LOGC to control the above-mentioned control signals wr, re. And the like. In the figure, Vcc is an external terminal for supplying a power supply voltage Vcc to each timing block, and Vss is an external terminal for supplying a circuit ground potential Vss to each circuit block. In the above description, the word line is divided for each memory array, but the word line may be shared for each memory array.

  FIG. 1 shows one memory array M-ARY in the flash EEPROM shown in FIG. 20, its peripheral circuits, a row address buffer, a column address buffer, a row address decoder, a column address decoder, a timing control circuit CNTR, and an internal circuit. A detailed block diagram of the circuit LOGC is shown. As can be easily understood from the above description, each circuit element shown in FIG. 1 is not particularly limited, but is formed of one single-crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. It is formed on such a semiconductor substrate. In the figure, a P-channel MOSFET is distinguished from an N-channel MOSFET by adding an arrow to its channel (back gate) portion. This is the same in other drawings.

  Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single-crystal P-type silicon. The N-channel MOSFET includes a source region, a drain region formed on the surface of the semiconductor substrate, and a polysilicon layer formed on the surface of the semiconductor substrate between the source region and the drain region via a thin gate insulating film. It is composed of such a gate electrode. The P-channel MOSFET is formed in an N-type well region formed on the surface of the semiconductor substrate. Thus, the semiconductor substrate forms a common substrate gate of the plurality of N-channel MOSFETs formed thereon, and is supplied with the circuit ground potential Vss. The N-type well region forms a substrate gate of a P-channel MOSFET formed thereon. The power supply voltage Vcc is supplied to the substrate gate of the P-channel MOSFET, that is, the N-type well region. However, the N-type well region where the P-channel MOSFET is formed, which constitutes a circuit for processing a high voltage higher than the power supply voltage Vcc, is not particularly limited, but a high voltage externally applied through the external terminal Vpp is used. Vpp or a high voltage generated inside the EEPROM is supplied.

  Alternatively, the integrated circuit may be formed over a semiconductor substrate made of single-crystal N-type silicon. In this case, the N-channel MOSFET and the nonvolatile memory element are formed in a P-type well region, and the P-channel MOSFET is formed on an N-type semiconductor substrate.

  Hereinafter, the flash EEPROM of this embodiment will be described in more detail with reference to FIG. 1. However, in order to facilitate understanding, the following description may overlap the description of FIG. 20 described above.

  Although not particularly limited, in the flash EEPROM of this embodiment, an internal complementary address signal is generated by address buffers XADB and YADB which receive X (row) and Y (column) address signals AX and AY externally supplied through external terminals. And is supplied to the address decoders XDCR and YDCR. Although not particularly limited, the address buffers XADB and YADB are activated by the internal chip select signal ceB, take in the external address signals AX and AY supplied from the external terminals, and have the same internal phase as the external address signals supplied from the external terminals. A complementary address signal consisting of the address signal and the internal address signal having the opposite phase is formed. The address buffers XADB and YADB are supplied with a signal ES indicating an erase mode, internal address signals AXI and AYI, in addition to the above-described chip selection signal ceB. However, these signals ES, AXI, YAI, etc. are used in an erasing mode described later, and do not affect the operation of the address buffers AXDB, YADB in a normal writing or reading mode.

  The row (X) address decoder XDCR is activated by an address decoder activation signal DE, and converts one word line according to a complementary address signal from the corresponding address buffer XADB into a plurality of word lines in the memory array M-ARY. , A selection signal for selecting a signal is formed.

  The column (Y) address decoder YDCR is also activated by the address decoder activation signal DE, and connects one data line according to the complementary address signal from the corresponding address buffer YADB to a plurality of data in the memory array M-ARY. Form a select signal to select from the lines.

  The memory array M-ARY includes a plurality of word lines, a plurality of data lines arranged to intersect the word lines, and a plurality of memory cells provided at each intersection of the word lines and the data lines. Have. FIG. 3 exemplarily shows a part of the memory array M-ARY as a representative. That is, in FIG. 1, the word lines W1, W2 of the plurality of word lines, the data lines D1, D2, Dn of the plurality of data lines, and the intersections of the data lines and the word lines are provided. The illustrated memory cells are exemplarily shown. As described with reference to FIG. 19A, each of the memory cells is configured by one storage transistor (nonvolatile storage element). That is, each of the memory cells is constituted by one storage transistor having a stacked gate structure having a control gate and a floating gate. The memory cell exemplarily shown in FIG. 1 includes storage transistors (non-volatile storage elements) Q1 to Q6. As described above, the storage transistor is not particularly limited, but has a structure similar to that of the EPROM storage transistor. However, the point that the erasing operation is electrically performed by utilizing the tunnel phenomenon between the floating gate and the source region coupled to the source line CS as described above or later will be described below. This is different from the method of erasing the EPROM.

  In the memory array M-ARY, the control gates (memory cell selection nodes) of the storage transistors Q1 to Q3 (Q4 to Q6) arranged in the same row are connected to corresponding word lines W1 (W2), respectively. The drain regions (input / output nodes of the memory cells) of the storage transistors Q1, Q4 to Q3, Q6 arranged in a column are connected to the corresponding data lines D1 to Dn, respectively. The source region of the storage transistor is coupled to a source line CS.

  In this embodiment, although not particularly limited, an N-channel MOSFET Q10 and a P-channel MOSFET Q17, which are switch-controlled by the erase circuit ERC, are connected to the source line CS. The erase circuit ERC turns on the N-channel MOSFET Q10 in the write mode and the read mode so that the source line CS is supplied with the circuit ground potential Vss. On the other hand, in the erase mode, the P-channel MOSFET Q17 is turned on so that the high voltage Vpp for erasing is applied to the source line CS.

  If it is desired to enable partial erasure of the memory array M-ARY, storage transistors arranged in a matrix are vertically divided into M blocks, and a source line corresponding to the source line is provided for each block. It is provided for each. As described above, each of the source lines CS provided in each block is provided with the above-described erase circuit ERC and MOSFETs Q10 and Q17. In this case, it is necessary to specify each erase circuit by an address signal in order to determine which of the plurality of blocks is to be erased. In the above-described embodiment, the storage information of all the memory cells constituting the memory array M-ARY is collectively erased. In this case, the number of source lines CS is one, and the erase circuit ERC and MOSFETs Q10 and Q17 are provided correspondingly.

  In the EEPROM of this embodiment, although there is no particular limitation, since writing / reading is performed in units of a plurality of bits such as 8 bits, the memory array M-ARY has a total of 8 bits as shown in FIG. A plurality of pairs are provided as pairs (M-ARY-0 to M-ARY-7). When writing or reading information in units of 16 bits, for example, 16 sets of the memory array M-ARY are provided.

  Each of the data lines D1 to Dn constituting the one memory array M-ARY is selected via column (column) selection switches MOSFET Q7 to Q9 (column switches) which receive a selection signal formed by the column address decoder YDCR. Connected to the common data line CD. To the common data line CD, the output terminal of a write data input buffer DIB that receives write data input from the external terminal I / O is connected via a switch MOSFET Q18. Similarly, the other seven memory arrays M-ARY are provided with the same column selection switch MOSFET as described above with reference to FIG. 20, and supplied with the selection signal from the column address decoder YDCR. Is done. A different column address decoder may be provided for each memory array, and the column selection switch MOSFET may be switch-controlled by a selection signal from the corresponding column address decoder.

  The common data line CD provided corresponding to the memory array M-ARY is coupled via a switch MOSFET Q16 to an input terminal of a first stage amplifier circuit constituting an input stage circuit of the sense amplifier SA. For convenience, a circuit constituted by the MOSFETs Q11 to Q15 constituting the first-stage amplifier circuit and the CMOS inverter circuits N1 and N2 in the cascade is referred to as a sense amplifier SA. The sense amplifier SA is supplied with a relatively low power supply voltage Vcc as a power supply of the sense amplifier SA during normal reading to the power supply voltage terminal Vcc / Vcv, and has a potential lower than the power supply voltage Vcc during erase verify described later. The power supply voltage terminal Vcc / Vcv is supplied with the voltage Vcv as a power supply.

  The common data line CD exemplified above is connected to the source of an N-channel type amplifying MOSFET Q11 through a MOSFET Q16 turned on by a read control signal re. Between the drain of the amplifying MOSFET Q11 and the power supply voltage terminal Vcc / Vcv of the sense amplifier SA, there is provided a P-channel load MOSFET Q12 having a gate to which the ground potential Vss of the circuit is applied. The load MOSFET Q12 performs an operation of flowing a precharge current to the common data line CD for a read operation.

  In order to increase the sensitivity of the amplifying MOSFET Q11, the voltage of the common data line CD via the switch MOSFET Q16 is applied to the gate of the driving MOSFET Q13 which is an input of an inverting amplifier circuit composed of an N-channel type driving MOSFET Q13 and a P-channel type load MOSFET Q14. Supplied to The output voltage of the inverting amplifier circuit is supplied to the gate of the amplifying MOSFET Q11. Further, during the non-operation period of the sense amplifier SA, an N-channel MOSFET Q15 is provided between the gate of the amplification MOSFET Q11 and the ground potential point Vss of the circuit in order to prevent the sense amplifier SA from consuming unnecessary current. Provided. The operation timing signal scB of the sense amplifier is commonly supplied to the gates of the MOSFET Q15 and the P-channel MOSFET Q14.

  At the time of reading the memory cell, the sense amplifier operation timing signal scB is set to the low level. As a result, the MOSFET Q14 is turned on and the MOSFET Q15 is turned off. A storage transistor forming a memory cell has a threshold voltage that is higher or lower than a selection level of a word line at the time of a read operation, in accordance with previously written data.

  In the read operation, one memory cell selected from the plurality of memory cells constituting the memory array M-ARY by the above-described address decoders XDCR and YDCR is turned off even though the word line is at the selected level. In the state, the common data line CD is set to a high level limited to a relatively low potential by currents supplied from the MOSFETs Q12 and Q11. On the other hand, when the selected memory cell is turned on by the word line selection level, the common data line CD is set to the low level limited to a relatively high potential.

  In this case, the high level of the common data line CD is obtained by supplying a relatively low level output voltage formed by the inverting amplifier circuits (MOSFETs Q13, Q14) receiving this high level potential to the gate of the MOSFET Q11. Is limited to a relatively low potential. On the other hand, the low level of the common data line CD is compared as described above by supplying a relatively high level voltage formed by the inverting amplifier circuits (MOSFETs Q13, Q14) receiving the low level potential to the gate of the MOSFET Q11. Limited to a very high potential. The data line discharge MOSFETs Q19 to Q21 provided between the data lines D1 to Dn and the source lines have the gate bias signal DS supplied to their gates at an intermediate level as described later. As a result, the data lines in the non-selected state, that is, the data lines in the non-selected state are discharged.

  The amplifying MOSFET Q11 performs an amplifying operation of a gate-grounded source input and transmits an output signal to an input of the CMOS inverter circuit N1. The CMOS inverter circuit N2 forms a signal S0 (in the case where the memory array M-ARY in FIG. 1 is the memory array M-ARY-0 in FIG. 20) obtained by shaping the output signal of the CMOS inverter circuit N1 and corresponding data. This is transmitted to the input of the output buffer DOB # 0. The data output buffer DOB # 0 amplifies the signal S0 and sends it out of the external terminal I / O0.

  The data output buffer is provided with the following functions in addition to the read data output function described above. As will be described later with reference to FIG. 11, data output buffers DOB-0 to DOB-6 corresponding to I / O0 to I / O6 among the eight external input / output terminals are provided with data output buffer activation signals DO and DOB. Performs a three-state output operation including high impedance. On the other hand, the data output buffer DOB-7 corresponding to the external input / output terminal I / O7 is controlled by data output buffer activation signals DO7 and DO7B different from the signals DO and DOB. This data output buffer DOB-7 is used in a data polling mode in which the internal erase state of the EEPROM is read out.

  The write data supplied from the external input / output terminal I / O is transmitted to the common data line CD via the data input buffer DIB. As shown in FIG. 20, even between a common data line corresponding to another memory array M-ARY and an external input / output terminal, a read operation including the same input stage circuit, sense amplifier SA, and data output buffer DOB is performed. And a write circuit including a data input buffer DIB.

(Table 1)
┌───────────┬──┬──┬──┬──┬──┬───────┐
│ │CEB │OEB │WEB │EEB │Vpp│ I / O │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ Non-select │H │ * │ * │ * │Vcc│ Hz │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ Lead │L │L │H │H │Vcc│ output │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ │L │L │L │L │Vcc│ Hz │
│ output │L │L │L │H │Vcc│ Hz │
│Disable │L │L │H │L │Vcc│ Hz │
│ │L │H │ * │ * │Vcc│ Hz │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ light │L │H │L │H │Vpp│ input │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ write verify │L │L │H │H │Vpp│ output │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ Erase │L │H │H │L │V ││ │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ Data polling │ L │ L │ H │ L │ Vpp │ output (I / O7) │
├───────────┼──┼──┼──┼──┼──┼───────┤
│ │H │ * │ * │ * │Vpp│ Hz │
│ Light / Erase │L │L │L │L │Vpp│ Hz │
│ Inhibit │L │L │L │H │Vpp│ Hz │
│ │L │H │L │L │Vpp│ Hz │
│ │L │H │H │H │Vpp│ Hz │
└───────────┴──┴──┴──┴──┴──┴───────┘
(Table 2)
┌────────┬─────────────────────────┐
│ │vp EV sc re DE wp wr AED DC ES POLM PP│
├────────┼─────────────────────────┤
│ Non-select │LLLLLLHLLLLLLLLL│
├────────┼─────────────────────────┤
│Lead │LLHHHLLLLLLLLLL│
├────────┼─────────────────────────┤
│ │LLHHHLLLLLLLLLL│
│ output │LLHHHLLLLLLLLLL│
│Disable │LLHHHLLLLLLLLLL│
│ │LLHHHLLLLLLLLLL│
├────────┼─────────────────────────┤
│ light │HLL LH HH HLL LLL L│
├────────┼─────────────────────────┤
│Write verify│H L H H H L L L L L L L│
├────────┼─────────────────────────┤
│ Erase │ HOOOOOLOLOOLOLLO│
├────────┼─────────────────────────┤
│Data Polling│HLHHHL HHLHLOL│
├────────┼─────────────────────────┤
│ │LL LLL HLL LLL LLL L│
│Light / Erase│HLLLLHLLLLLLLLL│
│inhibit│HLLLLHLLLLLLLLL│
│ │LL LLL HLL LLL LLL L│
│ │LL LLL HLL LLL LLL L│
└────────┴─────────────────────────┘
Although not particularly limited, the timing control circuit CNTR includes the external terminals CEB, OEB, WEB, EEB (hereinafter, may be simply referred to as signals CEB, OEB, WEB, and EEB) and a chip enable signal CEB supplied to Vpp. , An output enable signal OEB, a write enable signal WEB, an erase enable signal EEB, a high voltage Vpp for writing / erasing, a prewrite pulse PP supplied from an internal circuit LOGC for controlling an automatic erasing operation described later, and erasing. The internal control signal ceB, the operation timing signal scB of the sense amplifier, etc., according to the signal ES indicating the mode, the decoder control signal DC, the erase verify signal EV, the automatic erase mode setting delay signal AED, the sense amplifier activation signal VE at the time of verification, etc. Form internal timing signal At the same time, the voltage is selectively switched between a low voltage Vcc for reading, a low voltage Vcv for erasure verification, and a high voltage Vpp for writing selectively supplied to an address decoder or the like, and selectively outputs any one of these voltages.

  The signals PP, ES, DC, EV, AED, VE, and the like formed by the internal circuit LOGC do not affect the operation of the timing control circuit CNTR in modes other than erase. That is, the signals PP, ES, DC, EV, AED, VE, and the like are made valid only in the erase mode, and various signals for an erase operation corresponding to these signals are generated by the timing control circuit CNTR. You.

  FIGS. 6 and 7 are circuit diagrams of an embodiment of a main part of the timing control circuit CNTR. Table 1 shows the external signals supplied to the flash EEPROM via the external terminals and the operation modes corresponding to the external signals. Table 2 shows the internal timing signals formed based on the external signals. Some of the internal timing signals are shown. In Tables 1 and 2, H indicates a high level, L indicates a low level, and Vpp indicates a voltage (for example, about 12 V) higher than the power supply voltage Vcc (for example, 5 V). In the column of the external terminal I / O in Tables 1 and 2, Hz indicates a high impedance state, input indicates data input, and output indicates data output. In particular, output (I / O7) indicates an external input / output terminal. This indicates that I / O 7 is a data output.

  In Tables 1 and 2, * indicates that the signal may be at a high level (H) or a low level (L), and O indicates that the level is controlled by a signal supplied from the internal circuit LOGC to the timing control circuit CNTR. It represents a change. How to read Tables 1 and 2 above will be described by taking a read mode as an example. The same applies to the other modes, which can be easily understood from the following example.

  A low level (L) chip enable signal CEB, an output enable signal OEB, a high level (H) write enable signal WEB, and an erase enable signal EEB are supplied from the outside to the flash EEPROM, and the external terminal Vpp of the flash EEPROM is supplied. When a low voltage such as the power supply voltage Vcc is applied to the CPU, it is determined that the read mode has been instructed by the timing control circuit CNTR, and the timing control circuit CNTR and the internal circuit LOGC output the internal signals VP, EV, wp, Each of wr, AED, DC, ES, POLM, PP is set to low level (L), and each of the internal signals SC, re, DE is set to high level (H). Then, the data held in the memory cell designated by the address signal is output from the external input / output terminals I / O0 to I / O7.

  In this specification, the same signal or the same terminal is denoted by the same symbol. In the drawings, a signal represented by a symbol having a letter “─” at the top of an alphabetical character is represented by a signal represented by the same alphabetic letter and a signal represented by a signal without a character “─” at the top. 3 shows a signal whose phase has been inverted. For example, the symbol vpB is a signal whose phase is inverted with respect to the signal represented by the symbol vp. The signal vp is at a high level (Vcc) when the high voltage Vpp is applied to the external terminal Vpp, and is at a low level (Vss) otherwise.

  The operation of the circuits shown in FIGS. 6 and 7 which constitute the main part of the timing control circuit CNTR will not be described in detail, but will be easily understood from Tables 1 and 2 showing the operation modes and the operation description described later. Let's do it.

  When the chip enable signal CEB is at a high level and no high voltage is supplied to the external terminal Vpp, the flash EEPROM is in a non-selected state.

  In a state where the chip enable signal CEB is set to the low level, the output enable signal OEB is set to the low level, the write enable signal WEB is set to the high level, the erase enable signal EEB is set to the high level, and no high voltage is supplied to the external terminal Vpp. The read mode is set as described above, the internal chip enable signal ceB is set to low level, and the address decoder activation signal DE, the operation timing signal sc of the sense amplifier, and the read signal re are set to high level.

  At this time, a low voltage Vcc (about 5 V) is supplied from the timing control circuit CNTR as an operating voltage to each of the address decoders XDCR and YDCR and the data input circuit DIB. As a result, the sense amplifier SA enters the operating state, and the above-described read operation is performed. At this time, the data line discharge MOSFET inactivation signal SB is set to low level by the circuit shown in FIG. In response, N-channel MOSFET (FIG. 7) receiving deactivation signal SB is turned off, and P-channel MOSFET (FIG. 7) also receiving deactivation signal SB is turned on. At this time, since the sense amplifier operation timing signal sc is at a high level, the N-channel MOSFET (FIG. 7) receiving the signal sc is turned on, and the P-channel MOSFET (FIG. 7) receiving the signal sc is turned off. You. Therefore, the gate bias signal DS of the data line discharge MOSFET becomes an intermediate voltage according to the conductance ratio of the two P-channel MOSFETs (FIG. 7) and the three N-channel MOSFETs (FIG. 7) arranged in series, and the memory array M-ARY The data line discharge MOSFETs Q19 to Q21 provided on the data line are controlled to discharge the data line in the non-selected state.

  The chip enable signal CEB is set to a low level, the output enable signal OEB is set to a high level, the write enable signal WEB is set to a low level, the erase enable signal EEB is set to a high level, and a high voltage (for example, about 12 V) is applied to the external terminal Vpp. Is supplied, the writing mode is set. At this time, the internal chip enable signal ceB is at a low level, the address decoder activation signal DE, the write mode signal WP, the write control signal wr, and the write pulse PG are each at a high level, and the gate bias signal DS, the sense amplifier operation timing The signal scB, the read control signal re, and the data output buffer activation signals DO and DO7 are each set to a low level.

  Each of the address decoders XDCR and YDCR is activated by the high level of the signal DE, and the one designated by the external address signals AX and AY from a plurality of word lines and a plurality of data lines constituting the memory array M-ARY. One word line and one data line are selected. At this time, a high voltage Vpp is supplied from the timing control circuit CNTR as an operating voltage to the address decoders XDCR and YDCR and the data input buffer DIB. As described above, since the read control signal re is at the low level at this time, the MOSFET Q16 is turned off, and the discharge MOSFETs Q19 to Q21 are also turned off by the low level of the gate bias signal DS, and the sense amplifier operation timing signal scB , The sense amplifier SA is inactivated. At this time, since data output buffer activation signals DO and DO7 are at the low level, each of data output buffers DOB-0 to DOB-7 is inactivated. The configuration of the data output buffer DOB will be described later with reference to FIG.

  The potential of the word line to which the selected node of the memory cell to be written is coupled, in other words, the selected word line is set to the high voltage by the address decoder XDCR supplied with the high voltage Vpp as its operating voltage. A high voltage according to Vpp, for example, a high voltage such as about 12V. On the other hand, the selected data line is set to a high voltage or a low potential by the data input buffer DIB according to the information to be written.

  As described above, the memory cell is constituted by the storage transistor shown in FIG. In the memory cell whose selected node is coupled to the selected word line and whose input / output node is coupled to the selected data line, that is, in the selected memory cell, the electron is connected to the floating gate of the storage transistor constituting it. Is implanted, the potential of the selected data line is set to a high voltage according to the high voltage Vpp via the MOSFET Q18 turned on in response to the high level of the write control signal wr and the data input buffer DIB. As a result, a channel saturation current flows through the storage transistor, and electrons accelerated by a high electric field are ionized in a pinch-off region near the drain region coupled to the data line, generating electrons having high energy, so-called hot electrons.

  On the other hand, the potential of the floating gate of this storage transistor is determined by the voltage of the control gate to which the word line is coupled and the voltage of the drain region, the capacitance between the semiconductor substrate and the floating gate, and the capacitance between the floating gate and the control gate. It becomes. Thus, hot electrons are attracted to the floating gate, and the potential of the floating gate becomes negative. By setting the potential of the floating gate to be negative, the threshold voltage of the storage transistor into which electrons are injected rises and becomes higher than before the injection of electrons.

  On the other hand, when electrons are not injected into the floating gate of the storage transistor constituting the selected memory cell, the threshold voltage of the storage transistor does not increase and is kept at a relatively low value. In order to prevent electrons from being injected into the floating gate of the storage transistor that constitutes the selected memory cell, the selected data line is turned on in the drain region of the storage transistor. What is necessary is just to apply a low voltage via the MOSFET Q18 and the data input buffer DIB such that hot electrons are not generated in the pinch-off region near the drain region.

  Whether to apply the above-described high voltage or the above-described low voltage to the drain region of the storage transistor of the selected memory cell is determined by information to be written. The data input buffer DIB, which will be described later with reference to FIG. 22, forms the above-described high voltage or low voltage according to information supplied via the external input / output terminal I / O, and the formed voltage is set as described above. It is transmitted to the selected data line.

  The storage transistor whose threshold voltage has been increased by the injection of electrons into the floating gate is supplied to the control gate thereof in the read mode even if a selection signal of a selection level (for example, 5 V) is supplied to the storage transistor. Even if the word line to which the selected node is coupled is selected, the word line is not turned on, but is turned off. On the other hand, in the storage transistor in which electrons have not been injected, the threshold voltage thereof is held at a relatively low voltage. Therefore, in the read mode, when the selection signal of the selection level is supplied, That is, by the operation of selecting the word line, the conductive state is established, and the current flows.

  In the write mode, a high voltage is not applied to a control gate and / or a drain region of a storage transistor included in a memory cell that is not selected. Therefore, electrons are not injected into the floating gate, and the threshold voltage of the storage transistor does not change.

  The chip enable signal CEB was set to low level, the output enable signal OEB was set to low level, the write enable signal WEB was set to high level, the erase enable signal EEB was set to high level, and the high voltage Vpp was supplied to the external terminal Vpp. In the state, the mode is set to the write verify mode. Except that the high voltage Vpp is supplied to the external terminal Vpp, the state is the same as in the read mode. The operating voltage of each of the address decoders XDCR and YDCR and the data input circuit DIB is switched from the high voltage Vpp to the low voltage Vcc and supplied.

  In the write / inhibit mode shown in Tables 1 and 2, each decoder is activated, but the high voltage Vpp for writing / erasing is not supplied to each decoder. In this mode, the gate bias signal DS is set to a high level, and a preparation period for writing / writing verification / erasing in which the data line is discharged is performed.

  The chip enable signal CEB and the erase enable signal EEB are set to the low level, the output enable signal OEB and the write enable signal WEB are set to the high level, and the high voltage Vpp is applied to the external terminal Vpp, thereby starting the erase mode. . As will be described later with reference to FIG. 21, the start of the erase mode is instructed by the combination of the voltages of these external signals, and it does not mean that the erase mode will end unless this state is maintained.

  The erasing mode in the flash EEPROM of this embodiment is shown in the operation flowchart of FIG. 2 showing an example of the algorithm, a specific circuit diagram of the main part of the internal circuit LOGC shown in FIGS. 3 and 4, and FIG. This will be described in detail below with reference to the operation timing diagram shown. The internal circuit LOGC functions as an erase control circuit.

  Since the circuits shown in FIGS. 3 and 4 perform the sequence control for executing the algorithm shown in the flowchart of FIG. 2, the operation timing chart of FIG. 5 described later is referred to. It will be easily understood from the description of the erase operation mode.

  In the flowchart of FIG. 2, a series of prewrite operations as indicated by the dotted lines in FIG. 2 are performed prior to the actual erase operation. This is because the stored information of the memory cell in the memory array M-ARY before erasing, in other words, the threshold voltage of the storage transistor is determined by the presence or absence of writing as described above (the presence or absence of injection of electrons into the floating gate). It is performed to be high and low according to. That is, the memory array M-ARY before erasing is executed because the storage transistor whose threshold voltage is increased and the storage transistor whose threshold voltage is maintained at a relatively low value are mixed.

  The above-described pre-write operation is to perform writing to all the storage transistors prior to the electrical erase operation. Thereby, the internal automatic erasing according to this embodiment is performed on an unwritten memory cell (in which electrons are not substantially injected into the floating gate of the storage transistor constituting the memory cell) which is in an erased state. By performing the operation, the threshold voltage of the storage transistor in the unwritten memory cell is prevented from becoming a negative threshold voltage.

  In this prewrite operation, first, in step (1), an address is set. That is, the setting of the address counter circuit is performed such that the address signal for selecting each memory cell is generated by the address counter circuit. By the address setting, although not particularly limited, an address signal indicating an address of a memory cell to be written first is generated by the address counter circuit.

  In step (2), a write pulse is generated, and write (prewrite) is performed on a memory cell specified by an address signal generated by the address counter circuit.

  After this writing, step (3) is performed. In this step (3), an address increment is performed such that the address counter circuit is operated by an increment (+1).

  Then, in step (4), it is determined whether or not the address signal generated by the address counter circuit indicates the final address. If the above prewriting has not been performed up to the final address (NO), the process returns to the step (2) and the prewriting is performed. This is repeated until the last address. After the step (3) of performing the address increment as described above, it is determined whether or not prewriting has been performed up to the final address. Therefore, the actually determined address is the final address + 1. Of course, after the step (4) of determining the final address, a step (3) of address increment may be provided. In this case, when the determination is NO, step (3) is provided on the path returning from step (4) to step (2) so that the address increment is performed. When the above pre-writing is performed up to the final address (YES), the following erasing operation is executed next.

  In step (5), initial setting of an address for an erase operation is performed. That is, the initial design of the address signal is performed for the address counter circuit. In this embodiment, since all the memory cells in the flash EEPROM are collectively erased, the initial setting of this address has no special meaning in the erase operation itself. This address setting is required for a verify operation (erase verify) performed after the erase operation.

  In step (6), an erase pulse for batch erase is generated, and an erase operation is performed. Thereafter, a verify operation is performed in step (7) according to the address setting. In this verify operation, as will be described later, the operating voltage is lower than the low power supply voltage Vcc (for example, 5 V) supplied via the external terminal Vcc (for example, 5 V), and is lower than the low voltage Vcv such as 3.5 V. Such a read operation is performed. That is, the above-described low voltage Vcv is supplied to the address decoders XDCR, YDCR and the sense amplifier SA instead of the power supply voltage Vcc as their operation voltages.

  At this time, the power supply voltage Vcc is supplied as an operating voltage to the internal circuit LOGC and the timing control circuit CNTR. In this read operation, if the read signal is "0", that is, if the storage transistor is turned on, it is recognized that the threshold voltage of the storage transistor is in the erased state of 3.5 V or less. Then, step (8) is executed. In this step (8), the address of the address counter circuit is incremented.

  Then, similarly to the case of the prewrite operation, in step (9), it is determined whether or not the address signal formed by the address counter circuit indicates the final address. If it is not the final address (NO), the process returns to step (7), and the same erase verify operation as described above is performed. This operation is repeated until the address counter circuit indicates the final address, thereby completing the erase operation.

  As described above, in the present embodiment, since the storage information of the memory array M-ARY is erased collectively, in the above-described erasing operation, the threshold voltage becomes highest due to the writing operation among all the memory cells. The number of times of erasing is determined by the memory transistor thus set. That is, the erasing pulse is applied (erasing operation) in step (6) until the memory transistor having the highest threshold voltage can be read at the above-mentioned 3.5 V, that is, has a low threshold voltage. Then, whether or not the storage transistor has the low threshold voltage is detected by the erase verify operation in step (7). That is, whether or not the erase pulse is applied (erase operation) in step (6) is determined based on the verification result in step (7).

  The above-described erase operation mode will be described in detail with reference to the operation timing chart of FIG. 5 and the specific circuits of FIGS. In the following description, FIGS. 6 and 7 and Tables 1 and 2 described above are also referred to.

  In a state where the chip enable signal CEB is set to the low level, the output enable signal OEB is set to the high level, the write enable signal WEB is set to the high level, and the high voltage Vpp (for example, about 12 V) is supplied to the external terminal Vpp, As is clear from the specific circuit of the timing control circuit CNTR shown in FIG. 6 and Tables 1 and 2, the internal chip enable signal ceB and the erase start signal ecB are at the low level. Therefore, when the erase enable signal EEB changes from the high level to the low level, the flip-flop circuit FF1 is set accordingly.

  As a result, the signal ES indicating the erasing mode changes from the high level to the low level to enter the erasing mode. The internal signal ES2B changes to low level with a delay of a predetermined time determined by the delay time of the delay circuit D1. When the signal ES indicating the erase mode changes to a high level, it is fed back to the NOR gate circuit NOR1. Therefore, the erase mode signal ES is held by this feedback operation until the erase mode signal ER is generated. Therefore, during the erasing mode, the NOR gate NOR1 does not receive any signal changes of CEB, OEB, WEB and EEB represented by the internal signal ec thereafter. That is, the erase control circuit LOGC does not accept the external control signal as described above, and executes the erase sequence. In other words, the erase mode signal ES prevents a change in the external control signal from affecting the internal operation. For example, in FIG. 6, the circuit that forms the decoder activation signal DE is not affected by the signal ceB based on the chip enable signal CEB when the erase mode signal ES is set to the high level.

  Before performing the erase operation, the prewrite operation is performed. The oscillation circuit O1 is activated by the address increment start signal AIS and the oscillator control signal OSC for the pre-write operation of performing writing for all bits for a certain period of time. The output signal of the oscillation circuit O1 is divided by a 4-bit binary counter circuit BCS1 to generate a prewrite pulse PP. The generation of the prewrite pulse PP is not limited to the one generated from the frequency-divided signals OS3 and OS4 and the prewrite control signal PC obtained by the above-described frequency division, and various modifications can be adopted. Needless to say,

  The output signal of the counter circuit BCS1 is supplied to a binary counter circuit BCS2. This counter circuit BCS2 operates as an address counter circuit and generates internal address signals A5I, A6I,... A2I. These address signals A5I, A6I... A2I are input to address buffers XADB and YADB. The erase mode signal ES is used for switching the inputs of the address buffers XADB and YADB. Each of the address buffers XADB and YADB is configured by a plurality of unit circuits having the same configuration.

  FIG. 9 shows the unit circuit. As shown in the drawing, the input of the unit circuit is changed from the external address signals AX and AY supplied via the external terminals AX and AY to the internal address signals AXI and AYI, respectively, according to the high level of the erase mode signal ES. The internal complementary address signals ax, axB and ay, ayB to be transmitted to the address decoders XDCR, YDCR are formed by switching. That is, due to the high level of the signal ES, the unit circuits of the address buffers XADB and YADB are not allowed to receive the external address signals AX and AY from the external terminals, and the internal circuits corresponding to the internal address signals A5I, A6I... Address signals AXI and AYI are received.

  Although not particularly limited, the counter circuit BCS2 generates the same number of internal address signals AXI and AYI as the external address signals AX and AY. Thus, one memory cell is selected from each memory array M-ARY by the internal address signals AXI and AYI. Information is supplied to the selected memory cell from the data input buffers DIB-0 to DIB-7 and written (pre-write). In this case, the data input buffers DIB-0 to DIB-7 form information not based on data from the external terminals I / O0 to I / O7, but on the basis of the prewrite pulse PP.

  When pre-writing is completed for all addresses of the memory array, the final address signal END becomes high level, and the flip-flop circuit FF2 is set. As a result, the automatic erase mode setting signal AE becomes high level, and the erase period starts. The address increment signal AIS and the oscillator control signal OSC are changed to low level by the internal signal PSC, and the oscillation circuit O1 and the counter circuits BCS1 and BCS2 are reset. The delay time set by the delay circuit D2 is a preparation period for performing erasing, and is used for setting all the word lines to a non-selected state or discharging the data lines.

  Thereafter, the erase start signal ST goes high for a fixed time set by the delay circuit D4, and the flip-flop circuit FF3 is set. After a time set by the delay circuit D5, the erase pulse EPB goes low. Due to the low level of the erase pulse EPB, a high voltage Vpp is applied to the source of the memory cell via the erase circuit ERC as described above.

  Although not particularly limited, the erase circuit ERC is a circuit shown in FIG. The signal EPB is basically supplied to the gate of the P-channel MOSFET Q17 via an inverter circuit using the low voltage Vcc as an operating voltage and an inverter circuit having a level shift function using the high voltage Vpp as the operating voltage. Is transmitted to the gate of the N-channel MOSFET Q10 via two stages of inverter circuits having an operating voltage of. In the figure, a signal EXTE is set to a high level in a normal erase mode, that is, when the erase operation is performed only for a period set by an external signal, in addition to the internal automatic erase mode in this embodiment. This is an external erase mode signal.

  The configuration and operation of the erasing circuit ERC are as follows. The NAND gate circuit receiving the erase pulse EPB substantially operates as an inverter circuit when the external erase mode signal EXTE is at a low level. Therefore, the signal EPB is supplied to the high voltage via the cut MOSFET in which the power supply voltage Vcc is constantly supplied to the gate and the high voltage Vpp is constantly supplied to the gate through the three inverter circuits. It is supplied to the gate of a P-channel MOSFET constituting a CMOS inverter circuit having an operating voltage of Vpp. The output signal of the last-stage inverter circuit is supplied to the gate of the N-channel MOSFET constituting the CMOS inverter circuit.

  Instead of this configuration, the gate of the N-channel MOSFET may be connected to the gate of the P-channel MOSFET. A feedback P-channel MOSFET for receiving a level-converted output signal is provided between the gate of the P-channel MOSFET and the high voltage Vpp. In the circuit of this embodiment, when the erase pulse EPB is set to low level, the output of the last-stage inverter circuit is set to high level, so that the N-channel MOSFET is turned on and the output signal is set to low level. As a result, the P-channel MOSFET for feedback is turned on, and the gate voltage of the P-channel MOSFET constituting the CMOS inverter circuit is increased, so that the P-channel MOSFET is turned off. Further, since the cutting MOSFET is turned off, a DC current is prevented from flowing from the high voltage Vpp to the final stage inverter circuit operating at the low voltage Vcc. As a result, the output signal is set to low level, so that the MOSFET Q17 is turned on, and the potential of the source region of the memory cell is set to the high voltage Vpp.

  At this time, the gate voltage of the MOSFET Q10 is at a low level, so that the MOSFET Q10 is turned off. When the erase pulse EPB is set to a high level, the output of the last-stage inverter circuit goes to a low level, so that the N-channel MOSFET is turned off and the P-channel MOSFET is turned on. As a result, the output signal becomes a high level such as the high voltage Vpp, and the P-channel MOSFET Q17 is turned off. At this time, the feedback P-channel MOSFET is turned off by the high level of the output signal. At this time, the gate voltage of the N-channel MOSFET Q10 becomes high level. As a result, the MOSFET Q10 is turned on, and the source potential of the memory cell is set to the ground potential of the circuit.

  Returning to FIG. 4 again, in FIG. 4, the oscillation circuit O2 and the binary counter circuit BCS3 output the erase pulse end signal PE after the time determined by the erase pulse EPB being set to the low level has elapsed. The level is changed from the low level to the high level, and the flip-flop circuit FF3 is reset. In response, the erase pulse EPB changes to a high level, so that the potential of the source of the memory cell is switched from the high voltage Vpp to the ground potential Vss of the circuit by the erase circuit ERC.

  After a delay time set by the delay circuit D7, the erase verify signal EV changes to a high level and shifts to the erase verify mode. At this time, unlike the pre-write operation, the counter circuits BCS1 and BCS2 are electrically disconnected from each other by the automatic erase mode setting signal AE, and the counter circuit BCS1 is used to generate a reference pulse for verification. The circuit BCS2 is used for generating an internal address signal for verification, not for prewrite.

  That is, the output signal OS2 of the counter circuit BCS1 is a high-level signal in the first half of the cycle and a low-level signal in the second half of the cycle, and the output signals S0 to S7 from the sense amplifier SA during the low level (in the case of an 8-bit output). ) Is performed, and when the signals S0 to S7 of all bits output from the sense amplifier SA are at low level, in other words, of the eight storage transistors selected by the counter circuit BSC2. In the erase state in which the respective threshold voltages are lowered, the flip-flop circuit FF3 is not set, and the internal address signals AXI and AYI indicating the next address are sent to the counter circuit in response to the address increment signal EAI at the time of verification. The signal OS2 is formed by BSC2, and is again in the low level period of the signal OS2. Determination to be carried out.

  In this manner, internal address signals AXI and AYI are formed in accordance with the address increment signal EAI at the time of verification, and the memory cell is determined according to the internal address signals AXI and AYI. If one or more bits of the output signals S0 to S7 of the sense amplifier SA are at a high level, that is, if there is a memory cell in which even one bit has not been erased, the flip-flop circuit 3 is set by the NOR gate circuit NOR2. Then, a low-level erase pulse EPB is generated again. The above-described erase operation is performed again by the low-level erase pulse EPB, and thereafter, the above-described erase verify is executed again.

  FIG. 5 shows an example in which it is determined that erasure has been performed at four addresses indicated by the internal signal OS2, and it has been determined that erasure has not been performed at the fifth address, and the verify period has ended. At this time, the operation of the delay circuit D8 prevents the last pulse of the signal OS2 from appearing in the address increment signal EAI, indicating that the last pulse remains at the address determined not to be erased last. In other words, the counter circuit BSC2 holds an address signal indicating an address determined not to be erased. Therefore, although not particularly limited, the erase verify after the automatic erase is performed again is executed from the address where it was previously determined that the erase was not performed. Here, the basic pulse in the verify mode is the output signal OS2 of the frequency divider, but it is needless to say that the present invention is not particularly limited to this.

  When the memory cells corresponding to all the addresses are verified by repeating the above operation, the end address signal END becomes high level as in the end of the prewrite, and the flip-flop circuit FF2 is reset. In response to the reset of the flip-flop circuit FF2, the automatic erase mode setting signal AE changes to a low level, and the erase mode end signal ER is set to a high level for a delay time set by the delay circuit D9.

  The flip-flop circuit FF1 is reset by the high level of the signal ER, and after the delay time set by the delay circuit D1, the signal ES indicating the erase mode is changed to the high level, so that no external signal is accepted. Is released.

  The binary counter circuit BCS4 counts the number of occurrences of the erase pulse EPB. If the erase mode does not end as described above even after counting a certain number of pulses EPB, the abnormality detection signal FAIL is set to the high level, and the erase mode is forcibly ended. That is, an erase mode end signal ER is generated. In the logic circuit for forming the erase mode end signal ER, a gate circuit to which the internal signal PSTOP and the end address signal END are inputted is shown. This is because this mode can be ended by an internal signal PSTOP generated by the signal.

  In the above description, the specific circuits of the erase control circuit LOGC shown in FIGS. 3 and 4 have been mainly described with reference to the timing chart of FIG. 5, but actually the erase control circuit LOGC has been generated. Each signal controls an address buffer, a decoder, a MOSFET, and the like via a timing control circuit CNTR.

  In the signal generation circuits such as the signals DE, SB, sc, re, wr, PG, and DO shown in FIGS. 6 and 7, the signals of the external terminals CEB, OEB, WEB, and EEB are generated by the signals ES and AED during the erase mode. Input is disabled and controlled internally. For example, during the period when the erase pulse EPB is at a low level, that is, during the period of performing the electrical erase, the signal DC in FIGS. 3 and 4 is at a high level, the signal DE is at a low level, and the decoders XDCR and YDCR are inactivated. It becomes. Therefore, all word lines and all data lines are in a non-selected state. In the other periods, the state is similarly determined by the output signal of the erase control circuit LOGC shown in FIGS.

  The data polling mode is a mode for determining whether or not erasing is being performed. Therefore, it can be regarded as a mode for knowing the internal state of the EEPROM, that is, a status polling mode. A state in which the chip enable signal CEB is set to low level, the output enable signal OEB is set to low level, the write enable signal WEB is set to high level, the erase enable signal EEB is set to low level, and the high voltage Vpp is supplied to the external terminal Vpp. To enter this mode. In this mode, the data polling control signal POLMB goes low in the circuits shown in FIGS. At this time, the data output buffer activation signal DO7 is set to high level, but the data output buffer activation signal DO is set to low level by the data polling control signal POLMB.

  FIG. 11 shows a specific circuit of the data output buffer DOB. Except for the data polling (status polling) control circuit DP, data output buffers DOB-0 to DOB-6 corresponding to external input / output terminals I / O0 to I / O6 and data corresponding to external input / output terminals I / O7 There is no difference in the configuration of the output buffer DOB-7 from the fact that the output buffer DOB-7 is a three-state output circuit including a high-impedance state. As described above in the read mode, when the activation signals DO and DO7 become high level, the sense is made. The operation of inverting and outputting the output signals S0 to S7 from the amplifier SA is performed.

  On the other hand, in the data polling mode (status polling mode), since the activation signal POLMB is at the low level, the output signal S7 is invalidated, and the terminal I / O7 is driven according to the level of the signal ES indicating the erase mode at that time. The output signal is determined. That is, during the erase mode, the signal ES indicating the erase mode is at the low level, so that a low-level signal is output from the external input / output terminal I / O7, and a high-level signal is output if the erase operation has been completed. You.

  FIG. 12 shows a power supply circuit for generating the operating voltage Vcv in the erase verify mode supplied to the sense amplifier SA and the address decoders XDCR and YDCR. This circuit is configured using a known reference voltage generation circuit VREF using a silicon band gap, and operational amplifier circuits OP1 and OP2. That is, the reference voltage VR formed by the reference voltage circuit VREF is amplified by the operational amplifier OP1 in accordance with the gain (R1 + R2) / R2 determined by the resistors R1 and R2 to form a voltage of about 3.5V. . This voltage is output through a voltage follower-type operational amplifier circuit OP2 to obtain the voltage Vcv.

  The operational amplifier circuits OP1 and OP2 are activated by the automatic erase mode setting signal AE to generate the voltage Vcv. This makes it possible to prevent the power supply circuit from consuming current in another operation mode. When an output circuit composed of a P-channel MOSFET and an N-channel MOSFET is used as the output circuit of the operational amplifier OP2, when the operational amplifier is deactivated by the signal AE, the P-channel is output by the signal AE. The MOSFET is turned on to output the low power supply voltage Vcc. By employing this configuration, a function of switching between the voltages Vcc and Vcv can be added to the power supply circuit by the signal AE. As the above-mentioned reference voltage generating circuit VREF, for example, the one disclosed in British Patent No. 2081458B can be used.

  The operating voltage during the erase verify operation is set lower than the power supply voltage Vcc in the flash EEPROM in the read mode so as to be substantially equal to the lower power supply voltage Vccmin at which the read operation can be performed on the flash EEPROM. It is desirable to do. Although it is assumed here that a power supply is built in as shown in FIG. 12, the signal AE is output to the outside of the flash EEPROM, and a programmable power supply provided outside is controlled by the signal AE. The voltage may be supplied to a circuit to which the voltage Vcv is to be applied, such as the sense amplifier SA and the address decoders XDCR and YDCR of the flash EEPROM. Here, the above-mentioned lower limit voltage Vccmin is the lowest power supply voltage Vcc (external to the EEPROM) that enables reading of stored information from the memory cell having the highest threshold voltage among the memory cells constituting the EEPROM. (Applied to terminal Vcc).

  FIG. 23 is a circuit diagram of a unit circuit constituting the address decoders XDCR and YDCR. Each address decoder is composed of a plurality of unit circuits having the same configuration. However, the combination of the supplied internal address signals differs in each unit circuit. FIG. 23 shows one of these unit circuits as an embodiment.

  In the figure, UDG is a unit decoder circuit, and is constituted by, for example, a NAND circuit receiving an internal address signal ax (ay) and an address decoder activating signal DE. The output signal of the NAND circuit is supplied to a level conversion circuit having the same configuration as the circuit shown in FIG. In the level conversion circuit of FIG. 23, the high voltage Vpp, the power supply voltage Vcc, and the low voltage Vcv are selectively supplied from the timing control circuit CNTR to a node corresponding to the node to which the high voltage Vpp was supplied in FIG. Supplied. On the other hand, the power supply voltage Vcc is constantly supplied to the NAND circuit UDG.

  Thus, during a write operation or pre-write, the high voltage Vpp is applied to the word line W (selection line CL of the column switch MOSFET) specified by the internal address signal ax (ay) from the address buffer XADB (YADB). The unit circuit outputs a selection signal having a voltage substantially equal to. In the read operation, a selection signal having a voltage substantially equal to the power supply voltage Vcc is output to the word line W (selection line CL) specified by the internal address signal ax (ay). In the erase verify mode, a select signal having a voltage substantially equal to the low voltage Vcv is applied to the word line W (select line CL) designated by the internal address signal ax (ay) from the address buffer XADB (YADB). Is output.

  During the erase operation, the activation signal DE is set to the low level as described above, so that a voltage substantially equal to the ground potential Vss of the circuit is supplied from all the unit circuits to the word line W (select line CL). . Note that a voltage according to the ground potential Vss of the circuit is supplied to the unselected word lines W (selection lines CL). Further, as described above, at the time of pre-write and erase verify, not the external address signal AX (AY) but the internal address signal AXI (AYI) formed by the counter circuit is taken into the address buffer XADB (YADB). An internal address signal ax (ay) corresponding to this is formed.

  FIG. 22 is a circuit diagram showing one embodiment of the data input buffer DIB. The data input buffer DIB is commonly used for writing data from an external input / output terminal I / O to a memory cell and for writing predetermined data to a memory cell during prewriting. In the case of the write mode, the write mode signal wp is set to the high level and the prewrite pulse PP is set to the low level as can be understood from Tables 1 and 2. Therefore, the data supplied to the external input / output terminal I / O is transmitted to the input node of the inverter via the two NOR circuits. After the data transmitted to the input node is inverted in phase by the inverter, the data is supplied to a bias circuit composed of one P-channel MOSFET and two N-channel MOSFETs connected in series.

  The data converted to a predetermined level by the bias circuit is supplied to the gate of a write P-channel MOSFET QPI. The write P-channel MOSFET QPI is coupled to the common data line CD via the MOSFET QL whose gate is supplied with a predetermined bias voltage and the above-described MOSFET Q18, and is to be written via the selected data line. Coupled to the drain of the memory cell (storage transistor). The P-channel MOSFET QPI supplies a voltage according to data to be written to the drain of the memory cell. Thus, data is written to the memory cells. However, when the threshold voltage of the storage transistor of the memory cell becomes negative, the current Iw flowing through the MOSFET QL or the like increases, and the voltage drop in the MOSFET QL or the like increases. You can not do it. On the other hand, according to the present embodiment, since the threshold voltage can be prevented from becoming negative, the current Iw can be prevented from increasing, and data can be reliably written.

  At the time of the pre-write operation, since the signal wp is at a low level, data from the external input / output terminal I / O is not taken in. Instead, writing is performed using the prewrite pulse PP as write data.

  FIG. 21 shows a timing chart focusing on the external input signal and the external output signal in the above-described automatic erase mode. When the erase enable signal EEB changes from the high level to the low level at the time t1, the latch provided inside the flash EEPROM operates to enter the automatic erase mode. Thereafter, the flash EEPROM does not accept any external signal except for a combination of external signals indicating a data polling request until the erasure is completed at time t4.

  After the erase enable signal EEB is kept at the low level for a certain fixed time or more internally, the external control signals of CEB, OEB, WEB, and EEB may be in any combination. In the automatic erasing mode of the present embodiment, erasing is not performed during the low level period of the erase enable signal EEB. Therefore, the above-mentioned fixed time is required for setting the latch circuit shown in FIG. 3 to a predetermined state or the like, and is sufficiently shorter than the time required for erasing the memory cell. Further, the external address signal is not shown in this figure, but is not taken in, so that any combination may be used.

  The figure shows an example in which the data polling mode is entered at time t2. At time t3 determined by an internal signal delay, a data polling signal appears at the external input / output terminal I / O7. Since the erasure has not been completed between the time t3 and the time t4, the output is at the low level. When the erasing ends at time t4, the level changes to a high level, and the erasing end can be detected from outside the flash EEPROM. In the automatic erasing mode, the external input / output terminals I / O0 to I / O6 are in a floating state. The external input / output terminal I / O7 is also in a floating state in the automatic erase mode except for the polling mode.

  FIG. 24 shows a waveform diagram of the erase enable signal EE supplied from the outside when erasing the storage information of the memory cell. FIG. 24A shows a waveform diagram of the erase enable signal EEB in the above-described automatic erase mode. FIG. 24B shows a waveform of an erase enable signal EEB when an erasing operation and a verifying operation are instructed from the outside, and FIG. 24C shows an erasing enable signal EEB simply for erasing stored information from the outside. 5 shows a waveform in the case where the instruction is made. These waveforms show the case of batch erasure.

  In FIG. 24B, during a period EO (for example, 10 ms) in which the signal EEB is at a low level, an erasing operation of a memory cell (for example, 1 byte) is actually performed and a period in which the signal EEB is at a high level In the VO, a verify operation involving a read operation from a memory cell (1 byte) is actually performed. In FIG. 24C, the erase operation is actually performed on all the memory cells on the chip during a period EO ′ (for example, 1 second) during which the signal EEB is at the low level.

  On the other hand, in the above-described automatic erasing mode, the signal EEB only needs to be at the low level for the time required to set the latch circuit and the like shown in FIG. 3 to the predetermined state. Therefore, the time during which the erase enable signal EEB is held at a low level may be shorter than those shown in FIGS. 24B and 24C, and may be, for example, about 50 ns. This is because in the automatic erase mode, the actual erase operation for the memory cells is not performed during the low level of the erase enable signal EEB.

  In this embodiment, the internal configuration mainly for the automatic erase mode has been described. However, the erase mode shown in FIGS. 24B and 24C may be executed together. .

  FIGS. 24D and 24E show the external address signals AX and AY and the output signal of the external input / output terminal I / O in the read cycle. In order to enter the read mode, it is necessary to set each external signal as shown in Tables 1 and 2 above. In the drawing, the external address signal and the output signal are shown as described above. I have. For example, by applying external address signals AX and AY indicating the desired address Ai from the standby mode to the EEPROM, the data Di held at the address Ai is output from the external input / output terminal I / O. Thereafter, the EEPROM is again set to, for example, a standby mode. In this read cycle, a selection operation of a memory cell, activation of a sense amplifier, and the like are performed. Therefore, a cycle time of about 100 to 200 ns is required, for example.

  On the other hand, in the erase mode shown in FIG. 24A, the pulse width of the erase enable signal EEB may be as short as about 50 ns as described above. Therefore, as will be described later with reference to FIGS. 14 and 15, it is possible to prevent a device (CPU or the like) for controlling the EEPROM from being exclusively used for the erasing operation of the EEPROM for a long time. The pulse width of the erase enable signal EEB (FIG. 24A) may be shorter than the time required to actually erase the memory cell. This is because, as described above, the erase enable signal EEB does not perform the actual erase operation but instructs the EEPROM to perform the erase operation.

  In this embodiment, the erase verify is performed for all the addresses, but the present invention is not limited to this. The threshold voltage may be changed depending on the required degree of control of the threshold voltage after erasing. For example, only one data line may be verified, or in an extreme case, only one representative bit (memory cell) may be verified. If the verifying power supply voltage Vcv can be set sufficiently lower than the required readable lower limit voltage Vccmin, a sufficiently readable lower limit power supply voltage Vccmin can usually be ensured even by such a method. In FIG. 5, PSTOP is a signal for a test.

  FIG. 13 is a circuit diagram showing another embodiment of the EEPROM to which the present invention is applied. In this embodiment, as in the embodiment of FIG. 1, only one memory array and the corresponding peripheral circuits are shown. See FIG. 20 above for the whole.

  The memory cell of the EEPROM of this embodiment is configured such that electrical erasing is performed on the drain region side instead of the electrical erasing performed on the source region side as in the above embodiment. That is, in this embodiment, the source line CS of the memory array M-ARY is fixedly connected to the ground potential point Vss of the circuit.

  The erasing circuit ERC and the output nodes of the P-channel MOSFET Q17 and the N-channel MOSFET Q10 that are switch-controlled by the erasing circuit ERC are connected to a common data line CD via a P-channel type switch MOSFET Q25. The switch MOSFET Q25 has the gate applied with the erase pulse EPB as described above. As a result, the switch MOSFET Q25 is turned on only during the period in which the erase pulse EPB is at the low level, and changes the high voltage Vpp output through the P-channel MOSFET Q17 that is turned on based on the low level of the erase pulse EPB to the common data. Tell the line CD. The address decoder YDCR transmits the high voltage Vpp of the common data line CD to the data lines in order to collectively erase all the memory cells in the memory array M-ARY, for example, in response to the erase pulse EPB. , All the column switch MOSFETs Q7 to Q9 are turned on.

  If, instead of this configuration, the column decoder YDCR generates a selection signal according to an internal or external address, erasing can be performed in units of data lines. Therefore, in the EEPROM of this embodiment, the control of the address decoder YDCR at the time of the erase operation is different from that of the embodiment of FIG. Other parts are the same as those in FIG. 1, and therefore, refer to FIG.

  FIG. 14 is a block diagram showing one embodiment of a microcomputer system using a flash (FLASH) EEPROM according to the present invention.

  The microcomputer system according to this embodiment includes a microprocessor CPU, a ROM (read only memory) storing programs and the like, a RAM (random access memory) used as a main memory device, and an input / output port I. / OPORT, the batch erase type EEPROM according to the present invention, a liquid crystal display device or a CRT (cathode ray tube) as a monitor connected via a control circuit CONTROLLER, an address bus ADDRESS, a data bus DATA, and control signals. They are interconnected by a control bus for transmitting CONTROL.

  In this embodiment, the 12V power supply RGU required for the operation of the display device LCD and CRT is also used as the high voltage Vpp of the EEPROM. Therefore, in this embodiment, the power supply RGU is provided with a function of switching the terminal Vpp to 5 V such as Vcc at the time of a read operation by a control signal from the microprocessor CPU. FIG. 15 shows a connection relationship between the microprocessor CPU and each signal focusing on the EEPROM.

  To the chip enable terminal CEB of the EEPROM, an address signal indicating the address space allocated to the EEPROM among the system addresses is supplied to the decoder circuit DEC to generate the chip enable signal CEB. The timing control circuit TC receives an R / W (read / write) signal, a DSB (data strobe) signal and a WAIT (wait) signal from the microprocessor CPU, and outputs an output enable signal OEB, a write enable signal WEB, and an erase enable. The signal EEB is generated. The data terminal of the microprocessor CPU is connected to external input / output terminals I / O0 to I / O7 of the EEPROM via a data bus, and the address terminals of the microprocessor CPU are partially connected to the EEPROM via the address bus. Are connected to the external address terminals AX and AY.

  In the microcomputer system of this embodiment, since the EEPROM has the above-described automatic erasing function, the microprocessor CPU addresses the EEPROM to generate the signal CEB, and simultaneously generates the signal CE / B, the signals R / W, DSB and Signals OEB, WEB and EEB designating the erase mode as shown in FIG. 21 are generated by the combination of WAIT. Thereafter, the EEPROM enters the automatic erase mode internally as described above. When the EEPROM enters the erasing mode, the address terminal, the data terminal, and all the control terminals become free as described above, and the EEPROM is electrically separated from the microprocessor CPU. Accordingly, the microprocessor CPU only instructs the erasing mode to the EEPROM, and thereafter uses the system bus to transmit and receive information to and from another memory device ROM or RAM, or an input / output port. Can be performed.

  As a result, the erasure of the batch erasure type EEPROM can be performed in the same state as the full-function (rewritable by byte) EEPROM mounted on the system without sacrificing the throughput of the system. After giving the instruction of the erasing mode as described above, the microprocessor CPU designates the data polling mode for the EEPROM at an appropriate time interval so that the level of the terminal I / O7 of the data bus becomes low level. It is determined whether the erasing operation has been completed by determining whether the erasing operation has been completed. If the erasing is completed and there is data to be written in the EEPROM, the writing is instructed.

The operational effects obtained from the above embodiment are as follows. That is,
(1) An EEPROM including a memory array in which electrically erasable nonvolatile storage elements are arranged in a matrix is provided with at least one corresponding memory cell after performing an erasing operation in accordance with an external erasing operation instruction. The EEPROM itself has an erasure confirmation function, that is, the above-mentioned automatic erasure function with reading by incorporating a built-in erasing control circuit that performs erasing operations and controls continuation and stop of the erasing operation based on the read information. Therefore, an erasing operation can be performed without placing a burden on the microprocessor while keeping it in the system.
(2) By adding a pre-write function of performing writing to all memory cells prior to the erasing operation as the erasing control circuit, an unwritten memory cell becomes a negative threshold by executing the erasing operation It can be prevented from having a value voltage.
(3) The above-mentioned memory cell is a MOSFET having a two-layer gate structure of a floating gate and a control gate, and the information charge accumulated in the floating gate is drawn out to the source, drain or well by utilizing a tunnel phenomenon. When the target cell is to be erased, the area occupied by the memory cell is reduced, and the storage capacity can be increased.
(4) In the memory cells constituting the memory array, the source and drain of the entire memory array or a part of the memory cell group are shared, and the electrical erasing operation is performed collectively for each shared memory cell. As a result, the size of the memory cell can be reduced as described above.
(5) By providing an address generation circuit for sequentially selecting memory cells as the erase control circuit, it is possible to perform the pre-write and erase verification for all memory cells.
(6) At the time of verifying the memory cell for controlling the continuation and stop of the erasing, the word line selection potential transmitted to the control gate is set to about 3.5 V corresponding to the lower limit voltage Vccmin lower than the low voltage Vcc. By setting the voltage to such a low voltage Vcv, it is possible to guarantee necessary and sufficient erasing.
(7) As a power supply circuit for generating the word line selection potential to a relatively low voltage Vcv, receives a reference voltage formed by a reference voltage generation circuit and converts it to a desired output voltage based on a gain setting resistor element. By obtaining the output signal from the first operational amplifier circuit and the output terminal of the second operational amplifier circuit in the form of a voltage follower which receives the output signal of the first operational amplifier circuit and forms an output voltage, variations in the element process can be reduced. An arbitrary set desired voltage can be obtained with high accuracy without being affected.
(8) By providing the EEPROM with a data polling function of outputting an internal state such as continuation or stop of an erasing operation to an external device according to an external instruction, memory management by the microprocessor is simplified.
(9) The EEPROM is mounted on a microcomputer, and an erase operation is automatically performed by an internal erase control circuit while electrically disconnected from the microprocessor in accordance with an erase instruction from the microprocessor. Thus, the erasing of the EEPROM can be executed in an on-board state without sacrificing the throughput of the microcomputer system.
(10) A memory array having a matrix of electrically erasable non-volatile storage elements selected by one gate signal line (word line) and one drain signal line (data line) is provided. The erase operation is started according to an external erase instruction. Thereafter, the erase operation is automatically performed irrespective of the external address signal, input data, and control signal. After the erase operation is completed, the external address signal is output. Thus, a semiconductor nonvolatile memory device capable of performing a desired operation by input data and a control signal is obtained.
(11) A memory array having a matrix of electrically erasable non-volatile storage elements selected by one gate signal line (word line) and one drain signal line (data line) is provided. An erasing operation is started according to an external erasing instruction. Thereafter, erasing is automatically performed irrespective of an external address signal, input data, and a control signal. After the erasing is completed, an external address signal is output. Input data, a semiconductor nonvolatile storage device capable of performing a desired operation by a control signal, a microprocessor having a predetermined information processing function, and a system bus connecting the semiconductor nonvolatile storage device and the microprocessor, The semiconductor non-volatile memory device is internally connected to the microprocessor in an electrically disconnected state according to the erase instruction from the microprocessor. And an information processing system that automatically performs an erasing operation by the erasing control circuit.
(12) An electrically erasable and erasable non-volatile memory composed of rows and columns and arranged in a matrix, wherein the erasure is performed by inputting a single pulse for a read cycle period or less. Start, and thereafter, the erase is automatically performed irrespective of the input of the external address, data, and control signal. After the erase is completed, the semiconductor nonvolatile memory device that receives the external address, data, and control signal is obtained. Can be
(13) In an information processing system including an electrically erasable and erasable non-volatile memory which is arranged in a matrix and composed of rows and columns, and which is connected to a microprocessor by a system bus, the information is read in the erasure. Erasure is started by inputting a single pulse for a cycle period or less, and thereafter, erasure is performed automatically regardless of the address, data, and control signals from the system bus. An information processing system including a semiconductor nonvolatile storage device that accepts the information is obtained.
(14) Of the memory cells, the memory cell having the lowest threshold voltage is prevented from having a negative threshold voltage due to the erase operation, and the memory cell having the highest threshold voltage is An internal erase control circuit automatically controls the erase operation of the EEPROM so as to have a threshold voltage that can be read at the lower limit voltage Vccmin by the erase operation.

  Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, the signal FAIL or ER in FIG. 4 may have a function of outputting it to the outside. In this case, in order to prevent an increase in the number of external terminals, it is desirable to output using the data polling function. For example, the data input / output terminals I / O5 and I / O6 are the same circuit as the data output circuit corresponding to the data input / output terminal I / O7 in FIG. It is sufficient to make it correspond. Thus, a signal indicating another internal operation sequence may be output to the outside as needed.

  The erasing of the memory array M-ARY may be such that a source line and a word line are divided, and a memory block to be erased is specified by a combination of the source line and the word line. As a storage transistor constituting a memory cell, a FLOTOX type storage transistor using a tunnel phenomenon for a write operation may be used in addition to a stacked gate MOS transistor used in an EPROM.

  In the above embodiment, one memory transistor shown in FIG. 16 is used as one memory cell. However, one memory transistor shown in FIG. 18 (in this case, substantially two transistors are used) (One storage transistor) may be used as one memory cell. That is, the present invention is particularly suitable for an EEPROM using one storage transistor shown in FIG. 19A as one memory cell. However, the present invention can also be applied to an EEPROM having a memory cell as shown in FIG. 19B (one memory cell is formed of two transistors and is defined by two word lines and one data line). .

  The high voltage Vpp for writing / erasing is not limited to the one using a high voltage supplied from the outside. That is, as long as the current flowing at the time of writing / erasing is small, a voltage boosted from a power supply voltage Vcc by a known charge pump circuit or the like inside the EEPROM may be used. Further, the internal step-up power supply and the external high voltage Vpp may be used in combination.

  In an EEPROM, a circuit portion (CNTR) for controlling normal writing / reading and the like and a circuit portion (LOGC) for controlling an erasing algorithm are configured by any circuit that performs the above-described operation sequence. It may be. That is, in addition to a random logic circuit as shown in FIGS. 3 and 4, and 6 and 7, a programmable logic array (PLA), a microcomputer and software are incorporated, or an asynchronous circuit is used in the above embodiment. May be configured. As described above, the circuit that realizes the above operation sequence can adopt various embodiments.

  Various specific embodiments can be adopted for the specific circuit configuration of the memory array and its peripheral circuits constituting the EEPROM. Further, the EEPROM or the like may be built in a digital semiconductor integrated circuit device such as a microcomputer.

  In the above description, a pair of regions of the storage transistor is defined as a source region and a drain region for ease of description. However, in a storage transistor whose source and drain are determined by the value of an applied voltage. The present invention can be applied by replacing the above-described source region and drain region with one region (node) and the other region (node).

  INDUSTRIAL APPLICABILITY The present invention can be widely used for a storage transistor having a stacked gate structure as used in an EPROM, a semiconductor nonvolatile storage device using a FLOTOX type storage transistor, and an information processing system using the same.

FIG. 1 is a circuit diagram of a memory array unit and a block diagram of a peripheral circuit showing an embodiment of an EEPROM to which the present invention is applied. FIG. 4 is a flowchart illustrating an example of an erasing algorithm according to the present invention. FIG. 4 is a partial circuit diagram of a specific example of an erase control circuit LOGC; FIG. 13 is another partial circuit diagram of a specific example of the erase control circuit LOGC; FIG. 5 is a timing chart for explaining an erasing operation. FIG. 9 is a partial circuit diagram of a specific example of a timing control circuit CNTR. FIG. 14 is another partial circuit diagram of a specific example of the timing control circuit CNTR. FIG. 9 is a characteristic diagram illustrating a relationship between an erasing time and a threshold voltage of a storage transistor. FIG. 4 is a circuit diagram showing one embodiment of a unit circuit of the address buffers XADB and YADB. FIG. 14 is a circuit diagram showing one embodiment of an erase circuit ERC. FIG. 3 is a circuit diagram showing one embodiment of a data output buffer DOB. FIG. 3 is a circuit diagram showing one embodiment of a power supply circuit for generating an erase verify voltage Vcv. FIG. 14 is a circuit diagram of a memory array section showing another embodiment of the EEPROM. FIG. 2 is a block diagram showing an embodiment of a microcomputer system using the EEPROM. FIG. 2 is a block diagram showing a connection between the EEPROM and a microprocessor CPU according to one embodiment. FIG. 3 is a structural cross-sectional view for explaining an example of a conventional memory cell. FIG. 3 is a schematic circuit diagram for explaining the read operation. FIG. 11 is a structural cross-sectional view for explaining another example of the memory cell of the related art. FIG. 2 is a circuit diagram of a memory cell (A) and a conventional memory cell (B) in an EEPROM to which the present invention is applied. 1 is an overall block diagram of an EEPROM according to an embodiment of the present invention. FIG. 4 is a waveform chart showing an example of an external signal of an EEPROM to which the present invention is applied. FIG. 3 is a circuit diagram showing one embodiment of a data input buffer. FIG. 3 is a circuit diagram showing one embodiment of an address decoder. FIG. 9 is a waveform diagram showing erase enable signals (A), (B), (C) and read cycles (D), (E).

Explanation of reference numerals

XADB, YADB: address buffer, XDCR, YDCR: address decoder, UDG: unit decoder circuit, M-ARY: memory array, SA: sense amplifier, DIB, DIB-0 to DIB-7: data input buffer, DOB, DOB- 0 to DOB-7: data output buffer, CNTR: timing control circuit, ERC: erase circuit, LOGC: erase control circuit (internal circuit), N1, N2: CMOS inverter circuit, CS: source line, W1, W2: word line , D1 to Dn data lines, CD common data lines, O1, O2 oscillation circuits, BCS1 to BCS4 binary counter circuits, DP data polling control circuits, CPU microprocessors, ROM read only memories, RAM: random access memory, I / OPORT: input / output port G, EEPROM (FLASH): batch erasure type semiconductor nonvolatile memory device, RGU: 12 V power supply device, LCD: liquid crystal display device, CRT: cathode ray tube, ADDRESS: address bus, DATA: data bus, DEC: decoder circuit, TC ... timing control circuit,
3 ... Drain, 4 ... Floating gate, 5 ... Source, 6 ... Control gate, 7 ... Thin oxide film, 8 ... P-type silicon substrate, 9 ... N-type diffusion layer, 10 ... Low-concentration N-type diffusion layer, 11 ... P-type diffusion layer, 12: selected memory cell, 14: unselected memory cell, 13: selected word line, 15: unselected word line, 16: data line, 17: sense amplifier.

Claims (22)

A bus, a plurality of memories, a processor, and an input / output terminal connected to the bus;
One of the memories is a non-volatile memory, and can receive a plurality of control signals from the processor;
The non-volatile memory includes an erase control circuit for automatically performing an erase operation and an erase verify operation internally until the erase of a plurality of memory cells to be erased in the erase mode is completed, and an address generation circuit for sequentially generating an address signal. Circuit, and a circuit for outputting information on whether or not the erase mode,
When an erase signal included in the control signal is received from the processor, the nonvolatile memory starts the erase mode, and the erase control circuit performs an erase operation on a plurality of memory cells to be erased. Performing the erase verify operation on the memory cell specified by the address generation circuit, and performing the erase operation again when the erase is insufficient,
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The processor can access another memory after sending an erase signal to the nonvolatile memory and before the erase mode in the nonvolatile memory ends, and via the input / output terminal. A device having a non-volatile memory, to which data can be externally input. A bus, a plurality of memories, a processor, and an input / output terminal connected to the bus;
One of the memories is a non-volatile memory, and can receive a plurality of control signals from the processor;
The nonvolatile memory includes: an erase control circuit for automatically performing an erase operation and an erase verify operation repeatedly until the erase of a plurality of memory cells to be erased is completed in an erase mode; and an address for the erase verify operation. An address counter circuit that generates a signal, and a circuit that outputs information as to whether or not the erase mode is in effect,
When an erasing signal included in the control signal is received from the processor, the nonvolatile memory starts the erasing mode, the erasing control circuit initializes an address signal of the address counter circuit, and performs the erasing operation. Thereafter, the erase verify operation is performed on a memory cell designated by an address signal output from the address counter circuit. If the erase operation is insufficient, the erase operation is performed again. Performing an erase verify operation on a memory cell designated by a next address signal output from the address counter circuit by performing an address increment of the address counter circuit;
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The processor can access another memory after sending an erase signal to the nonvolatile memory and before the erase mode in the nonvolatile memory ends, and via the input / output terminal. A device having a non-volatile memory, to which data can be externally input. A bus, a plurality of memories, a processor, and an input / output terminal connected to the bus;
One of the memories is a non-volatile memory, and can receive a plurality of control signals from the processor;
The nonvolatile memory includes an erasing circuit that performs an erasing operation on a plurality of memory cells to be erased, and an address counter circuit that generates an address signal designating some of the plurality of memory cells to be erased. A determination circuit for performing an erase verify operation for determining whether or not the erasure of the memory cell specified by the address signal has been completed; and a circuit for outputting information as to whether or not the memory is in the erase mode,
When receiving the erase signal included in the control signal from the processor, the nonvolatile memory starts an erase mode in which the erase operation and the erase verify operation are automatically performed internally. After the erase operation is performed, the erase verify operation is performed on the memory cell specified by the address signal. When the determination circuit determines that the erase has not been completed, the erase circuit again performs the erase operation. Performing an erase operation, and performing the erase verify operation on a memory cell specified by a next address signal output from the address counter circuit when the determination circuit determines that the erase is completed;
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The processor can access another memory after sending an erase signal to the nonvolatile memory and before the erase mode in the nonvolatile memory ends, and via the input / output terminal. A device having a non-volatile memory, to which data can be externally input.   4. The nonvolatile memory according to claim 1, wherein the processor designates a data polling mode for the nonvolatile memory to determine whether the erasing mode has ended. 5. A device having a volatile memory.   5. The nonvolatile memory according to claim 11, wherein the nonvolatile memory performs a write operation to write data when receiving a write signal included in the control signal from the processor. An apparatus comprising the non-volatile memory according to claim 1. The nonvolatile memory has a plurality of nonvolatile memory cells,
Each non-volatile memory cell has one threshold voltage within a plurality of threshold voltage ranges,
One of the threshold voltage ranges is an erase level at which a threshold voltage of a nonvolatile memory cell is moved by the erase operation;
6. The device having a nonvolatile memory according to claim 5, wherein the other threshold voltage range is a write level at which a threshold voltage of a nonvolatile memory cell is moved by the write operation. A bus, a plurality of memories, a processor, and an input / output terminal connected to the bus;
One of the memories is a non-volatile memory, and can receive a plurality of control signals from the processor;
The non-volatile memory includes an erase control circuit for automatically performing an erase operation and an erase verify operation internally until the erase of a plurality of memory cells to be erased in the erase mode is completed, and an address generation circuit for sequentially generating an address signal. Circuit, and a circuit for outputting information on whether or not the erase mode,
When an erase signal included in the control signal is received from the processor, the nonvolatile memory starts the erase mode, and the erase control circuit performs an erase operation on a plurality of memory cells to be erased. Performing the erase verify operation on the memory cell specified by the address generation circuit, and performing the erase operation again when the erase is insufficient,
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The processor can access another memory after sending an erase signal to the nonvolatile memory and before the erase mode in the nonvolatile memory ends, and via the input / output terminal. A device having a nonvolatile memory, which can output data to the outside. A bus, a plurality of memories, a processor, and an input / output terminal connected to the bus;
One of the memories is a non-volatile memory, and can receive a plurality of control signals from the processor;
The nonvolatile memory includes: an erase control circuit for automatically performing an erase operation and an erase verify operation repeatedly until the erase of a plurality of memory cells to be erased is completed in an erase mode; and an address for the erase verify operation. An address counter circuit that generates a signal, and a circuit that outputs information as to whether or not the erase mode is in effect,
When an erasing signal included in the control signal is received from the processor, the nonvolatile memory starts the erasing mode, the erasing control circuit initializes an address signal of the address counter circuit, and performs the erasing operation. Thereafter, the erase verify operation is performed on a memory cell designated by an address signal output from the address counter circuit. If the erase operation is insufficient, the erase operation is performed again. Performing an erase verify operation on a memory cell designated by a next address signal output from the address counter circuit by performing an address increment of the address counter circuit;
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The processor can access another memory after sending an erase signal to the nonvolatile memory and before the erase mode in the nonvolatile memory ends, and via the input / output terminal. A device having a nonvolatile memory, which can output data to the outside. A bus, a plurality of memories, a processor, and an input / output terminal connected to the bus;
One of the memories is a non-volatile memory, and can receive a plurality of control signals from the processor;
The nonvolatile memory includes an erasing circuit that performs an erasing operation on a plurality of memory cells to be erased, and an address counter circuit that generates an address signal designating some of the plurality of memory cells to be erased. A determination circuit for performing an erase verify operation for determining whether or not the erasure of the memory cell specified by the address signal has been completed; and a circuit for outputting information as to whether or not the memory is in the erase mode,
When receiving the erase signal included in the control signal from the processor, the nonvolatile memory starts an erase mode in which the erase operation and the erase verify operation are automatically performed internally. After the erase operation is performed, the erase verify operation is performed on the memory cell specified by the address signal. When the determination circuit determines that the erase has not been completed, the erase circuit again performs the erase operation. Performing an erase operation, and performing the erase verify operation on a memory cell specified by a next address signal output from the address counter circuit when the determination circuit determines that the erase is completed;
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The processor can access another memory after sending an erase signal to the nonvolatile memory and before the erase mode in the nonvolatile memory ends, and via the input / output terminal. A device having a nonvolatile memory, which can output data to the outside.   10. The nonvolatile memory according to claim 7, wherein the processor designates a data polling mode for the nonvolatile memory to determine whether the erase mode has been completed. A device having a volatile memory.   11. The nonvolatile memory according to claim 7, wherein the nonvolatile memory performs a write operation to write data when receiving a write signal included in the control signal from the processor. An apparatus comprising the non-volatile memory according to claim 1. The nonvolatile memory has a plurality of nonvolatile memory cells,
Each non-volatile memory cell has one threshold voltage within a plurality of threshold voltage ranges,
One of the threshold voltage ranges is an erase level at which a threshold voltage of a nonvolatile memory cell is moved by the erase operation;
12. The device having a nonvolatile memory according to claim 11, wherein the other threshold voltage range is a write level at which a threshold voltage of a nonvolatile memory cell is moved by the write operation. A bus, a processor connected to the bus, a plurality of nonvolatile memories, and input / output terminals;
The processor can instruct the nonvolatile memory to start an erase mode for erasing data stored in the nonvolatile memory,
The non-volatile memory includes an erase control circuit for automatically performing an erase operation and an erase verify operation internally until the erase of a plurality of memory cells to be erased is completed in the erase mode, and an address for sequentially generating an address signal. A generation circuit, and a circuit for outputting information as to whether or not the erase mode is in effect,
When receiving the instruction to start the erasing mode from the processor, the nonvolatile memory performs the erasing operation on the plurality of memory cells to be erased by the erasing control circuit, and then the memory specified by the address generating circuit. Performing the erase verify operation on the cell, performing the erase operation again when the erase is insufficient,
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
An apparatus having a nonvolatile memory, wherein the processor can externally input data via the input / output terminal while the erase mode is being performed in the nonvolatile memory. A bus, a processor connected to the bus, a plurality of nonvolatile memories, and input / output terminals;
The processor can instruct the nonvolatile memory to start an erase mode for erasing data stored in the nonvolatile memory,
The non-volatile memory includes an erase control circuit for automatically performing an erase operation and an erase verify operation repeatedly internally in the erase mode until erasure of a plurality of memory cells to be erased is completed, and an erase control circuit for the erase verify operation. An address counter circuit that generates an address signal, and a circuit that outputs information as to whether or not an erase mode is in effect,
When receiving the instruction to start the erase mode from the processor, the nonvolatile memory initializes the address signal of the address counter circuit by the erase control circuit, and outputs the address signal from the address counter circuit after the erase operation. The erase verify operation is performed on the memory cell specified by the address signal. If the erase is insufficient, the erase operation is performed again. If the erase is completed, the address of the address counter circuit is incremented. Performing the erase verify operation on a memory cell specified by a next address signal output from the address counter circuit;
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
An apparatus having a nonvolatile memory, wherein the processor can externally input data via the input / output terminal while the erase mode is being performed in the nonvolatile memory. A bus, a processor connected to the bus, a plurality of nonvolatile memories, and input / output terminals;
The processor can instruct the nonvolatile memory to start an erase mode for erasing data stored in the nonvolatile memory,
The nonvolatile memory includes an erasing circuit that performs an erasing operation on a plurality of memory cells to be erased, and an address counter circuit that generates an address signal designating some of the plurality of memory cells to be erased. A determination circuit for performing an erase verify operation for determining whether or not the erasure of the memory cell specified by the address signal has been completed; and a circuit for outputting information as to whether or not the memory is in the erase mode,
When receiving the instruction to start the erase mode from the processor, the nonvolatile memory performs the erase operation by the erase circuit, and then performs the erase verify operation on a memory cell specified by the address signal. When it is determined by the determination circuit that the erasure has not been completed, the erasure operation is performed again by the erasure circuit, and when it is determined that the erasure has been completed, an output from the address counter circuit is performed. Performing the erase verify operation on the memory cell specified by the next address signal to be executed,
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
An apparatus having a nonvolatile memory, wherein the processor can externally input data via the input / output terminal while the erase mode is being performed in the nonvolatile memory.   16. The non-volatile memory according to claim 13, wherein the processor designates a data polling mode for the non-volatile memory to determine whether the erasing mode has ended. An apparatus having   17. The nonvolatile memory according to claim 13, wherein the processor is capable of instructing the nonvolatile memory to perform a write operation in order to store data in the nonvolatile memory. An apparatus having A bus, a processor connected to the bus, a plurality of nonvolatile memories, and input / output terminals;
The processor can instruct the nonvolatile memory to start an erase mode for erasing data stored in the nonvolatile memory,
The non-volatile memory includes an erase control circuit for automatically performing an erase operation and an erase verify operation internally until the erase of a plurality of memory cells to be erased is completed in the erase mode, and an address for sequentially generating an address signal. A generation circuit, and a circuit for outputting information as to whether or not the erase mode is in effect,
When receiving the instruction to start the erasing mode from the processor, the nonvolatile memory performs the erasing operation on the plurality of memory cells to be erased by the erasing control circuit, and then the memory specified by the address generating circuit. Performing the erase verify operation on the cell, performing the erase operation again when the erase is insufficient,
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The device having a nonvolatile memory, wherein the processor can output data to the outside via the input / output terminal while the erase mode is being performed in the nonvolatile memory. A bus, a processor connected to the bus, a plurality of nonvolatile memories, and input / output terminals;
The processor can instruct the nonvolatile memory to start an erase mode for erasing data stored in the nonvolatile memory,
The non-volatile memory includes an erase control circuit for automatically performing an erase operation and an erase verify operation repeatedly internally in the erase mode until erasure of a plurality of memory cells to be erased is completed, and an erase control circuit for the erase verify operation. An address counter circuit that generates an address signal, and a circuit that outputs information as to whether or not the erase mode is in effect,
When receiving the instruction to start the erase mode from the processor, the nonvolatile memory initializes the address signal of the address counter circuit by the erase control circuit, and outputs the address signal from the address counter circuit after the erase operation. The erase verify operation is performed on the memory cell specified by the address signal. If the erase is insufficient, the erase operation is performed again. If the erase is completed, the address of the address counter circuit is incremented. Performing the erase verify operation on a memory cell specified by a next address signal output from the address counter circuit;
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The device having a nonvolatile memory, wherein the processor can output data to the outside via the input / output terminal while the erase mode is being performed in the nonvolatile memory. A bus, a processor connected to the bus, a plurality of nonvolatile memories, and input / output terminals;
The processor can instruct the nonvolatile memory to start an erase mode for erasing data stored in the nonvolatile memory,
The nonvolatile memory includes an erasing circuit that performs an erasing operation on a plurality of memory cells to be erased, and an address counter circuit that generates an address signal designating some of the plurality of memory cells to be erased. A determination circuit for performing an erase verify operation for determining whether or not the erasure of the memory cell specified by the address signal has been completed; and a circuit for outputting information as to whether or not the memory is in the erase mode,
When receiving the instruction to start the erase mode from the processor, the nonvolatile memory performs the erase operation by the erase circuit, and then performs the erase verify operation on a memory cell specified by the address signal. When it is determined by the determination circuit that the erasure has not been completed, the erasure operation is performed again by the erasure circuit, and when it is determined that the erasure has been completed, an output from the address counter circuit is performed. Performing the erase verify operation on the memory cell specified by the next address signal to be executed,
The processor, after sending an erase signal to the nonvolatile memory, determines whether the erase mode has ended based on the information output from the circuit to the bus,
The device having a nonvolatile memory, wherein the processor can output data to the outside via the input / output terminal while the erase mode is being performed in the nonvolatile memory.   21. The non-volatile memory according to claim 18, wherein the processor designates a data polling mode for the non-volatile memory to determine whether the erasing mode has ended. An apparatus having 22. The nonvolatile memory according to claim 18, wherein the processor is capable of instructing the nonvolatile memory to perform a write operation in order to store data in the nonvolatile memory. An apparatus having

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