JP3537989B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable and erasable nonvolatile semiconductor memory device, and more particularly, to a nonvolatile semiconductor memory device having a booster circuit therein and a high voltage generated by the booster circuit. Write information to memory cells using
The present invention relates to a nonvolatile semiconductor memory device that performs erasing.

[0002]

2. Description of the Related Art Normally, electrical writing / erasing operations on memory cells performed in a nonvolatile semiconductor memory device include:
A higher potential (about 12 V) is required as compared with a power supply potential (generally about 5 V). Although there is a method of directly applying the high potential from the outside, recently, the high potential is often generated by boosting the power potential from a power supply potential by a boosting circuit inside the semiconductor memory device.

FIG. 2 shows a conventional configuration of a non-volatile semiconductor memory device having a booster circuit therein, focusing on the booster circuit. As shown in the figure, a conventional nonvolatile semiconductor memory device having a booster circuit therein has a booster circuit 23, a terminal potential switching circuit 24 for switching a terminal potential applied to a memory cell, and an output from the terminal potential switching circuit 24. Address decoder circuit 2 for applying the applied potential V to the terminal of the memory cell selected by address signal A.
5. An interface circuit 21 connected to a memory cell 26 for storing information and an internal control circuit 22 and having a function of recognizing a command input from the outside and outputting an internal state to the outside, and control from the interface circuit 21 The internal control circuit 22 has a function of outputting a control signal (including a control signal (not shown)) for writing or erasing to each circuit (including a circuit (not shown)) in accordance with a sequence preset by a signal. . In this case, the external power supply supplied to the booster circuit 23 and the external power supply connected to other internal circuits (including circuits not shown) are often separated from the external terminals. Because, when the booster circuit starts operating,
This is because a current is rapidly supplied from the external power supply to the booster circuit through the external terminal, and a temporary drop in the power supply potential may cause a malfunction inside the circuit. This power supply dedicated to the booster circuit is called V _PP (usually the same potential as the power supply potential V _CC ).

When a write command or an erase command is given to a nonvolatile semiconductor memory device, a write or erase operation starts. When the interface circuit 21 recognizes that the input command is a write or erase command, the interface circuit 21 causes the internal control circuit 22 to operate the internal circuit based on the write or erase sequence. Outputs control signal. The internal control circuit 22 having received this signal outputs a control signal to the boosting circuit 23 to start the boosting operation. As a result, the booster circuit 23 starts generating a high potential required for a write or erase operation from V _PP which is a power supply dedicated to the booster circuit.

On the other hand, the address decoder circuit 25 becomes an object of writing or erasing from among the memory cells 26 by an address signal A generated from the address of a memory cell to be written or erased inputted from the outside. Select a memory cell. At this time, a plurality of memory cells may be selected. Further, the terminal potential switching circuit 2
4 supplies the high potential generated by the booster circuit 23 to the address decoder circuit 25 in order to apply a desired potential to the terminal of the selected memory cell. The terminal potential switching circuit 24 also receives a control signal from the internal control circuit 22 and responds to the control signal by the address decoder circuit 2.
5 can be switched.

The high potential generated by the booster circuit 23 is supplied to the terminal of the selected memory cell through the terminal potential switching circuit 24 and the address decoder circuit 25, so that the selected memory cell is written or erased. Mode. The writing or erasing mode indicates a state in which a terminal potential of a memory cell becomes a potential necessary for writing or erasing, or a necessary current is supplied to enable writing or erasing.

Here, it is assumed that V _PP, which is an external power supply dedicated to the booster circuit, causes an extremely low potential or is cut off due to an unexpected situation during the writing or erasing operation.
These correspond to the case where the user disconnects the external power supply or interrupts the power supply of the system in which the nonvolatile semiconductor memory device is mounted during the writing or erasing operation. When a certain memory cell is in the writing or erasing operation mode and the terminal potential applied to the memory cell is extremely lowered due to these causes, the memory cell in the writing or erasing mode is normally written or erased. Operation cannot continue. The same applies to a case where the output potential of the booster circuit is lower than a desired potential, such as when the booster circuit does not operate normally due to some problem. As described above, in order to prevent erroneous writing or erroneous erasing caused by the above-mentioned reasons, to protect internal data, to prevent problems on the system side due to a delay in a writing or erasing operation time, and to improve system reliability. Cannot continue the write or erase operation in that state.

In order to solve the above-mentioned problem, the output potential of the booster circuit is monitored while the booster circuit is operating, and when the output potential is lower than a predetermined potential, writing or erasing operation to the memory cell is performed. What is necessary is just to add means to interrupt / prohibit.

Next, as a second conventional technique, Japanese Patent Laid-Open No. 7-500 is provided with means for interrupting and inhibiting the writing and erasing operations when the output potential of the booster circuit is lower than a predetermined potential.
FIG. 3 shows a configuration of a nonvolatile semiconductor memory device described in Japanese Patent Publication No. 97-97. In this example, the output potential detection circuit 37 connected to the booster circuit 33 constantly monitors the output potential of the booster circuit 33. If the output potential does not reach a predetermined potential, the terminal potential switching / cutoff circuit 34 The supply of the output potential of the booster circuit 33 to the address decoder circuit 35 is cut off. In the figure, 31 is an interface circuit, 32 is an internal control circuit, and 36 is a memory cell. According to this circuit, when the output potential of the booster circuit does not reach the predetermined potential, the supply of the potential to the address decoder circuit is cut off to prevent problems such as erroneous writing to the memory cell. Can be.

[0010]

Generally, a booster circuit occupies a large area on a chip because it has a large number of capacitance components. Since reduction of the chip area contributes to low cost and high yield, it is required to reduce the occupied area in the booster circuit as much as possible. For this reason, the electric characteristics such as the current supply capability of the booster circuit usually do not have much margin.
Further, since the booster circuit is designed to maintain its output at a desired potential, a circuit for changing the frequency of the internal clock is incorporated so that the current supply capability becomes an appropriate value each time. Often. The internal operation of these booster circuits has been clarified by various known materials. Therefore, when the load applied to the output of the booster circuit changes due to the switching operation of the internal circuit or the like, the booster circuit tries to change the state so as to have an appropriate current supply capability each time. Therefore, for example, when the load suddenly increases, the output potential of the booster circuit may instantaneously become low due to the delay time until the booster circuit switches to a current supply capability suitable for the load. . The instantaneous occurrence of the low potential state is particularly likely to occur when there is no margin in the current supply capacity of the booster circuit. This potential drop is not continuous due to the interruption of the power supply as described above, but is only an instantaneous one. This instantaneous decrease in the output potential is caused by switching of the internal circuit at the switching timing of operation such as switching from a write operation to a memory cell to a write verify operation in a series of write or erase procedures. This is because a DC path (a path between the output of the booster circuit and the ground potential) is instantaneously formed due to fluctuations and switching of the internal circuit. Since these do not affect the write / erase operation, there is no need to interrupt or stop the write / erase.

However, according to the above-mentioned second prior art, even when an instantaneous drop in the boosted potential occurs, the supply of the booster circuit output is cut off by the terminal potential switching / cutoff circuit 34. In this case, each time the instantaneous drop of the boosted potential occurs, the write / erase operation is interrupted, and the write / erase time is increased. Further, every time the output potential of the booster circuit is cut off, an extra current is consumed in the circuit to which the high potential has been supplied and the booster circuit.

When the output potential from the booster circuit exceeds a predetermined level (for example, 12 V), an unnecessarily high potential is applied to the word line during the write operation, and the selected cell during the write operation is In the case of (1), there is a possibility that over-programming may occur. In addition, for a non-selected memory cell connected to a selected word line, a gate disturb occurs, and a problem arises in that electrons are injected into a floating gate by a tunnel current. Furthermore, the memory cell may be permanently damaged by an unnecessarily high potential. Therefore, in such a case as well, it is necessary to cut off the supply of the booster circuit output. However, when the application of the high potential equal to or higher than the predetermined level is completed in a short time, there is no need to cut off the supply.

The present invention has been made in view of such circumstances, and has as its object to respond to the fact that the output potential of the booster circuit has become lower than or equal to a predetermined potential for a predetermined period or more. As described above, by stopping the write / erase operation in response to the potential becoming higher than the predetermined potential,
Without increasing the write / erase time and current consumption,
It is to improve the reliability of a nonvolatile semiconductor memory device.

[0014]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device having a booster circuit therein, and using a high voltage generated by the booster circuit to write information into a memory cell. In the nonvolatile semiconductor memory device for erasing, the output potential of the booster circuit, which is connected to the output of the booster circuit, becomes lower than a predetermined first potential, and / or Detecting that the potential has become higher than the predetermined second potential, and outputting a detection signal during that period; and outputting the detection signal from the output potential detection circuit to a predetermined predetermined potential. A control signal output circuit for detecting that the operation has continued for more than a time and outputting a control signal; and a function of having the control signal as an input and stopping the operation of writing / erasing information to / from the memory cell by the control signal. It is characterized in that comprising providing a control circuit.

According to a second aspect of the present invention, there is provided the nonvolatile semiconductor memory device according to the first aspect, wherein the predetermined first potential and / or the predetermined second potential are different from each other. It is characterized by being variable.

Further, a nonvolatile semiconductor memory device according to the present invention according to claim 3 is the nonvolatile semiconductor memory device according to claim 1 or 2, wherein the predetermined time is variable. It is.

According to such a nonvolatile semiconductor memory device of the present invention, the output of the booster circuit becomes lower than the predetermined potential for a predetermined period or more, or in response to a predetermined period or more.
The writing / erasing operation is stopped when the potential becomes higher than the predetermined potential.

[0018]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory device according to one embodiment of the present invention.

The nonvolatile semiconductor memory device according to the present embodiment
A booster circuit 13, a terminal potential switching circuit 14 for switching a terminal potential applied to a memory cell, and a potential V output from the terminal potential switching circuit 14 as an address signal A
Address decoder circuit 15 to be applied to the terminal of the memory cell selected by the above, memory cell 1 for storing information
6. An interface circuit 11, which is connected to the internal control circuit 12 and has a function of recognizing a command input from the outside and outputting an internal state to the outside. Each of the interface circuits 11 according to a sequence set in advance by a control signal from the interface circuit 11. Internal control circuit 1 having a function of outputting a control signal (including a control signal not shown) for writing or erasing to a circuit (including a circuit not shown)
2 and so on.

In this embodiment, in addition to the above configuration,
An output potential detection circuit 17 connected to the booster circuit 13 and outputting a detection signal D when the output potential of the booster circuit 13 is lower than a predetermined potential is provided. While the booster circuit 13 is operating, the high potential output from the booster circuit is constantly monitored by the output potential detection circuit 17.

FIG. 4 shows an example of the output potential detecting circuit 17. The potential of the input a of the output potential detection circuit gradually decreases from the high potential, and the potential of the input a−the potential of the input a × (the resistance component 1
When the value of (resistance value of resistance component 1) + (resistance value of resistance component 2) becomes equal to or less than the threshold value of the P-channel MOS transistor, the P-channel MOS transistor transitions from the on state to the off state, and the inverter Of the input d starts to drop. When the potential drops below the threshold value of the inverter, the output b of the output potential detection circuit 17 goes to the “H” level, indicating that the potential of the input a has fallen below the set potential. The “H” level indicates the same level as the power supply potential, and the “L” level indicates the same level as the ground potential. At this time, the output b becomes the “H” level, which is determined by the resistance values of the resistance components 1, 2, and 3, the threshold value of the P-channel MOS transistor, and the threshold value of the inverter.
The potential of the input a is called a low potential detection level.

The configuration of the output potential detecting circuit 17 is not limited to the configuration shown in FIG. Further, the resistance component may be realized by any element. For example, it can be formed by a diffusion resistor, a polysilicon resistor, a transistor, or the like.

Further, the resistance value of the resistance component may be variable, and the low potential detection level may be set to a plurality of values. With such a configuration, an optimum detection level can be set according to the power supply potential or the use environment temperature.

In the present embodiment, a detection signal D, which is an output of the output potential detection circuit 17, is input and activated only when the detection signal D is output for a period equal to or longer than a preset period. A control signal output circuit 18 for outputting a control signal C to the internal control circuit 12 is provided. An example of the control signal output circuit 18 is shown in FIG. As shown in the figure, the control signal output circuit includes a delay circuit and an AND gate. Although the delay circuit may be configured in any manner, for example, the delay circuit can be configured by a plurality of (even) inverters connected in cascade.

A detection signal D output from the output potential detection circuit 17 is input to an input e. The delay time realized by the delay circuit is called a low potential detection time. A detection signal D having an “H” level period longer than the low potential detection time
Only when is input, both e and g become "H" level, and the output f (control signal C) becomes "H" level. Accordingly, the output f is not activated by the pulse-shaped input e having a short potential detection time or less due to an instantaneous potential drop, and the internal control circuit 12 informs the internal control circuit 12 that the output of the booster circuit 13 is in the low potential state. Don't tell.

The control signal output circuit 18 may be under clock control. FIG. 6 shows another example of such a configuration. In this case, the control signal output circuit outputs a plurality of (four in the figure) clocks (Clocks).
It is composed of a control latch circuit and an AND gate. FIG. 13 shows the configuration of the latch circuit. Each latch circuit receives the input level (“H”) at the falling edge of the clock signal Clock.
Level or “L” level) and store the clock signal Cl
While ock is at the "L" level, the stored level is output regardless of the input level. Clock signal Cl
During the period when ock is at “H” level, the same level as the input level is output. As the clock signal Clock, a rectangular wave having a fixed period is input. When the internal control circuit performs clock control, an internal clock signal used in the internal control circuit may be connected.

When the input e of the control signal output circuit 18 transitions to the "H" level, the "H" level is propagated between the latch circuits in accordance with the phase of the clock signal. The output g of the last-stage latch circuit becomes “H level”, and at that time,
Only when the input e is at the "H" level, the output f (control signal C) becomes the "H" level and informs the internal control circuit that the output of the booster circuit is lower than the low potential detection level. . When a pulse-like “H” level signal shorter than (cycle of clock signal Clock × number of latch circuit stages) is input to input e of the control signal output circuit, output g of the last-stage latch circuit becomes “H” level. At this point, since the input e of the control signal output circuit has returned to the “L” level, the output f of the control signal output circuit does not go to the “H” level, and the internal control circuit includes It does not signal that the output potential is lower than the low potential detection level. As described above, when the pulse-like detection signal D having a width equal to or less than (cycle of the clock signal Clock × number of latch circuits) is supplied to the input e, this signal does not affect the writing or erasing operation. Judge that this is due to an instantaneous potential drop, and do not transmit it to the internal control circuit.
The time determined by the cycle of the clock signal Clock and the number of latch circuit stages, that is, (the clock signal Clock
(cycle of k × number of latch circuit stages) is referred to as a low potential detection time.

The configuration of the control signal output circuit is shown in FIGS.
The configuration is not limited to this. For example, as shown in FIG. 7, a circuit configuration is also possible in which the number of stages of the latch circuit is changed by another control signal Select to set the low potential detection time to a plurality of values. In this example, one of the four inputs of the 4: 1 multiplexer circuit can be selected by the 2-bit control signal Select. Control signal Sel
Since the number of effective latch circuits can be changed by ect, it is possible to optimize the low potential detection time depending on operating conditions such as a power supply voltage.

The control signal C output from the control signal output circuit 18 is input to the internal control circuit 12, and the internal control circuit 12 sends a control signal for stopping the writing operation or the erasing operation to each circuit based on the control signal. Output.

Next, the operation of this embodiment will be described.

When the interface circuit 11 receives a write or erase command from the outside, the nonvolatile semiconductor memory device of this embodiment starts a write or erase operation. When the interface circuit 11 recognizes that the input command is a write or erase command, the interface circuit 11 controls the internal control circuit 12 to operate the internal circuit based on the sequence of the write or erase operation. Send a signal.
Upon receiving this, the internal control circuit 12 operates the booster circuit 1
In order to generate a high potential required for the writing or erasing operation, a control signal is sent to 3 to start the boosting operation. As a result, the booster circuit 13 in an operable state
Starts the generation of the high potential required for the writing or erasing operation from V _PP which is the power supply dedicated to the booster circuit.

Upon receiving the control signal, the booster circuit 13 that has started generating a high potential, after a booster circuit setup time,
The output is set to a potential at which a write or erase operation can be performed.
When the output reaches a writable or erasable potential, the internal control circuit 12 sends a control signal (including a not-shown circuit) to a circuit (including a not-shown circuit) related to writing or erasing based on a preset procedure. ) To execute a write or erase operation. An example of the procedure of the write operation will be described with reference to FIG. Write operations include write preparation (including the booster circuit setup time), write, verify after write, rewrite,
Post-processing operations are required. Preparation for writing includes setting up a booster circuit and selecting a memory cell based on an input address. The writing is an operation of setting a selected memory cell to a writing operation mode and actually writing data to the memory cell. Verify after writing
This is an operation for confirming whether or not writing to a memory cell has been performed normally. Rewriting is performed based on the result of post-write verification, and is an operation of writing again to a memory cell that has not been correctly written.
The post-processing is an operation of stopping the boosting operation of the boosting circuit, notifying the outside that the writing operation has been normally completed, and the like.

During the execution of the above-described write operation procedure, the internal control circuit 1 is switched when each mode is switched.
The states of the circuits related to the write operation change at the same time by the control signal from the control circuit 2. At this time, the output of the booster circuit 13 is instantaneously pulled to the ground potential or the load component value applied to the output changes greatly due to the state transition (switching) inside the terminal potential switching circuit 14. Booster circuit 1
3 attempts to change the current supply capability according to the change in the output situation, but if the reaction time is not sufficiently fast,
The potential of the output of the booster circuit 13 may momentarily become low.

FIG. 9 shows the procedure of the write operation and the booster circuit 1.
3 shows a model of the relationship between the output of FIG. As shown in FIG. 9, in the procedure of the write operation, the output of the booster circuit may instantaneously become low potential in synchronization with the switching timing of each mode.
Therefore, it is not notified to the internal control circuit 12 that the output of the booster circuit has become lower than the low potential detection level. Therefore, the write operation can be performed without interruption or temporary stop.

If the potential of the output of the booster circuit 13 falls below the low-potential detection level for a period equal to or longer than the low-potential detection time due to, for example, a decrease in the _VPP potential, which is a power supply dedicated to the booster circuit, the control is performed. The control signal C is output from the signal output circuit 18 and the fact is transmitted to the internal control circuit 12.

FIG. 10 shows the output of the booster circuit 13 at that time,
Detection signal D, control signal C to internal control circuit 12
3 shows an example of a waveform diagram of FIG. The potential of the output of the booster circuit 13 is
After a high potential has been reached after the set-up time, two instantaneous potential drops are seen in FIG. As mentioned above,
When the potential drops momentarily, the control signal C to the internal control circuit 12 does not go to the “H” level. Thereafter, when the potential of the output of the booster circuit 13 becomes lower than the low potential detection level for a period longer than the low potential detection time, it is determined that further writing operation cannot be continued, and the control signal C becomes "H" level. , To the internal control circuit 12 to stop the write operation. Upon receiving the control signal C, the internal control circuit 12 stops the boosting operation of the boosting circuit 13 and suspends the writing operation in each circuit (including a circuit (not shown)) related to the writing operation so that the normal operation (reset state) is performed. ). Further, the internal control circuit 12 having received the control signal C further notifies the outside through the interface circuit 11 that the write operation has been abnormally terminated. Interface circuit 11
Can notify an abnormal termination of writing to the outside through a specific pin, an internal register, or the like.

The write operation has been described as an example, but the same applies to the erase operation.

In the above embodiment, the writing or erasing operation is stopped when the output of the booster circuit falls below the predetermined level for a predetermined period or more. However, the output of the booster circuit is higher than necessary. In order to eliminate the inconvenience caused by the continuation of the state, a configuration in which a high potential detection circuit is provided instead of the low potential detection circuit is also effective.

FIG. 11 shows an example of the high potential detection circuit.
The potential of the input a rises from a predetermined high potential, and the value of the potential of the input a × (the resistance value of the resistance component 1) / (the resistance value of the resistance component 1 + the resistance value of the resistance component 2) becomes an N-channel MOS transistor. , The N-channel MOS transistor transitions from the off state to the on state, and the potential of the input d of the inverter starts to decrease. When the potential drops below the threshold value of the inverter, the output b goes to the “H” level, indicating that the potential of the input a has risen above the set potential. The “H” level indicates the same level as the power supply potential, and the “L” level indicates the same level as the ground potential. At this time, the resistance values of the resistance components 1, 2 and 3 and the N-channel M
The input a is determined by the threshold value of the OS transistor and the threshold value of the inverter.
Is referred to as a high potential detection level.

The configuration of the high potential detection circuit is not limited to the configuration shown in FIG. Further, the resistance component may be realized by any element. For example, it can be formed by a diffusion resistor, a polysilicon resistor, a transistor, or the like.

Further, the resistance value of the resistance component may be variable, and the high potential detection level may be set to a plurality of values. With such a configuration, an optimum detection level can be set according to the power supply potential or the use environment temperature.

Further, both the low potential detection circuit and the high potential detection circuit are provided so that the output of the booster circuit is maintained for a predetermined period or more.
The writing and erasing operations may be stopped when the voltage exceeds the high-potential detection level or when the voltage drops below the low-potential detection level. FIG. 12 shows the configuration in this case. As shown in the figure, the output potential detection circuit
It includes a high potential detection circuit and a low potential detection circuit to which the output of the booster circuit is applied in parallel, and uses the OR signal of the outputs of the two potential detection circuits as the output signal (detection signal D) of the output potential detection circuit.

[0044]

As described in detail above, the nonvolatile semiconductor memory device of the present invention has a booster circuit therein, and uses the high voltage generated by the booster circuit to write / write information to / from a memory cell. In the nonvolatile semiconductor memory device for erasing, the output potential of the booster circuit is connected to the output of the booster circuit, and is lower than a predetermined first potential, and / or Detecting that the potential has become higher than the predetermined second potential, and during that period, an output potential detection circuit for outputting a detection signal, and outputting the detection signal from the output potential detection circuit for a predetermined time. A control signal output circuit that detects the continuation of the above and outputs a control signal, and has a function of having the control signal as an input and stopping the operation of writing / erasing information to / from the memory cell by the control signal According to the nonvolatile semiconductor memory device of the present invention, the instantaneous potential drop or the instantaneous potential increase of the high potential output from the booster circuit is provided. In some cases, the control signal output circuit is not activated, and the control signal output circuit is activated only when a continuous potential drop and potential rise occur. Accordingly, unnecessary writing and erasing operations are not interrupted by an instantaneous potential drop or potential rise that does not affect the writing and erasing operations. According to the nonvolatile semiconductor memory device of the present invention, It is possible to provide a highly reliable nonvolatile semiconductor memory device without increasing the erasing time and current consumption.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional nonvolatile semiconductor memory device.

FIG. 3 is a configuration diagram of another conventional nonvolatile semiconductor memory device.

FIG. 4 is a configuration diagram of an output potential detection circuit shown in FIG. 1;

FIG. 5 is a configuration diagram of the control signal output circuit.

FIG. 6 is a configuration diagram of another example of the control signal output circuit.

FIG. 7 is a configuration diagram of still another example of the control signal output circuit.

FIG. 8 is a flowchart illustrating an example of a procedure of a write operation.

FIG. 9 is a diagram illustrating a relationship between a write operation procedure and an output potential of a booster circuit.

FIG. 10 is a waveform chart showing an example of an output of a booster circuit, a detection signal, and a control signal to an internal control circuit.

FIG. 11 is a configuration diagram of an example of a high potential detection circuit.

FIG. 12 is a configuration diagram of an output potential detection circuit including a high potential detection circuit and a low potential detection circuit.

FIG. 13 is a configuration diagram of a latch circuit shown in FIG. 6;

[Explanation of symbols] 11 Interface circuit 12 Internal control circuit 13 Boost circuit 14-terminal potential switching circuit 15 Address decoder circuit 16 memory cells 17 Output potential detection circuit 18 Control signal output circuit D detection signal C control signal

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-109291 (JP, A) JP-A-7-211087 (JP, A) JP-A-7-50097 (JP, A) JP-A-6-110 332588 (JP, A) JP-A-5-14158 (JP, A) JP-A-5-108503 (JP, A) JP-A-5-35614 (JP, A) JP-A-5-61572 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 16/00-16/34

Claims (3)

(57) [Claims] 1. A nonvolatile semiconductor memory device having a booster circuit therein and writing / erasing information to / from a memory cell using a high voltage generated by the booster circuit. And detecting that the output potential of the booster circuit is lower than a predetermined first potential and / or higher than a predetermined second potential. An output potential detection circuit that outputs a detection signal, and a control signal output circuit that detects that the output of the detection signal from the output potential detection circuit has continued for a predetermined time or more and outputs a control signal. A control circuit having the control signal as an input, and having a function of stopping an operation of writing / erasing information to / from a memory cell in accordance with the control signal. . 2. The non-volatile semiconductor memory device according to claim 1, wherein the predetermined first potential and / or the predetermined second potential are different.
A nonvolatile semiconductor memory device having a variable potential. 3. The nonvolatile semiconductor memory device according to claim 1, wherein said predetermined time is variable.