JP2725560B2 - Nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device, and more particularly, to an electrically erasable and writable nonvolatile semiconductor memory device (EEPROM).

[0002]

2. Description of the Related Art Generally, in a nonvolatile semiconductor memory device,
A high voltage (V
_PP ), but usually provided by an externally supplied power supply voltage (V _CC )
Is boosted by a charge pump circuit to generate a high boosted voltage (generally, V _PP = 20 V with respect to V _CC = 5 V) and supplies it to the memory cell and its peripheral circuits.

FIG. 8 is a block diagram mainly showing an erase / write system circuit of a conventional nonvolatile semiconductor memory device.
In FIG. 1, reference numeral 10 denotes a control circuit block which receives a clock CLK and various control signals CNL from the outside, and controls various operations including an erase / write operation and a read operation of the device. An erasing / writing timing generating circuit controlled by the circuit block 10 to generate a timing signal therefor, 12 is a pulse generator, 13 is a charge pump circuit that generates a boosted voltage by a pulse of the pulse generator, and 15 is an external device. The register receives and holds the address signal AD and the data DA, and transmits the word / address pointer 16 and the memory cell array 17.

When the control circuit block 10 starts an erase / write operation, an erase / write timing generation circuit 11 generates an erase / write timing, and a charge pump circuit 13 generates a boosted voltage V _PP . During the erase / write timing, the boosted voltage V _PP is applied to the word address pointer 1
The memory cell at the address designated by the register 15 is erased, and the cell at the address is rewritten with the data designated by the register 15.

[0005]

In the conventional nonvolatile semiconductor memory device described above, the boosted voltage V _PP of the charge pump circuit is supplied to the memory cells regardless of the boosted level. Thus, the boosted voltage V _PP of the charge pump circuit can be obtained at a stable level in a device with a power supply voltage of 5 V, but can be boosted in a low voltage device with a power supply voltage of 3.3 V or less. Shortage may occur. When the write operation is performed with the boosted voltage V _PP that has not reached the sufficient boost level for some reason, the write level becomes shallower than when erase / write is performed with the boost voltage V _PP of a sufficient level, Alternatively, no erasing / writing is performed. When the writing level is low, erroneous writing or omission of writing data is caused. When erasing / writing is not performed, data written so far remains as it is. Which data has been erroneously written or not written cannot be monitored externally unless read out and compared with write data each time erasure or writing is performed.

Therefore, an object of the present invention is to firstly prevent erasing / writing from being performed under an insufficient boosted voltage V _PP to prevent a writing malfunction caused by a voltage shortage. Secondly, it is possible to externally monitor that the boosted voltage is insufficient for erasing / writing, thereby improving the operation reliability of the nonvolatile semiconductor memory device. Things.

[0007]

According to the present invention, there is provided a memory cell array in which a plurality of memory cells are arranged, and various kinds of operations including erasing / writing and reading operations for the memory cells. a control circuit block for controlling the operation (10), the control and circuit timing generator circuit being controlled by a block generating a signal indicative of the timing of the erasing and writing to the memory cell (11), wherein the erase-write mode booster circuit power supply voltage supplied from the outside in response to an instruction from the control block by boosting generating boosted voltage for erasing and writing (13), a voltage detection circuit for detecting the boosted voltage; and (Di + Qp + Qp + in 18), erase ·writing
A switching circuit (SW; 19) for interrupting transmission of the boosted voltage to the memory cell when the boosted voltage detected by the voltage detection circuit in a mode is equal to or less than a predetermined value. A semiconductor storage device is provided. Preferably, the nonvolatile semiconductor memory device is configured so that an output signal of the voltage detection circuit can be monitored from outside.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. In the present embodiment, a clock CLK and various control signals CNL are supplied from the outside, a control circuit block 10 that supplies control signals to various parts in the device, and a control signal of the control circuit block 10 are supplied. , An erase / write timing generation circuit 11 for generating a signal for instructing, a pulse generator 12 for receiving a signal from the control circuit block 10 to generate a pulse, and receiving a pulse from the pulse generator to generate a boosted voltage. Charge pump circuit 13 to generate and charge pump circuit 13
Boosted voltage V _PP is supplied from the boosted voltage clamping transfer circuit 14 for controlling the external transmission of the clamping voltage while clamping the boosted voltage, the memory cell array 17 which nonvolatile memory cells are plural arranged A word / address pointer 16 for selecting a memory cell at a specific address and transmitting the boosted voltage supplied by the boosted voltage clamp / transmission circuit 14, data DA and an address signal AD are input to the memory cell array 1.
7 and a register 15 for transmitting to the word address pointer 16.

Next, the operation of this embodiment will be described. When the output signal of the control circuit block 10 enters the erase / write state, the timing generation circuit 11 supplies the erase / write timing to the word / address pointer 16, and the charge pump circuit 13 applies the boosted voltage V _PP to the boosted voltage clamp circuit. It is supplied to the transmission circuit 14. The boost voltage clamp / transmission circuit 14 supplies the clamped boost voltage V _PP to the word address pointer 16 only when the boost voltage reaches a predetermined voltage. Word address pointer 1
6 selects the memory cell at the address specified by the register 15 and transmits the boosted voltage V _PP . As a result, erasing is performed, and subsequently the data held in the register 15 is written.

FIG. 2 shows a circuit example of the boosted voltage clamp / transmission circuit 14, and FIG. Boosted input voltage V _I is the diode Di and a two-stage p-channel MOS transistor Qp, is clamped by Qp.
The clamped boosted voltage V _PP is applied to the switching circuit SW
Is output as an output voltage V _O through The conduction and non-conduction of the switching circuit SW is controlled by the inverter In. That is, when the output of the inverter In is low, the switching circuit SW conducts, and when high, the switching circuit SW is shut off.

Assuming that the reverse withstand voltage of the diode Di is V _BD and the threshold voltage of the two stages of the transistor Qp is V _TP , the clamp voltage V _CP becomes V _CP = V _BD + V _TP , and the boosted voltage V _PP is this voltage. Clamped. The voltage on the anode side of the diode Di is V1 and the voltage on the output side of the inverter In is V2.
And As shown in FIG. 3, when the input voltage V _I is less than the reverse breakdown voltage of the diode _{Di (V I <V BD)} , the voltage V1 is 0V, therefore, the voltage V2 is at a high level. Therefore, at this time, the switching circuit SW is in the cutoff state. Reverse voltage V of the input voltage V _I is the diode Di
Exceeding the _BD, the diode conducts, the voltage V1 junction current rises diode with increasing input voltage V _I rises. When the voltage V1 exceeds the threshold voltage V _TINV of the inverter In, the voltage V2 becomes low level, and the switching circuit SW starts conducting. Voltage V1 is further increased input voltage V _I exceeds V _BD + V _TP is fixed to the threshold voltage V _TP of the transistor Qp.

As described above, the output voltage of the charge pump circuit 13, that is, the boosted input voltage V _I is less than V _I <
When V _BD + V _TINV , the output voltage of the transmission circuit 14 is
0 V, and no erasing / writing of the memory cell is performed. Input voltage V _I is, V _I> V _BD + V _TINV become the conducting switching circuit SW, clamped boosted voltage V
_PP is output as the output voltage V _O of the transmission circuit 14, and the erasing / writing of the memory cell is reliably performed.

FIG. 4 is a block diagram showing a second embodiment of the present invention. This embodiment is different from the first embodiment in that the boosted voltage clamp / transmission circuit 14 in the first embodiment is different from the first embodiment.
Is eliminated, and a boosted voltage detection circuit 18 for detecting a boosted voltage of the charge pump circuit 13 and a cutoff circuit 19 for transmitting / cutting off the output voltage of the charge pump circuit 13 are used instead. That is, in the present embodiment, when the boosted voltage has not reached the predetermined value, the boosted voltage detection circuit 18 outputs a signal of the first level, whereby the cutoff circuit 19 causes the word / address pointer of the boosted voltage to output. When the boosted voltage exceeds a predetermined value, the boosted voltage detection circuit 18 outputs a signal of the second level, thereby turning on the cutoff circuit 19, and the output of the charge pump circuit. Is transmitted to the word / address pointer 16. With this configuration, the present embodiment can also achieve the same effects as the previous embodiment.

FIG. 5 is a block diagram showing a third embodiment of the present invention. This embodiment differs from the second embodiment in that the output signal of the boosted voltage detection circuit 18 is also applied to the erase / write timing generation circuit 11 as a control signal. That is, in the present embodiment, when the boosted voltage has not reached the predetermined value, the operation of the timing generation circuit 11 is stopped by the first level signal output from the boosted voltage detection circuit 18, and the boosted voltage is reduced to the predetermined value. When the value exceeds the value, the timing generation circuit is activated by the second level signal output from the boosted voltage detection circuit 18, and sends the timing signal to the word / address pointer 16. In this embodiment, when the boost voltage of the charge pump is not sufficient, not only the boost voltage but also the erase / write timing is not supplied, so that erroneous writing can be prevented twice.

FIG. 6 is a block diagram showing a fourth embodiment of the present invention. This embodiment is different from the second embodiment in that a boost voltage notification terminal WRN is provided, and the output of the boost voltage detection circuit 18 is supplied to this terminal. In this embodiment, the output signal of the boosted voltage detection circuit 18 is supplied not only to the cut-off circuit 19 but also to the boosted voltage notification terminal WRN. Therefore, when the level of the boosted voltage is not sufficient, erasing / writing to the memory is avoided. In addition, it is possible to externally monitor that no erasing / writing has been performed. Further, when the level of the boosted voltage is sufficiently high, it is possible to know from the signal at this terminal that the erasing / writing to the memory cell has been performed.

FIG. 7 is a block diagram showing a fifth embodiment of the present invention. This embodiment is different from the third embodiment in that a boosted voltage notification terminal WRN is added, and a boosted voltage detection circuit 1
8 can be monitored. In this embodiment, when the level of the boosted voltage output from the charge pump circuit 13 is not sufficient, the boosted voltage and the erasing / writing timing are not supplied to the memory. Can be externally monitored that writing is not performed due to insufficient data.

While the preferred embodiment has been described above,
The present invention is not limited to these embodiments, and various changes can be made within the gist of the present invention described in the claims. For example, in the third to fifth embodiments, a clamp circuit may be provided at an input portion or an output portion of the boosted voltage of the cutoff circuit 19 to limit the voltage applied to the word / address pointer 16.

[0018]

As described above, in the nonvolatile semiconductor memory device according to the present invention, when the boosted voltage for erasing / writing is lower than a predetermined value, this is prevented from being transmitted to the memory cell, and the predetermined voltage is maintained. Therefore, according to the present invention, even if the output signal of the control circuit block is in an erase / write state, the boosted voltage for erasure / write is transmitted according to the present invention. If the level is not sufficient, the erasing / writing operation is not performed, so that erroneous writing caused by a writing operation with an insufficient boosted voltage or omission of write data can be prevented. Therefore, according to the present invention, even when the level of an external power supply such as a battery is lowered or the level of a boosted voltage is lowered for some other reason, data is not destroyed, and a highly reliable nonvolatile semiconductor memory device is provided. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a boosted voltage clamp / transfer circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating the operation of a boosted voltage clamp / transmission circuit according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a block diagram showing a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a fifth embodiment of the present invention.

FIG. 8 is a block diagram of a conventional example.

[Explanation of symbols]

 Reference Signs List 10 control circuit block 11 erase / write timing generation circuit 12 pulse generator 13 charge pump circuit 14 boost voltage clamp / transmission circuit 15 register 16 word / address pointer 17 memory cell array 18 boost voltage detection circuit 19 cutoff circuit

Claims (3)

(57) [Claims] A memory cell array in which a plurality of memory cells are arranged; a control circuit block for controlling various operations including erasing, writing, and reading operations on the memory cells; and a memory cell controlled by the control circuit block. a timing generating circuit for generating a signal indicative of the timing of the erasing and writing to, erasing and Form
A booster circuit for boosting a power supply voltage supplied from the outside in accordance with an instruction of the control block in the write mode to generate a boosted voltage for erasing / writing; a voltage detecting circuit for detecting the boosted voltage; sometimes the voltage detecting circuit nonvolatile semiconductor memory device, wherein a and a switching circuit for blocking transmission to the memory cell of the boosted voltage when the boosting voltage to be detected is below a predetermined value. 2. The non-volatile semiconductor device according to claim 1, wherein the timing generation circuit transmits the signal only when the boosted voltage detected by the voltage detection circuit is equal to or higher than a predetermined value. Storage device. 3. The non-volatile semiconductor memory device according to claim 1, further comprising means for externally detecting an output signal of said voltage detection circuit.