JPH0668685A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable reading data surely within a range of wide power supply voltage to be carried out by detecting a level of power supply voltage of a non-volatile memory cell and compensating output voltage of a sense amplifier with voltage generated in accordance with it. CONSTITUTION:A sense amplifier is constituted with a level detecting circuit 31 of a data line and a feedback circuit 32, in a reading circuit of a LSI incorporated in a EPROM, the feedback circuit 32 adjusts gate voltage of a MOSFET Q8 for current control in accordance with a level of a data line, and adjusts current flowing toward the data line. Also, a MOSFET Q14 for compensating an output level is connected to a point between a node n6 of the level detecting circuit 31 and a power supply voltage Vcc. And output voltage Vco of a power supply potential detecting circuit 36 which detects a level of the power supply voltage Vcc and outputs voltage corresponding to the detected voltage is applied to a gate terminal of the FET Q14. Thereby, an output of the sense amplifier, that is, the level detecting circuit 31 is compensated in accordance with a level of the power supply voltage Vcc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology and a technology effective when applied to a semiconductor integrated circuit equipped with a rewritable read-only semiconductor memory device, for example, an EEPROM (electrically programmable). -Technology effective when used in a single-chip microcomputer with a built-in read-only memory.

[0002]

2. Description of the Related Art In a data processing LSI (large-scale integrated circuit) such as a single-chip microcomputer (hereinafter referred to as a single-chip microcomputer), a ROM (read only memory) for storing a system operation program or the like. There is one that integrally includes a read-only storage device called a memory, which is also referred to as a ROM hereinafter).

Conventionally, the above-mentioned built-in ROM in a single-chip microcomputer is generally composed of a mask ROM that is generally not rewritable, but a rewritable memory called an EPROM (EPROM) is mounted on the package. Some are.

Regarding the single-chip microcomputer in which the mask ROM is built in on the chip, the semiconductor data book "8 /" issued by Hitachi, Ltd. in September 1982 was used.
16-bit Microcomputer ", pages 45 to 82, and EPROM-mounted single-chip microcomputers are described in more detail in pages 350 to 389 of the same data book.

By the way, in the above-mentioned single-chip microcomputer equipped with a ROM (including an on-chip one), the sense amplifier (readout circuit) is continuously operated during the ROM read cycle. .

However, the ROM mounted on the single-chip microcomputer does not need to continuously operate the sense amplifier during the read cycle, and after the output of the read data is confirmed, the sense amplifier can be operated by latching it. No need.

Therefore, the present inventor has clarified that the conventional single-chip microcomputer has a disadvantage that the power consumption of the sense amplifier is large.

In order to reduce power consumption, a semiconductor memory such as a static RAM has been proposed in which the operation of the sense amplifier is stopped after the output of the read data is confirmed.

Further, the operating power supply voltage range at the time of reading the conventional single EPROM is 5V ± 5% or 5V ± 10.
%. This is from "Hitachi IC Memory Data Book", page 279, published by Hitachi, Ltd. in September, 1984.
See page 318. However, the operating power supply voltage range required for a single-chip microcomputer is wide, for example, there is a range of 2.7V to 6V. Therefore, when the EPROM is built in the single-chip microcomputer, the EPROM that operates in a wide voltage range is required.

[0010]

However, in a memory which is not an on-chip type such as a static RAM, it is operated by a control signal such as a chip enable signal supplied from a microcomputer, etc. The timing pulse (clock) from the outside is not given.

Therefore, in order to dynamically operate the sense amplifier in order to reduce power consumption, a timing generation circuit such as an address transition detection circuit that detects a transition of an externally supplied address signal and forms a timing signal is used. It must be provided internally, and the larger the number of address inputs, the larger and more complicated the circuit becomes.

Further, when the writing state of the non-volatile memory cell is shallow and the threshold value is not sufficiently high, the selection level of the word line becomes higher than the above threshold value when the power supply voltage becomes high, and erroneous data reading is performed. May be

An object of the present invention is to provide an LS equipped with a ROM.
In I, it is intended to reduce power consumption without providing a complicated circuit such as an address change detection circuit.

Another object of the present invention is to provide a technique capable of precisely stopping the sense amplifier in an LSI having a ROM.

Still another object of the present invention is to provide a sense amplifier circuit which can operate in a wide power supply voltage range, for example, a sense amplifier circuit which can perform accurate reading in a wide power supply voltage range even when the writing state is shallow. To provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0017]

Among the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, note that a data processing LSI such as a single-chip microcomputer equipped with a ROM has a clock indicating the timing internally, and when this clock is used, the read cycle is entered during the ROM read. However, the R sense amplifier is not activated immediately.
The sense amplifier is activated around the time when the word line in the OM is selected and the level of the data line is determined, and after reading the data, the output of the sense amplifier is latched and then the sense amplifier is stopped. The operation period of the amplifier is shortened, thereby reducing power consumption without providing a complicated timing generation circuit such as an address change detection circuit.

Further, a dummy memory array and its sense amplifier different from the built-in ROM memory array are provided, and the dummy memory array is preliminarily filled with data such that the data line level is always changed by reading. The object of the present invention is to achieve accurate detection of the sense amplifier stop timing that minimizes the operation period of the sense amplifier by reading and detecting the data in the dummy memory array.

In addition, the sense amplifier circuit of the rewritable nonvolatile memory includes a level detection section for detecting the level of the data line, a voltage corresponding to the level of the data line, and a voltage for the data line and the power supply voltage. Feedback is applied to the current control transistor connected between the feedback control unit and the feedback unit that controls the current flowing in the data line according to the level of the data line.
The correction means for correcting the output voltage of the detection unit is connected by the output voltage of the power supply voltage detection circuit that detects the level of the power supply voltage and generates a voltage corresponding to the level.

[0021]

According to the above-mentioned means, the operation start timing of the sense amplifier circuit uses the periodic timing necessary for the operation of the data processing circuit, and the operation stop timing of the sense amplifier circuit uses the data of the dummy memory array. Can be done by reading and detecting
The operation period of the sense amplifier can be minimized with a simple circuit, and low power consumption can be realized.

In the case where the nonvolatile memory cell has a shallow written state and the threshold value is not sufficiently high, the selection level of the word line becomes higher than the above threshold value when the power supply voltage becomes high, and erroneous data reading is performed. However, even if the writing state is shallow, the output voltage correction means can perform accurate reading in a wide power supply voltage range.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below with reference to the drawings.

FIG. 3 shows an example of the configuration of a single-chip microcomputer to which the present invention is applied. Each circuit portion shown in FIG. 3 is formed on a single-layer semiconductor substrate such as silicon. .

The single chip microcomputer of this embodiment is
Although not particularly limited, a microprocessor (hereinafter referred to as a CPU) 1 for controlling an internal execution unit and the like according to a program, a program ROM 2 in which an operation program of the CPU 1 and the like are stored, and a work area of the CPU 1 are mainly provided. RAM (random access memory) 3, serial communication interface circuit 4,
The timer circuit 5 and four input / output ports 6a to 6d and the like are connected to each other via an internal address bus 7a and an internal data bus 7b.

Although not shown in detail, the CPU 1 has a program counter for holding an instruction and a data address to be read next, an instruction register for sequentially fetching instructions of the program, a micro ROM storing a micro program, or The control unit is composed of a random logic circuit and forms a control signal according to the instruction fetched in the instruction register, and an execution unit including various registers such as an accumulator and an ALU (arithmetic logic unit).

Of the input / output ports 6a to 6d, the address bus 7a and the data bus 7b are connected to the port 6d, and the address bus 7a and the data bus 7b are connectable to the port 6c via the multiplexer 8. There is.

Further, there is provided a mode switching circuit 9 which determines an operation mode after resetting the microcomputer by setting an appropriate external terminal to a predetermined state.

The input / output port 6d is operated by the mode setting circuit 9 so as to have a data input / output function or an address output function, and the port 6c is similarly operated.
Under the control of the mode switching circuit 9, it operates so as to have a data input / output function or a function of multiplexing the data bus and the address bus.

As a result, the address space of the single chip microcomputer of this embodiment can be expanded.

In this embodiment, the program ROM 2 is composed of a rewritable EPROM having a storage capacity of, for example, 4k × 8 bits, although not particularly limited thereto.

The single-chip microcomputer has an address decoder 10 for selectively operating the program ROM 2 so that the address data output from the CPU 1 onto the address bus 7a is stored in the program ROM (EPROM). ) 2, the address decoder 10 outputs the enable signal φ _E to decode the program ROM 2 so that the program ROM 2 is in the operating state.

Whether the mode switching circuit 9 is in a mode in which it operates as a normal microcomputer (hereinafter referred to as a microcomputer mode) or not depending on the input state of the dedicated mode setting external terminal 11 is used. Data writing mode (hereinafter referred to as EPROM mode)
Then, the operation mode inside the microcomputer is determined accordingly.

By the mode switching circuit 9, the inside is EPRO.
When set to M mode, circuits other than the program ROM 2 and input / output ports required for data input (CPU 1 and RA
M3) are separated from the internal address bus 7a and the data bus 7b.

As a result, from the outside of the chip, the EPR
Only the OM is visible.

In the EPROM mode, the internal clock signals φ1 and φ2 are not formed, and the program RO
The M (EPROM) 2 is statically operated.

In the CPU 1 shown in FIG. 3,
Although not shown, an original oscillation signal such as 4 MHz supplied from the outside is divided, and as shown in FIG. 5, two internal phases are shifted in phase by a half cycle so that the low level periods do not overlap each other. clock signals phi _1, and phi _2, these internal clock signals phi _1, the clock pulse generator is provided to form a substantially phase equal external periodic signal E and clock phi ₁ has half the frequency of phi ₂ There is.

The internal clock signals φ ₁ and φ ₂ are
It is supplied to each circuit block in the chip such as a control circuit (described later) in the program ROM 2 and operates those circuits in synchronization with the CPU 1.

The external synchronization signal E is output to the outside of the single chip microcomputer and supplied to the peripheral device as a system clock.

FIG. 4 shows an embodiment of the program ROM 2 comprising an EPROM, and FIG. 5 shows a timing chart thereof.

The program ROM 2 of this embodiment is not particularly limited, but the memory array is divided into eight memory blocks 20a to 20h, and each memory block is _{256 × 16} FAMOS (floating) arranged in a matrix. A non-volatile memory cell MC including a gate type MOS transistor).

The memory blocks 20a to 20h are also included.
A dummy memory array 21 in which 256 memory cells are arranged in a line along the data line is provided.

256 words W _{1 to} W in the memory blocks 20a to 20h and the dummy memory array 21.
₂₅₆ are formed continuously, respectively, and address bus 7a
X for taking in and decoding the above address signals A _{0 to} A ₇
The decoder 22 sets one of them to the selection level.

The FAMOS forming the memory cell MC is
When writing is performed in advance, that is, when charge is injected into the floating gate electrode, the threshold voltage is at the selection level (about 5 V) of the word lines W _{1 to} W _64.
Will be a little higher than.

Further, the threshold voltage of the so-called erased FAMOS in which writing is not performed is made lower than the selection level of the word line.

Therefore, the FAMOS (memory cell MC) of each row, which is control-gate connected to the word line set to the selection level by the decoder 22, becomes non-conductive or conductive depending on the write or erase state. To be done.

The 16 data lines drain terminal of each row are connected in the memory block 20a DL ₁ through DL ₁₆
Are column switches Q _{C1 to} Q _C16 each of which is composed of a MOSFET (insulated gate type field effect transistor) and one of which is turned on by the Y decoder 23.
And is connected to the common data line CDL ₁ via.

[0048] is to be connected to the common data line CDL ₂ ~CDL ₈ by each data is also column switch circuit 24b~24h in other memory blocks 20a-20h.

The Y decoder 23 takes in the address signals A _{8 to} A ₁₁ from the address bus 7a and decodes them to form a data line selection signal and applies it to the gate terminals of the column switches Q _{S1 to} Q _S16. Turn on any one.

The shared data lines CDL _{1 to} CDL ₈ provided for each of the memory blocks 20a to 20h have control transistors Q _{W1 to} Q _W8 , which are depletion type MOSFETs, connected to the read circuits 25a to 25h. .

Although not particularly limited, the dummy data line DLd in the dummy memory array 21 is read through the dummy read circuit 26 via the dummy column switch Qcd and the dummy write control MOSFET Qwd which are always turned on.
It is connected to the.

At the time of data reading, a write control signal We * based on a mode designating signal EPM output from the mode switching circuit 9 and a control signal input from the outside is used to control the write control connected to the common data lines CDL _{1 to} CDL _8. use MOSFETQw1~Qw8 is conductive, the level of the data line by the read circuit 25a~25h is read signal D ₀ to D ₇ are amplified respectively formed, is output on the data bus 7b.

At this time, as will be described later in detail, the level of the dummy data line DLd is detected by the dummy read circuit 26 to know the read end timing signal,
Control signal S output from dictated control circuit 27
Readout circuits 25a to 25 by changing AC *, LTC, etc.
It controls h and 26 (see FIG. 5).

On the other hand, each of the memory blocks 20a-20
The source terminal of the FAMOS forming each memory cell in h is connected to the common source lines C _{S1 to} C _S16 for each column,
These common source lines C _{S1 to} C _S16 include a pair of enhancement type MOSFETs Q connected in parallel for each column.
_{N1 to} Q _N8 and depletion type MOSFETs Q _{D1 to} Q _D8 are connected to the ground point of the circuit.

Each of the pair of MOSFETs Q _{N1 to} Q _N
The write control signal WE * is applied to _N8 and MOSFETs Q _{D1 to} Q _D8 .
Is controlled by.

That is, at the time of data reading, the high-level write control signal WE * is applied to the gate terminal, so that the MOSFETs Q _N1 and Q _D1 are both turned on to connect the common source lines C _{S1 to} C _S8 to the ground point. Let

Further, at the time of data writing, by applying the low level write control signal WE * to the gate terminal, only the depletion type MOSFET QD1 is turned on, and the common source line C _S1 is turned on via a resistor of an appropriate size.
~ C _S8 is connected.

As a result, at the time of writing, a current flows from the common source line toward the ground point to raise the potential of the common source line, which prevents a leak current from flowing to the unselected memory cells.

In the above case, the transistors connected between the common source lines C _{S1 to} C _S8 and the ground point may be only the depletion type MOSFETs Q _{D1 to} Q _D8, but in the present embodiment, the enhancement type MOSFETs are connected in parallel with them. MOSFETQ
By connecting _{N1 to} Q _N8 , the resistance value of the common source line at the time of reading can be lowered.

By _reducing the resistance value of the common source lines C _{S1 to} C _S8 , the level difference of the data lines at the time of reading can be increased.

Although not particularly limited, in this embodiment, 8
For one of the memory blocks 20a to 20h and the dummy memory array 21, MOSFETs Q _N1 to
Q _N8 and Q _{D1 to} Q _D8 are provided, and each common source line is connected to the ground point.

Further, each of the memory blocks 20a-20
Write circuits 28a to 28h are connected to the common data lines CDL _{1 to} CDL ₈ provided for each h, and the write circuits 28a to 28h write data to each memory cell.

The write circuits 28a to 28h are connected to predetermined pins (shared with signal pins in the microcomputer mode).
A write voltage Vpp, such as 12.5 V, which is higher than the power supply voltage (5 V) applied in the microcomputer mode, is applied, and the mode switching circuit 9 shown in FIG. When it is determined that the write operation is performed, the write operation is performed based on the mode designating signal EPM output from the mode switching circuit 9.

[0064] That is, the write circuit 28a~28h in EPROM mode, generates a voltage corresponding to the data capture data Din ₀ through Din ₇ which is placed from the time the outside on the data bus 7b, a memory block 20a
It is applied to the common data lines CDL _{1 to} CDL ₈ of ˜20 h.

The write voltage applied to the common data lines CDL _{1 to} CDL ₈ is supplied to the data line DL through the column switch Qc which is selectively turned on by the Y decoder 23 at that time.

Further, in the EPROM mode, the X decoder 22 supplies a selection signal having a level such as 12.5 V, which is higher than the selection level (5 V) in the microcomputer mode, to one of the word lines.

When writing to the selected memory cell, the control gate electrode of the memory cell is
A high selection signal such as 12.5V is applied by the X decoder 22, and its drain terminal is connected through a column switch Qc to which a high write voltage such as 12.5V is connected by the write circuits 28a to 28h. It is supplied to the data line DL.

As a result, charges are injected into the floating gate of the selected memory cell to bring it into the written state.

At this time, the common data lines CDL _{1 to} CDL ₈
The transistors Q _{W1 to} Q _W8 connected to are applied with the low level write control signal WE * based on the mode designating signal EPM output from the mode switching circuit 9 and the control signal input from the outside, so that the read circuit side is connected. When the potential of 2 becomes about 3 V or more, the device is cut off.

[0070] Therefore, not convey a higher write voltage supplied from the write circuit 28a~28h to the common data line CDL ₁ ~CDL ₁₆ common to the readout circuit 25a to 25h.

In the above case, the dummy memory array 2
Since the dummy memory cells constituting 1 always read the data corresponding to the erased state as described later,
It is not necessary to write data to the dummy memory cell.

Next, the timing of the input / output signals of the control circuit 27 will be described with reference to FIG.

The control signal SAC * is the system clock E.
Based on the internal clock signal φ1, it is changed to the low level in synchronization with the clock φi formed in the control circuit.

The clock φi is a signal which changes in the same manner in synchronization with the clock signal φ1 only during the low level period of the system clock E, and the control circuit 27 sends this clock φi to the read circuits 25a to 25h and 26 and outputs it. Initialize.

Then, the read circuits 25a to 25c are driven by the control signal SAC * which is changed to the high level in synchronization with the falling of the clock φi for the read circuit initialization.
The operations of 25h and 26 are started.

The control circuit 27 controls the control signal SAC.
In synchronization with the fall of *, the precharge signal φp is set to the low level and supplied to the read circuits 25a to 25h and 26 to start the precharge of the internal sense amplifier (described later).

Then, the level detecting means provided in the control circuit 27 detects the level of the dummy data line DLd, and when the dummy data line DLd rises above a predetermined level, the precharge φp is raised. Has become.

When the precharge is completed, the control circuit 27 raises the drive signal φx of the X decoder 22 to drive the X decoder 22.

As a result, the level of the selected one word line W rises, and after a certain time, the read circuits 25a ...
Read data D _{0 to} D ₇ output from 25h and dummy read data D output from the dummy read circuit 26.
d changes.

The control circuit 27 monitors the dummy read data Dd, changes the control signal SAC * to the high level when the data is fixed, and the read circuit 2 is read.
The operations of 5a to 25h and 26 are stopped.

Further, the control circuit 27 changes the control signal LTC supplied to the read circuits 25a to 25h and 26 to the high level in synchronization with the rise of the drive signal φx of the X decoder 22.

Then, the latch circuits (described later) in the read circuits 25a to 25h and 26 start the latch operation and take in the output of the sense amplifier.

Then, the control signal LTC is changed to the low level in synchronization with the operation of the read circuits 25a to 25h, 26 being stopped by the rise of the control signal SAC *, whereby the latch circuit ends the latching of the data. Then, it shifts to the state of holding the data.

While the latch circuit holds data,
The data of the read circuits 25a to 25h is stored in the data bus 7b.
Output above.

Next, FIG. 1 shows the read circuits 25a to 25a.
An example of a specific circuit configuration of one circuit 25a of 5h and a part of the memory array connected to it are shown.

Unless otherwise specified below, each MOSFET constituting the circuit is assumed to be of N-channel type.

In the same figure, for facilitating understanding, one FAMOS Qf which constitutes a memory cell in the memory array is shown.
And one of the plurality of column switches is representatively shown. The node n ₁ to which the source terminal of the FAMOS Qf is connected is the common source line CS in FIG. 4 and the node n ₂ to which the drain terminal is connected. Corresponds to the data line DL.

The column switch Qc is connected to the node n ₂ corresponding to the data DL.

A write control transistor is shown by Qw.

Therefore, the connection node n ₃ between the column switch Qc and the transistor Qw corresponds to the common data line CDL.

The selection signal X output from the X decoder 22 of FIG. 4 is applied to the gate terminal of the FAMOS Qf through the word lines (W _{1 to} W ₂₅₆ ) and the column switch Qc.
The selection signal Y output from the Y decoder 23 is applied to the gate terminal of the.

A control signal WE * is applied to the gate terminal of the write control transistor Qw.

The read circuit 25a comprises a sense amplifier SA, a latch circuit 34 and an output circuit OC.

The output circuit OC is made up of a trastate circuit arranged between the latch circuit 34 and the data bus.

The sense amplifier SA is not particularly limited, but as shown in the drawing, the P-channel MOSFET Q ₁ ,
Q _3, Q _5, Q ₈ and N-channel MOSFETQ _2, Q _4,
It is composed of Q ₆ and Q ₇ and a CMOS inverter 33.

The MOSFET Q ₁ is switch-controlled by the control signal SAC * and operates as a constant current source.

The MOSFET Q ₂ is switch-controlled by the signal φi and is provided to discharge the node n ₄ .

The MOSFETs Q ₃ to Q ₇ constitute one differential amplifier circuit as a whole.

That is, the P-channel MOSFET Q ₃
And Q ₅ are N-channel input differential amplifier MOSFET Q ₄
And Q _{6 form} a current mirror load, and the N-channel MOSFET Q ₇ forms an operating current source.

MOSFET Q ₄ has its gate coupled to node n ₄ , and MOSFET Q ₆ has its gate coupled to a reference voltage (not shown).

The reference voltage source is not particularly limited, but is composed of, for example, a resistance voltage dividing circuit, and upon receiving the power supply voltage Vcc, outputs a reference voltage Vref of an appropriate level to be supplied to the differential amplifier circuit. .

The P-channel MOSFET Q ₈ is a precharge MOSFET.

The operation of the read circuit 25a having this configuration is as follows.

First, when the clock φi is set to the high level as shown in D of FIG. 5, the MOSF is accordingly responded.
ETQ ₂ is turned on.

The node n ₄ is connected to the MOSFET Q ₂ by
Initialized to a level of almost 0 volts.

Next, when the clock .phi.i falls to the low level, the control signal SAC * and the precharge signal .phi.p fall to the low level in synchronization with it as shown in E and F of FIG.

Although not particularly limited, the control signal SAC is
The control signal SAC * is set to the high level in synchronization with the low level.

The MOSFET Q ₇ is made conductive by setting the control signal SAC to the high level.

In response to this, an operating current starts to flow through the differential amplifier circuit.

In this case, the potential of the output node n ₅ is MO
Since the SFETQ ₈ is turned on by the low-level precharge signal φp, it is brought to the precharge level (high level).

When the signals φp and SAC are set at the above timing, regardless of the output node ns of the differential amplifier circuit being set to the precharge level,
An operating current will flow through the differential amplifier circuit.

The generation of the operating current in such a precharge period is, for example, the timing when the control signal SAC is set to the high level substantially the same timing as the timing when the precharge signal φp is set to the high level again or more. It can be made substantially zero by delaying to the delayed timing.

In this case, however, it should be noted that the circuit (not shown) for forming the control signal SAC becomes somewhat complicated.

The MOSFET Q _{2 of} FIG. 1 is turned off by setting the timing signal φi to the low level as shown in FIG.

The precharge MOSFET Q ₁ is rendered conductive by setting the control signal SAC * to the low level as shown by E in FIG.

As a result, the node n ₄ has the MOSFE
Charging begins via TQ ₁ .

Here, the address signals A ₀ to A ₁₁ supplied to the address bus 7a of FIG. 4 are set to the low level when the system clock E is set to the low level as shown in A of FIG.
The levels are determined in synchronization with it.

In response to this, the output of the Y decoder 23 is
The level of the signal SAC * is determined before it is set to the low level.

That is, one column switch corresponding to the address signals A _{8 to} A ₁₁ is turned on.

Therefore, the selection data DL (node n ₁ )
When the control signal SAC * is set to the low level, the precharge starts via the control MOSFET Qw and the column switch Qc.

The read circuit 26 of FIG. 4 has substantially the same configuration as the read circuit 25a of FIG.

As a result, the data lines (hereinafter referred to as dummy data lines) DL in the dummy memory array of FIG.
d starts to be charged at the same timing as the data line to be selected in the memory array.

Although not particularly limited, the dummy data line DL
MOSFETQ provided between d and the read circuit 26
cd and Qwd are a column switch Qc and a control MOSF.
The impedance is made substantially equal to the impedance of ETQw.

Therefore, the precharged state of the data line to be selected in the memory array can be simulated by the dummy data line DLd.

The level of the dummy data line DLd is monitored by the control circuit 27 shown in FIG.

When the precharge level of the dummy data line DLd reaches a predetermined level as shown in G of FIG. 5,
In response to this, the precharge signal φp * output from the control circuit 27 is returned to the high level as shown in F of FIG. 5, and the drive signal φx is set to the low level as shown in H of FIG. Is changed to high level.

The precharge MOSFET Q ₈ coupled to the output node n5 of the differential amplifier circuit is turned off by setting the signal φp to the high level.

The X decoder 22 of FIG. 4 is put into operation by setting the drive signal φx to the high level.

Accordingly, one of the plurality of word lines W ₁ to W ₂₅₆ corresponding to address signals A ₀ to A ₇ is set to the selection level (high level) substantially equal to power supply voltage Vcc.

Here, FAMOSQ as a memory cell
f has one of a high threshold voltage and a low threshold voltage according to write data in advance.

When FAMOS Qf has a high threshold voltage, FAMOS Qf maintains the off state even when the word line is set to the selection level. Therefore in this case,
No direct current path is formed between the circuit node n _{4 of} FIG. 1 and the circuit ground. The node n ₄ remains at the precharge level (high level). Data line DL
Similarly, (node n ₂ ) remains at the precharge level.

On the contrary, if FAMOS Qf has a low threshold voltage, FAMOS Qf is turned on accordingly when the word line is set to the selection level. Therefore, in this case, the control MOSFET Qw and the column switch Q are provided between the circuit node n ₄ and the ground point of the circuit.
A direct current path is formed by c, FAMOS Qf and MOSFETs Q _N1 and Q _D1 . The data line DL and the node n ₄ therefore start to be lowered in their respective levels as the word line goes down to the selected level.

According to this embodiment, the level of the dummy data line DLd is referred to detect whether the level of the node n ₄ and the data line DL has been changed from the precharge level to the readable level. It

Each FAM in the dummy memory array 21
The OS transistor is set in the unwritten state as described above and has a low threshold voltage.

Therefore, in the dummy data line DLd, when one of the word lines is selected, the charge stored in the dummy data line DLd is F.
As it begins to be discharged through the AMOS transistor, its potential is lowered as shown at G in FIG. The level of the dummy data line DLd is detected by the read circuit 26.

The output of the read circuit 26 is changed from the low level to the high level as indicated by J in FIG. 5 when the level of the dummy data line DLd is lowered below the predetermined level.

The control circuit 27 is the read circuit 2
By setting the output of 6 to the high level, the control signals SAC * and SAC are changed to the high level and the low level as shown in E of FIG. 5, respectively.

Thus, the precharge MOSFET
Q ₁ is turned off, and the differential amplifier circuit is turned off. The threshold voltage of the read circuit 26 is
Considering the operation delay of the control circuit 27, it may be set to a value slightly higher than that of the read circuit 25a.

A latch control signal LT for controlling the operation of the latch circuit composed of the clocked inverter 34 of FIG.
Although not particularly limited, C is set to a high level based on the monitoring result of the dummy memory array, and the control signals SAC * and SAC are returned to the high level and the low level, respectively, as shown in L of FIG. It goes low level before. The clocked inverter 34 has a latch control signal L
If TC is set to the high level, an output signal of the level corresponding to the previous input signal is output regardless of the input signal, and if the control signal LTC is set to the low level, the input signal at that time is fetched. Therefore, the output of the clocked inverter 34 is changed as shown in K of FIG. 5 in response to the change of the control signal LTC.

FIG. 2 shows a circuit diagram of a sense amplifier which can be replaced with the sense amplifier SA of FIG.

In this embodiment, a constant current MOSFET Q for flowing a read current into each data line via the column switch Qc between the drain terminal (node n ₄ ) of the control transistor Qw and the power supply voltage Vcc. ₁ and a current control MOSFET Q ₈ for controlling the current are connected in series. Of these, the MOSFET Q ₁ is formed in a P-channel type and operates as a constant current source by applying a ground potential to its gate terminal.

A level detection circuit 31 for detecting the level of the selected data line DL (node n ₃ ) and the gate voltage of the current control MOSFET Q ₈ according to the level of the data line DL are applied to the node n _4. A feedback circuit 32 that adjusts and controls the current flowing toward the data line is provided.

In the feedback circuit 32, the gate terminal is the node n ₄
Connected to the MOSFET Q ₉ whose current is controlled by the potential of the data line DL, and a control signal SAC * output from the control circuit 27 to the gate terminal.
P-channel type MOSFE adapted to receive
It is composed of TQ ₁₀ and. And MOSFE
The potential of the connection node n ₅ between TQ ₉ and Q ₁₀ is M for current control.
It is applied to the gate terminal of OSFET Q ₈ .

The level detecting circuit 31 includes a MOSFET Q ₁₁ having a source terminal connected to the node n ₄ and a P-channel load MOSFET Q ₁₂ connected between the drain terminal of the MOSFET Q ₁₁ and the power supply voltage Vcc.
It is composed of and. The gate terminal of the MOSFET Q ₁₁ is applied with the potential of the node n ₅ in the feedback circuit 32 and is connected to the data line to control the current.
It is on / off controlled similarly to Q ₈ . MOSFET
The gate terminal of Q ₁₂ is applied with the potential of the node n ₄ at which the read level of the data line is output, and acts as a resistance variable load element.

The level detection circuit 31 and the feedback circuit 32 constitute a so-called sense amplifier. In this sense amplifier, in addition to the above MOSFETs Q _{9 to} Q ₁₂ ,
Discharge MOSFETs Q ₂ and Q are provided between the node n ₄ and the ground point and between the node n ₅ and the ground point, respectively.
₁₃ are connected.

One discharge MOSFET Q
The _second gate terminal, said control circuit 27 initialization clock φi supplied is applied to, prior to the operation start of the sense amplifier (the fall of the control signal SAC *), pull the charge of the node n _4. The control signal SAC * output from the control circuit 27 is applied to the gate terminal of the other discharging MOSFET Q ₁₃ , which is turned on before the sense amplifier is operated to extract the electric charge of the node n _5. , Set the sense amplifier to the stopped state. When the control signal SAC * is changed to low level and the sense amplifier starts to operate, the MOS
FETs Q ₂ and Q ₁₃ are turned off and have no effect on the operation of the circuit.

An inverter 33 for waveform shaping is connected to the output node of the level detection circuit 31, that is, the connection node n ₆ of the MOSFETs Q ₁₁ and Q ₁₂ , and the inverter 33.
Output is a clocked inverter 3 as a latch circuit
It is entered in 4. The output of the clocked inverter 34 is amplified and inverted by the data output inverter 35 and output to the data bus 7b.

Although not particularly limited, the inverters 33 to 35 are of CMOS (complementary MOS) type. Further, the clocked inverter 34 is controlled by the control signal LTC from the control circuit 27 to perform the latch operation.

Further, between the node n ₆ in the level detection circuit 31 and the power supply voltage Vcc, a MOSFET Q ₁₄ for output level correction and a MOSFET Qp for precharge are provided.
Are connected. The MOSFETs Q ₁₄ and Qp are each formed in a P-channel type. The precharge signal φp output from the control circuit 27 is applied to the gate terminal of the precharge MOSFET Qp, and when the control signal SAC * changes from high level to low level and the sense amplifier starts operating. ,
First, the precharge signal φp pushes up the node n ₆ to the power supply voltage Vcc. As a result, the read data outputs D _{0 to} D ₇ are always set to the low level first.

Further, the output level correction MOSFE
A power supply voltage detection circuit 36 that detects the level of the power supply voltage Vcc and outputs a voltage corresponding to the level is supplied to the gate terminal of TQ _14.
Output voltage Vco is applied. As a result, the output of the sense amplifier, that is, the level detection circuit 31 is corrected according to the level of the power supply voltage Vcc.
This will be described in detail later.

Next, the operation of the read circuit having the above-mentioned configuration is as follows.

When the control signal SAC * supplied from the control circuit 27 changes from the high level to the low level, the MOSFET Q ₁₀ is turned on, the MOSFET Q ₁₃ is turned off, and the operation of the sense amplifier is started. That is, the MOSFET turned on by the control signal SAC *
Electric charges flow into the node n ₅ through Q _{10, and} the level of the node n ₅ is raised. As a result, MOSFET Q ₈
Is turned on, and the current supplied from the constant current MOSFET Q ₁ flows into the node n ₄ . By this time, the Y decoder 23 has turned on one column switch Qc corresponding to the addresses A _{8 to} A ₁₁ . Therefore, the current flowing into the node n ₄ flows into the data line DL through the selected column switch Qc to charge up the data line.

At this time, MOSFET Q ₁₁ is also turned on, so that the precharge signal φp also precharges from the output node n ₆ side of the sense amplifier as described above. Therefore, the data line DL is quickly precharged.

Moreover, the precharge of the data line is
The control circuit 27 monitors the level of the data line DLd in the dummy memory array 21 and raises the precharge signal φp to raise the precharge signal φp when the level exceeds a predetermined level. End the charge. In addition, the precharge signal φ
In synchronization with the rise of p, the drive signal φx output from the control circuit 27 is changed to the high level to drive the X decoder 22, and the level of the selected one word line is raised.

At the end of precharge, the control signal LTC supplied to the clocked inverter 34 is changed to the high level, and the output of the sense amplifier starts to be taken. Then, the sense amplifier output at the time when the clocked inverter 34 starts the latch operation is initially set to the high level by the precharge, so the output of the output inverter 35 is initially the low level.

As described above, when the word line starts rising after the completion of precharge, the threshold voltage is changed depending on whether the FAMOS Qf of the memory cell selected by this is in the written state or the erased state. Because they are different
A difference occurs in the potential of the data line DL (node n ₂ ). That is, when the selected FAMOS Qf is in the write state, the FAMOS Qf is selected at the word line selection level (about 5 V).
Is turned off, the data line DL (node n ₂ )
Potential is the same as at the end of precharge. On the other hand, if the selected FAMOS Qf is in the erased state, FAMOS Qf
Since Qf is turned on, the potential of the data line DL becomes low.

The potential of the data line DL, which has a difference as described above, is the column switch Qc and the write control transistor Q.
When it is transmitted to the node n ₄ through w, M in the feedback circuit 32
The OSFET Q ₉ is strongly turned on as the potential of the data line is higher. Then, when the MOSFET Q ₉ is strongly turned on, the potential of the node n ₅ is lowered, and the current control MOSFE
TQ ₈ will be turned off.

Therefore, when the selected FAMOS Qf is in the write state, the MOSFET Q ₈ is cut off and the current flowing toward the data line DL is limited, and the node n ₄
The electric potential of becomes equilibrium at a high place. On the other hand, the selected F
When the AMOS Qf is in the erased state, the FAMOS Qf is in the conductive state, so that the potential of the data line becomes low and the MOSFET Qf
₉ is weakly turned on, and the potential of the node n ₃ rises,
MOSFET Q ₈ continues to be turned on. As a result, the constant current supplied from the constant current MOSFET Q ₁ becomes
It flows through SFETs Q ₈ , Qw, Qc and FAMOS Qf and MOSFETs Q _D1 , Q _N1 to the ground point. As a result, an equilibrium state is reached where the potential of the node n ₄ is low due to the low impedance of the FAMOS Qf.

Therefore, the MOSFET Q ₁₁ forming the level detection circuit 31 connected to the node n ₄ is connected to the node n.
The potential of ₅ operates in exactly the same manner as the MOSFET Q ₈ . Therefore, when the selected FAMOS Qf is in the write state, the potential of the node n ₄ having a relatively high potential cuts off the MOSFET Q _{11 and} the potential of the output node n ₆ maintains a high level. Also, the selected FAM
When OSQf is in the erased state, the potential of the output node n ₆ is pulled down by the potential of the node n ₄ and the output of the waveform shaping inverter 33 is inverted.

In this way, when the output of the sense amplifier is determined, the control circuit 27 for monitoring the read data of the dummy memory array 21 in which the read data (the output of the inverter 35) is always inverted depending on the data line level. However, it detects the inversion of the read data on the dummy side and changes the latch control signal LTC from the high level to the low level. As a result, the clocked inverter 34 stops latching the output of the sense amplifier (inverter 33) and holds the data latched immediately before.

Then, in synchronization with the fall of the latch control signal LTC, the control signal SAC * output from the control circuit 27 is changed from the low level to the high level. Then, the MOSFET Q ₁₀ is cut off, current is not passed through the feedback circuit 32, and the MOSF
The ETQ ₁₃ is turned on, the node n ₅ is fixed at a low level, the MOSFET Q ₁₁ is turned off, and the level detection circuit 31
Also, the current stops flowing and the operation of the sense amplifier is stopped.

As described above, according to the above embodiment, although the sense amplifier is composed of the CMOS circuit, the feedback circuit 32 and the level detection circuit 31 are in operation while the circuit is operating.
The current that has been supplied to the sensor is limited only to the time when the sense amplifier is operated by the control signal SAC *. However, during the operation period of the sense amplifier, that is, during the low level period of the control signal SAC *, the control circuit 2
7, the power consumption of the sense amplifier is significantly reduced.

Further, when the control signal SAC * is set to the high level, the MOSFET Q ₈ is also turned off, so that the current flowing toward the data line is cut when the selected memory is in the write state, and the read current at the time of reading is read. The current consumption of the entire memory array is also reduced. Moreover, according to the above embodiment, the operating time of the sense amplifier becomes relatively short, especially when the period of the internal clock signals φ ₁ and φ ₂ becomes long,
There is an advantage that the effect of reducing power consumption becomes large.

Next, a supplementary description will be given of the operation of the output level correcting MOSFET Q ₁₄ of the sense amplifier, which has been briefly described above.

As shown in the above embodiment, when the data line level is detected by the sense amplifier composed of the level detection circuit 31 and the feedback circuit 32, the memory cell causes a write failure and the threshold value of the FAMOS Qf. When the voltage is lower than the selection level (Vcc) of the word line, as shown in FIG. 6, as the power supply voltage becomes higher, the output of the sense amplifier (node n ₆ potential) Vso decreases and becomes lower than the logical threshold value V _TL of the inverter 33 in the next stage, and there is a possibility that erroneous data may be read.

Therefore, in the above embodiment, the power supply voltage detection circuit 36 detects the level of the power supply voltage Vcc, generates a control voltage Vco having the characteristic shown in FIG. It is applied to the gate of the correction MOSFET Q ₁₄ . As a result, when the sense amplifier operates on the side where the power supply voltage Vcc is high, its output is the broken line A in FIG.
It will be corrected so as to increase with the tendency shown in.

The voltage characteristic shown in FIG. 7 is an example, and the elements (MOSFETs Q ₉ to
It depends on the characteristics and size of Q ₁₂ ).
In short, as a result of the relationship with the characteristics of the sense amplifier, as shown in FIG.
It suffices to form the control voltage Vco so as to obtain the output characteristics shown in FIG.

If the memory cell has a defective write and the threshold value is not sufficiently high, the word line selection level at the time of reading is turned on for a while and the data line level is hard to rise. May become longer. However, in the above embodiment, since the precharge MOSFET Qp is provided to precharge the word line in the non-selected state, the data line level can be quickly raised by the precharge and good reading can be performed. There is.

In the above embodiment, the memory array has 8
The description has been given of the case where the read circuit is divided into two blocks, the read circuits are provided corresponding to the blocks, and the 8-bit data is read in parallel.
The bit configuration of the memory array is not limited to that, and it goes without saying that it may be configured to have 1 bit, 4 bits, 16 bits or the like.

Further, the MOSFET Q ₁₄ for correcting the output level of the sense amplifier and the precharge M in the above-described embodiment are used.
The OSFET Qp can be omitted.

Further, the method of providing the dummy memory array to know the operation stop timing of the sense amplifier can be applied not only to the EPROM of the single-chip microcomputer but also to the EPROM as a single product (semiconductor memory).

[Effect] (1) The sense amplifier does not operate constantly,
Since the sense amplifier is activated when the word line in the ROM is selected and the level of the data line is determined by this, the output of the sense amplifier is latched and the sense amplifier is stopped after reading the data. By the action of shortening the operation period of the amplifier, there is an effect that power consumption can be reduced without providing a complicated timing generation circuit such as an address change detection circuit.

(2) A dummy memory array and its sense amplifier are provided separately from the memory array of the built-in ROM, and the dummy memory array is preliminarily filled with data such that the data line level always changes by reading. Since the data in the dummy memory array is read and detected, when the data read from the dummy memory array is fixed, the data read from the regular memory array is always fixed.
There is an effect that it becomes possible to accurately detect the sense amplifier stop timing that minimizes the operation period of the sense amplifier.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the configuration of the sense amplifier is not limited to that of the above-described embodiment, and various modifications can be considered. The present invention is effective when applied to a sense amplifier having a structure in which a through current flows during operation.

Further, in the above-mentioned embodiment, the single-chip microcomputer in which the EPROM is formed on the chip has been described, but it goes without saying that the present invention can also be applied to the single-chip microcomputer in which the EPROM is mounted on the package. Nor.

[Field of Use] In the above description, the invention mainly made by the present inventor was applied to a single-chip microcomputer having a built-in EPROM which is the field of use in the background, but the invention is not limited thereto. Not L with built-in EPROM with internal clock
The present invention can be used for SI or LSI with built-in ROM, and also for general semiconductor memory devices.

[0177]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

When the writing state of the nonvolatile memory cell is shallow and the threshold value is not sufficiently high, the selection level of the word line becomes higher than the threshold value when the power supply voltage becomes high.
Wrong data may be read. Even in such a shallow write state, the output voltage of the power supply voltage detection circuit, which detects the power supply voltage level and generates a voltage corresponding to it, corrects the output voltage of the sense amplifier to provide a wide power supply voltage range. Can be read accurately.

[0179]

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of a read circuit used in an LSI incorporating an EPROM according to the present invention.

FIG. 2 is a circuit configuration diagram showing another embodiment of a read circuit used in an LSI incorporating an EPROM according to the present invention.

FIG. 3 is a block diagram showing an example of a configuration of an EPROM built-in single-chip microcomputer to which the present invention is applied.

FIG. 4 is a circuit configuration diagram showing an embodiment of an on-chip EPROM circuit.

5 is a timing chart showing the operation of the EPROM circuit of FIG.

FIG. 6 is an explanatory diagram showing the power supply voltage dependency of the sense amplifier output of the read circuit of the embodiment.

FIG. 7 is an explanatory diagram showing an example of characteristics of a control voltage Vco to be applied to the gate of the sense amplifier output level correcting MOSFET when the power supply voltage Vcc changes.

[Explanation of symbols]

1 CPU (microprocessor) 2 Rewritable memory (EPROM) 3 Random access memory (RAM) 4 Serial communication interface circuit (SCI) 7a Address bus 7b Data bus 9 Mode switching circuit (MODE) 11 mode External terminal for setting 20a to 20h Memory block 21 Dummy memory array 24a to 24h Column switch circuit 25a to 25h Read circuit 26 Dummy read circuit 27 Control circuit 28a to 28h Write circuit 31 Level detection circuit 32 Feedback circuit 33 Waveform shaping circuit (inverter) ) 34 latch circuit (clocked inverter) 35 output inverter DL, DL ₁ ~DL ₈ data lines DLd dummy data line Qc, Q _C1 ~Q _C8 column switch MC memory cells CS ₁ ~ CS ₁₆ common source line CDL, CDL _{1 to} CDL ₁₆ common data line Qw, Q _{W1 to} Q _W8 write control transistor

Claims (7)

[Claims] 1. A semiconductor integrated circuit comprising a rewritable nonvolatile memory having a memory array and a sense amplifier circuit connected to a data line of the memory array, wherein the sense amplifier circuit comprises the data The level detection unit for detecting the level of the line and the voltage corresponding to the level of the data line are fed back to the current control transistor connected between the data line and the power supply voltage to feed the data line. The output voltage of the power supply voltage detection circuit that detects the level of the power supply voltage and generates a voltage corresponding to it is provided at the output node of the level detection unit. The semiconductor integrated circuit is characterized in that a correction means for correcting the output voltage of the detection section is connected. 2. The sense amplifier circuit means for initializing the sense amplifier circuit to a predetermined state prior to the start of the operation of the sense amplifier, and setting the output of the sense amplifier circuit to a predetermined level at the start of the operation of the sense amplifier. The semiconductor integrated circuit according to claim 1, further comprising: 3. The non-volatile memory comprises means for controlling start and stop of operation of the sense amplifier circuit, means for controlling means for initializing the sense amplifier circuit, and a predetermined output of the sense amplifier circuit. 3. The semiconductor integrated circuit according to claim 2, further comprising a control circuit having a means for controlling a level setting means. 4. The semiconductor integrated circuit according to claim 3, wherein the control circuit operates based on a periodic timing signal for operating the data processing circuit. 5. The semiconductor integrated circuit further comprises a data processing circuit, and the non-volatile memory is a memory capable of storing a program required for the data processing circuit. Item 5. A semiconductor integrated circuit according to item 1 or 4. 6. The semiconductor integrated circuit further has a RAM, and the RAM, the data processing circuit, and the non-volatile memory are interconnected by a bus, and the semiconductor integrated circuit has a first circuit. And in the second operation mode, in the first operation mode, the nonvolatile memory is supplied with the periodic timing signal, and in the second operation mode, the data processing 6. The semiconductor integrated circuit according to claim 5, wherein the circuit and the RAM are separated from the internal bus so that the periodic timing signal is not supplied to the memory. 7. The first and second operation modes are set by the input state of an external terminal for mode setting, and the first and second operation modes are set.
7. The semiconductor integrated circuit according to claim 6, wherein said operation mode is a mode for operating as a microcomputer, and said second operation mode is a mode for writing data in said nonvolatile memory.