JPS62224119A - Data processor - Google Patents

Abstract

PURPOSE:To attain high speed data transfer in an internal bus line by giving precharge to the internal bus line to an intermediate level of a power voltage in advance. CONSTITUTION:A precharge circuit PR consists of a P-channel MOSFET Q5 receiving a control signal phi'pr at its gate, a P-channel MOSFET Q6 of diode connection, an N-channel MOSFET Q7 whose gate receives a control signal phipr and an N-channel MOSFET Q8 of diode connection. In the stage of the instruction fetch, the control signals phi'pr, phipr are brought respectively into a low and a high level and the internal bus line BL is precharged in advance to the intermediate level. Thus, even when the size of a discharge MOSFET is not made large, the high speed discharge of the bus line is made possible, an undesired capacitive load of the internal bus line based on the discharge MOSFET is decreased and the high speed data transfer in the internal bus line is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a precharging technique for internal bus lines included in a data processing device, and is applicable to, for example, a digital signal processing processor capable of high-speed data processing including a multiplication circuit and an addition circuit. It relates to techniques that can be applied and are effective.

[Prior art]

In microprocessors, in order to limit the scope of application and achieve improved processing power and high-speed data processing, various dedicated processors have been provided.For example, in December 1985,
As described in "Microcomputer Handbook J P2O3 and I) 209" published by Ohmsha on May 25th, digital signal processing processors including 1 multiplication circuits and addition circuits are used in digital filters, tone generators for push-button telephones, etc. ing.

The present inventor has provided such a digital signal processor with t
; When considering the precharging technology for the internal bus line, we found that the internal bus line was precharged by MO8F.
When the internal bus line is precharged to the power supply voltage level using an ET or the like and the level of the internal bus line is determined by the output buffer circuit such as the arithmetic unit or internal data memory included in the digital signal processing processor, in other words, the precharge charge of the internal bus line is When discharging according to the data to be given to it, a discharge M included in the output buffer circuit is included to increase the discharge speed.
It was decided to increase the size of the O3FET, and also to increase the size of the precharge MOS FET in order to increase the precharge speed.

[Problem that the invention seeks to solve]

However, the large size of the discharge MOS
F' E When "I" is connected to multiple internal bus lines corresponding to the arithmetic unit or internal data memory, the discharge MOS F: Due to the influence of the gate capacitance and drain capacitance of "I" The undesired capacitive loading of the line will increase, resulting in
The present inventor has revealed that even if the size of the precharge and discharge MO3FET is increased, it is not possible to sufficiently increase the discharge and precharge speeds.

An object of the present invention is to provide a data processing device that can achieve high-speed data transfer on an internal bus line.

The above and other objects and novel features of the present invention are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, as a precharging circuit that precharges the internal bus line, an MO as a switch element is provided between each of a pair of power supply terminals of the circuit and the internal bus line.
A circuit is provided in which an SFET and a diode-connected MOSFET functioning as a resistance element are connected in series.

[For production]

According to the above-mentioned means, by precharging the internal bus line to an intermediate level of the power supply voltage, high-speed discharging of the bus line is possible without increasing the size of the discharge MO8FET. The undesired capacitive load on the internal bus line due to the internal bus line can also be reduced, thereby achieving high speed data transfer on the internal bus line.

〔Example〕

FIG. 1 is a circuit diagram showing a part of a digital signal processing processor (hereinafter simply referred to as processor) that is an embodiment of the present invention. Although not particularly limited, the processor shown in the figure can be manufactured using known semiconductor integrated circuit manufacturing technology.
It takes the form of a one-chip microprocessor formed on one semiconductor substrate.

In the figure, PC is a program counter for indicating the address of an instruction to be executed. The output terminal of the program counter PC is a ROM that stores instructions to be executed.
The data output terminal of the program memory PM is connected to the input terminal of a decoder DEC which receives and decodes the instruction to be executed. be combined. The data decoded by the decoder DEC is
The signal is supplied to a controller C0NT which forms various control signals for controlling the entire processor.

The ALU is an execution unit that receives control signals output from the controller C0NT and executes instructions. Execution part AL
U is a multiplier (not shown) for high-speed processing of product-sum calculations, which is important in digital signal processing.

It includes an adder (not shown), various registers (not shown), and the like. The output terminal of such execution unit ALU is not particularly limited, but may be P-channel type MO8FE'r Q and N
Channel type MO8FETQ21? The internal bus line IIL is coupled to the internal bus line IIL via a CMOS inverter circuit consisting of a CMOS inverter circuit.

Note that, in the internal bus line BL shown in FIG. 1, one of the signal lines included therein is representatively shown. Further, the input terminal of the execution unit AL (J) is coupled to the internal bus line BL via a clocked inverter circuit InV that can take on three-state states based on the timing signal output from the execution unit ALU.

In FIG. 1, DM is a representative data memory, which is constituted by RAM (Random Access Memory), although it is not particularly limited. The data memory DM is subject to read/write control based on the read/write control signal R/W output from the controller C0NT.
Addressing is performed based on an internal address signal (not shown) output from the . The data output terminal of the data memory DM is not particularly limited, but may be a P-channel type MOS.
F' ET Q 3, N channel/L/type MO8FE
'I.

Q4. The data input terminal of the data memory DM is connected to the internal bus line BL via the CMO83 state output circuit consisting of the circuit G1 and G2, and the data input terminal of the data memory DM is outputted from the data memory I)M, although the data input terminal is not particularly limited. It is coupled to the internal bus line BL via a clocked inverter circuit 1nv that can assume three stay i states based on a timing signal. MO8l? E"l'Q3.Q4
In a three-state output circuit consisting of a gate circuit G2 and a gate circuit G2, such MOS +=”ET Q3 and Q4 are
During the non-output period, both circuits G1 to G are turned off, and during the output period, one of them is turned on by data supplied from the data memory. Although not shown in the drawings, the processor of this embodiment also includes A
AccuL router that stores data calculated by L U;
It is equipped with a register that temporarily stores data on the internal bus line, a data output cover sofa that can be connected to an external data bus, etc.

Here, one instruction execution cycle in the processor of this embodiment is a cycle that can be executed based on one instruction fetch by the program counter PC. The execution cycle of the cutting command is not particularly limited, but the data memory DM
an arithmetic processing instruction execution cycle that includes read/write operations, a transfer instruction execution cycle that transfers data between various registers or between registers and memory, and conditional jumps and null operations that change the instruction sequence within a program. An instruction fetch is performed at the beginning of each instruction execution cycle, which includes a jump instruction execution cycle such as a conditional jump, but as mentioned above, the data path from the program counter PC to the decoder is used for instruction fetching. Because it is dedicated, each instruction execution cycle is performed successively in a so-called pipeline process, making it possible to process data at high speed.

In FIG. 1, PR connects the internal bus line BL to a level J'6 lower than the power supply voltage level and lower than the circuit ground level.
This is a precharge circuit for precharging to a level such as a high intermediate level at a predetermined timing. Such a precharge circuit P R is connected in series between one power supply terminal Vdd of one circuit and the internal bus line B L, and is connected in series between one power supply terminal Vdd of one circuit and the internal bus line B L. A P-channel type MO8FET Q5 receives the gate 1- and a P-channel type MO8FE whose drain is coupled to the gate is diode-connected.
'I'Q6 and ground terminal G which is the other power supply terminal of one circuit
nd and the internal bus line RL. N-channel type MO8FET Q7 whose gate receives control number 48 φρr output from controller 0ONT and so-called diode-connected N-channel type MOS F E
It consists of TQ8. The above control signal φpr
and φpr are, although not particularly limited to, the internal bus line R
In one instruction execution cycle that includes the process of inputting and outputting data via L, the level is set to low level and high level for a predetermined period of time from the instruction fetch stage, which is the beginning of the process. Therefore, during that period, MO3F'ETQ
5 and Ql are turned on, thereby causing the internal bus line B'L to become a MO
Based on the on-resistance of each of the 5FETs Q6 and Q8, it is possible to precharge the power supply voltage to a potential level obtained by dividing the power supply voltage, in other words, to a level intermediate between the power supply pressure level and the ground level. Here, according to this embodiment, the intermediate level achieved by the precharge circuit PR is a level near the logic threshold voltage of the clocked inverter circuits I nVl and I nV2, and
Or when the operation of the output stage consisting of Q3 and Q4 is started, the internal bus line B by MO8FET Q2 or Q4 is
Discharge completion time to the ground level of L and MO8
F' ET Q Internal bus line B by L or Q3
The level is set such that the time required to complete charging to the L power supply voltage level is approximately equal.

Next, the operation of the above embodiment will be explained.

If the arithmetic processing instruction execution cycle of the processor includes a process of outputting data via the internal bus line BL, in the instruction fetch stage which is the first stage of the instruction execution cycle, the control signals φρr and φpr
are set to a low level and a high level, respectively, thereby precharging the internal bus line RL to an intermediate level as described above. At this time, the output stage MOSFET
QI to Q4 are turned off. That is, the output stage is placed in a high output impedance state.

Case 1: When the internal bus line BL is set to low level through processing in the instruction execution cycle, for example, when high level data output from the execution unit ALU is transferred to the data memory DM, first the execution unit A L tJ The above MO5FE
At the same time that TQ2 is turned on, MOSFETQI is turned off, and the internal bus line l'3L is discharged via MO8FETQ2 that is on.

Such a discharge operation by MO8FETQ2 can be performed by simply changing the internal bus line BI from the intermediate level of the power supply voltage to the ground level, so it is easier to perform the discharge operation than when forcing the level of the internal bus line BL from the power supply voltage level to the ground level. , the discharge operation is performed at high speed. Therefore, in the transfer operation of high-level data, the low level determination timing of the internal bus line BL is brought forward, so that the inversion of the clocked inverter circuit I nv2 connected to the input terminal of the data memory DM is also performed at high speed, and the high-level data is transferred at high speed. Transfer is accomplished.

Further, when the internal bus line BL is set to high level through processing in the instruction execution cycle, for example, when low level data output from the data memory DM is transferred to the execution unit ALU, first the data memory D
The above MO5 is determined by the low level data output from M.
FETQ3 is turned on and MOSFETQ
4 is turned off and its on state MOSFETQ3
The internal bus line BL is charged via the internal bus line BL.

The internal bus line BL is brought from the intermediate level to the power supply voltage level by this charging operation by MOSFET Q4, but the intermediate level preset for the internal bus line BL is MOSFET Q 2 or Q as described above.
Since the time required to complete discharging the internal bus line BL to the ground level by MOSFET QI or Q3 is approximately equal to the time required to complete charging the internal bus line BL to the power supply voltage level by MOSFET QI or Q3, the charging i! ! The J+ operation is performed at high speed in approximately the same time as the above-mentioned discharge operation. Therefore, even in the transfer operation of low level data, the internal bus line 1
．． Since the high level determination timing of 1L is achieved at the same time as the above-mentioned high level data transfer operation, the execution unit A
Inversion of the clocked inverter circuit I nv connected to the input terminal of L tJ is also performed at high speed, and high-speed transfer of low-level data is also guaranteed.

According to the above embodiment, the following effects can be obtained.

(1) At the first stage of the instruction execution cycle, the internal bus line BL is precharged to the intermediate level of the power supply voltage, so the low level determination timing of the internal bus line BL is brought forward, and the intermediate level is OSFE'
Completion time of discharging internal bus line BL to ground level by I'Q2 or Q4 and MOSFETQ
If the charging completion time of the internal bus line Br to the power supply voltage level by I or Q3 is set to a level that is approximately equal to the time, the high level determination time of the internal bus line BL is also the same as the low level determination time described above. Guaranteed high speed.

(2) Since the internal bus line is precharged to the intermediate level of the power supply voltage, the MOSFET I'' discharges the precharged internal bus line and charges the precharged internal bus line to the power supply voltage level. There is no need to increase the size of MO8F'ETs, and the effect of undesired capacitive loading of internal bus lines due to these MOSFETs will significantly delay the completion of discharge and charge operations of precharged internal bus lines. Never.

(3) From the effects (1) and (2) above, it is possible to achieve faster data transfer.

(4) In particular, connect the output terminals of ALU, data memory DM, etc. to internal bus line B like a CMOS inverter circuit.
L is connected to the internal bus line BL via a switch element capable of supplying a power supply voltage and a discharge switch element, and when a low-level data transfer operation is performed, the charge switch element included therein is turned on. If a configuration is adopted in which the internal bus line BL is charged to the power supply voltage level, the clocked inverter circuit Inv and I connected to the input terminals of the ALU, data memory DM, etc.
It is possible to improve the margin for process variations with respect to the threshold voltage of an input circuit such as nV2.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and can be variously modified within the scope of the gist thereof.

For example, the precharge circuit in the above embodiment has a diode-connected MOS as a resistance element included therein.
Although FET is used, the present invention is not limited to this, and other resistance elements such as polysilicon resistance can be used. Furthermore, the positions where the resistive elements are arranged are not limited to those in the above embodiments, and any positioning that can divide the power supply voltage at a predetermined ratio is sufficient, and the resistive elements are directly connected to a pair of power supply terminals of the circuit. It may be arranged like this.

Further, in the above embodiment, the output terminals of the ALU, data memory DM, etc. are connected to the internal bus line B via a switch element capable of supplying a power supply voltage to the internal bus line BL and a discharge switch element, like a CMOS inverter circuit.
When a low-level data transfer operation is performed, a charging switch element included in the charging switch element is turned on to charge the internal bus line BL to the power supply voltage level. However, the present invention is not limited to this. Alternatively, the connection can be made only through the discharge switch element. In that case, the intermediate level to be achieved by the precharge circuit is
Clocked inverter circuit I coupled to input terminals such as
It is necessary to maintain a stable level equal to or higher than the logic threshold voltage of the input circuit such as nVl and InV2. In such a case, such clocked inverter circuits Inv□ and In
Although the process variation margin is reduced relative to the logic threshold voltage of input circuits such as 92, internal bus line charging is no longer required when low-level data is transferred, making it possible to further speed up data transfer. .

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a digital signal processing processor, which is the technical field behind the invention, but the invention is not limited to this, and the invention is not limited to this. The present invention can be applied to various data processing devices such as processors that do not have the same technology.

The present invention can be applied at least to conditions where internal bus lines are precharged.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, a MOSFET that functions as a switch element is connected to each of a pair of power supply terminals and an internal bus line of the circuit.
and a diode-connected MOS that functions as a resistance element.
By providing a precharge circuit consisting of a MO8FET connected in series and precharging the internal bus line to a level lower than the power supply voltage level and higher than the ground potential, the bus line can be set up without increasing the size of the discharge MO8FET. High speed data transfer on the internal bus line can thereby be achieved since a fast discharge of the line is possible and the undesired capacitive loading of the internal bus line due to the discharge MO5FET can also be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a part of a digital signal processing processor according to an embodiment of the present invention. PR...precharge circuit, Q5 and Q7...switch element, Q6 and Q8...resistance element, C0NT...
- Controller 1 - Roller, ALU...Execution unit, DM...Data memory. Figure 1

Claims (1)

Claims: 1. A data processing device having an internal bus line, the data processing device comprising a precharge circuit for precharging the bus line to an intermediate level of the power supply voltage. 2. Claims characterized in that the precharge circuit comprises a switch element and a resistor element connected in series between each of a pair of power supply terminals of the circuit and an internal bus line. The data processing device according to item 1. 3. The data processing device according to claim 2, wherein the switching element is a MOSFET, and the resistance element is a diode-connected MOSFET.