JPH0616586B2 - N OR circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multistage logic circuit, and more particularly to a circuit configuration method suitable for a dynamic multistage logic circuit in which a precharge system is introduced.

[Background of the Invention]

A PLA or the like conventionally used as a multi-stage logic is a multi-stage logic having a NAND structure shown in FIG. 1 or a NOR shown in FIG.
It is composed of multi-stage logic. If this multi-stage logic is constructed by a static logic circuit, a large number of circuits for holding levels are required, resulting in an increase in chip area and power consumption. Therefore, a dynamic multi-stage logic circuit has been often used, and in particular, a precharge system has been adopted in order to reduce the area and speed up. However,
In the precharge system, various types of clock signals are required to control the precharge period. However, in the LSI, it is difficult to generate many types of clock signals because the types of input clocks are limited.

Under such circumstances, the domino type multi-stage logic circuit shown in FIG. 3 is shown (Bernard T. Murphy et al,
"A CMOS32b Single Chip Microprocessor", SESSION XV
I: VLSI LOGIC, 1981 IEEE ISSCC, p.230-231, (1981 2
(May 20)). The operation of the NOR logic multi-stage logic circuit using the domino method will be described with reference to FIGS. While the clock signal 1 is L, P channel MOS
Since 2 and 3 are turned on and N channel MOSs 9 and 12 are turned off, the outputs 4 and 5 of the NOR logic 8 and 11 are H respectively.
It is precharged to the level. The input signal 7 is determined during this precharge period.

When clock signal 1 goes high, P channel MOS
2, 3 are turned off, and N channel MOS9 is turned on
Then, the NOR logic 8 operates. If the inputs 7 are all L, the output 4 holds H, otherwise the output 4 transits to L. The NOR logic 11 in the next stage has a clock signal 1 in order to prevent the inputs 4 and 6 from operating until they are determined.
A means for delaying is provided. NOR logic 11 input 4,
The propagating signals 10 of the clock signal 1 delayed until the time point 6 is determined so that they become H at the time point when they are determined,
NOR logic 11 operates.

In the logic circuit which introduced the precharge system. The smaller the number of NMOSs connected in series between the output line and GND, the faster the operation. That is, the time for discharging the charges held on the output line is the operation time of the logic circuit. Therefore, the closer the resistance value of the discharge system path is, the faster the operation time is. for that reason,
When increasing the speed of a logic circuit, the NOR structure is more advantageous than the NAND structure for the logic structure.

The domino system shown in FIG. 3 satisfies the conditions for speeding up with respect to the above points. However, in order to further increase the speed, the following points become a problem. In the domino system, grounding is prohibited by the N-channel MOSs 9 and 12 so that the electric charges stored on the output lines 4 and 5 during the precharge period do not leak until the logic operation time is reached. Therefore, in a simple NOR configuration, the output line and GND
While only one NMOS is connected in series between and,
I need two NMOSs. As a result, in the precharge period, not only the drain capacitance of the N-channel MOS constituting the NOR logics 8 and 11 on the output lines 4 and 5, but also the source capacitance and the N-channel MOS on the ground side.
Precharge is also performed for the drain capacitances of 9 and 12. Therefore, N between the output line and GND line
The time required for precharging is slower than that of a NOR circuit having only one channel MOS. In addition, the amount of charge that must be discharged during the operation time of the logic circuit also increases.

The domino NOR configuration logic circuit shown in FIG.
An example applied to A is shown in FIG. The clock signal 1 in FIG. 3 is the clock signal 75, and the output 10 of the delay means is the signal 7.
Corresponds to 6. The input signal 60 is a P channel MOS 62.
An inverter type buffer composed of the N-channel MOS 63 and the N-channel MOS 63 inputs the signal to the gate of the N-channel MOS 64 corresponding to the NOR logic 8 in FIG. In FIG. 3, the P-channel MOS 2 corresponds to the P-channel MOS 74, and the N-channel MOS 9 corresponds to the N-channel MOS 65. Further, a P channel MOS 69 is provided for the P channel MOS 3 and an N channel M is provided for the N channel MOS 12 in FIG.
OS71 is supported. NOR logic 11 in FIG.
The N-channel MOS 70 shown in FIG. 8 is used. The source capacitance and the drain capacitance of the MOS transistor, which are factors that delay the precharge time and the discharge time for the logic operation, are represented by 68 in FIG.

Generally, the NOR logic constituted by the N channel MOSs 64 and 70 occupies most of the circuit scale of the PLA shown in FIG. In order to reduce the circuit area of the PLA, the N-channel MOS 6 which occupies most of this circuit is used.
It is effective to make the transistor sizes of 4, 70 as small as possible. However, if the transistor size is reduced, the precharge and discharge times of the output line 77 and the like become longer due to the influence of the capacitance 68 in FIG. Therefore, in order to make the domino NOR configuration logic circuit shown in FIGS. 3 and 8 into a circuit having a higher speed and a smaller area, an N-channel MOS connected in series between the output line and GND is used. It is necessary to remove the capacity 68, which has been an obstacle to speeding up, by setting the number of 1 to 1.

[Object of the Invention]

An object of the present invention is to realize a high-speed, small-area multi-stage logic circuit. Therefore, it is a precharge type NOR logic circuit that can be continuously operated by only one clock signal, and it is a series N connected between the output line and GND.
It is to provide a circuit in which the number of channel MOSs is 1.

[Outline of Invention]

When the output line is precharged, the driver circuit sets the signal input to the N-channel MOS gate of the NOR logic to the L level to prevent the output line from being grounded. N connected in series between
The number of N-channel MOS of OR logic is set to 1. As a result, even if the transistor size of the N-channel MOS forming the NOR logic is reduced to some extent, it is possible to realize a multi-stage logic circuit that can operate at high speed. Further, since the driver circuit that controls the timing of the input signal and inputs it to the NOR logic is small in the entire circuit, it can be speeded up by increasing the transistor size. It is something.

In the above circuit, the signal line designating the precharge period is delayed by using the delay means, and the next stage NO connected in series is connected.
By using the R logic signal line, it is possible to configure a multi-stage logic having the same function as the domino system.

In the above circuit, the signal line designating the precharge period is delayed by using the delay means, and the next stage N is connected in series.
By using a signal line of OR logic, it is possible to configure a multi-stage logic similar to the domino method.

Example of Invention

An embodiment of the present invention will be described below with reference to FIGS.

In FIG. 5, the first-stage NOR logic is N-channel MOS3.
It is composed of 3, 34 and 35. The input of this logic is P
It is the output 26 of the driver composed of the channel MOSs 30 and 15 and the N channel MOS 16, and the output is the potential of 17. The P channel MOS 13 is used for precharging the output terminal. Input to NOR logic 26
, Etc. are all "L", N channel MOS 33, 3
Since the outputs 4 and 35 are in the OFF state, the output 17 is not grounded and the precharged charges are not discharged, so that the output H is maintained at H. Output 1 when even one of the inputs becomes "H"
7 is grounded and the output transitions to L. The next NOR logic is composed of N-channel MOS 37, 38, 39.

The clock signal line 25 specifies the precharge period. Period when clock signal 25 is at H level (see FIG. 6)
Output 17 is precharged. That is, the level of the signal 25 is inverted by the inverter 32, and the L level is input to the P channel MOS 13, so that 13 is turned on and electric charge is supplied to 17. On the other hand, the signal 25 is also input to the P-channel MOS 15 and the N-channel MOS 16 of the driver circuit that inputs to the NOR logic. During the precharge period, since the signal 25 is H, the P channel MOS15 is in the OFF state, the N channel MOS16 is in the ON state, and the N channel MOS16 is in the ON state.
The input 26 to the OR logic is grounded and becomes L level. Therefore, the N channel MOSs 33 and 3 that form the NOR logic
4, 35 are turned off to prevent the output 17 from being grounded. The signal 25 is delayed by the delay means, and is also input to the next-stage NOR logic as the signal 23. Next stage N
The OR logic has the same configuration as the NOR logic of the first stage, and precharge is similarly performed at a time slightly delayed from the first stage. When the precharge is completed, the outputs 17 and 28 of the respective NOR logics become H level. The first-stage NOR logic starts its operation when the clock signal 25 goes low.
Before that, the signal 29 to be input to the first-stage NOR logic is fixed. When the clock signal 25 becomes L level, H is input to the P channel MOS 13 through the inverter 32, and the connection between the output 17 and the power supply is cut off. On the other hand, the P channel MOS 15 of the driver is turned on and the N channel MOS 16 is turned off. At this time, if the input 29 to the driver is at the H level, the P channel MOS 30 becomes O.
Since the FF state is set, the driver output 26 holds L. On the other hand, if 29 is at L level, P channel MOS30
Becomes an ON state, the output 26 transits to H through the P channel MOSs 30 and 15, the N channel MOS 33 constituting the NOR logic becomes an ON state, and the output 17 transits to the L level. At this time, the driver input 29 and the first stage NO
Looking at the relationship between the output 17 of the R logic 18 and the inverted signal 20 after passing through the inverter 19, all the signals 29 are "H".
When it is at level, the signal 20 becomes "L" level, and when even one of the signals 29 becomes "L" level, the signal 20 becomes "H" level, so it is logically equivalent to the NAND configuration shown in FIG. Becomes

Until the output 17 of the first stage NOR logic 18 is confirmed, the next stage N
A means for delaying the clock signal 25 is provided so that the OR logic 24 does not operate.
Logic driver section P channel MOS21, N channel M
A signal obtained by inverting the level of the OS 22 and the delay signal 23 by the inverter 36 is used as the P channel MOS 14 for precharge.
To enter. The operation of the second-stage NOR logic 24 is also the first-stage NOR
Similar to the logic, the P-channel MOS 14 for pre-charge is in the OFF state, the P-channel MOS 21 in the driver section is in the ON state, and the N-channel MOS is in the operating time.
22 is in the OFF state, and when the driver inputs 20 are all at the "H" level, the output 28 holds the H level,
20 becomes L level.

An example in which the multistage logic circuit configured in FIG. 5 is applied to a PLA is shown in FIG. The clock signal 25 corresponds to the signal 55, and the delayed signal 23 corresponds to 56. 42 corresponds to the P channel MOS 30 of the first-stage driver, and 43 corresponds to 15. 45 corresponds to the N channel MOS 16. Further, 44 corresponds to the N-channel MOS 33 and the like which configure the NOR logic. P channel MOS13 for precharge
Corresponds to 54. The output of the first-stage NOR logic is 57,
The inverter 19 corresponds to 46. 47 for the P channel MOS31 of the next stage driver, 48 for 21 and N
51 corresponds to the channel MOS 22. 50 corresponds to the N-channel MOS 37 and the like which form the NOR logic of the next stage. 49 corresponds to the P channel MOS 14 for precharge. The circuit configuration is exactly the same as the multi-stage logic shown in FIG.

〔The invention's effect〕

According to the present invention, the multi-stage logic circuit uses only one clock signal, and the N of the pre-charge type N channel MOS is used.
An OR logic M is connected in series between the output line and GND.
Since the number of OSs can be set to 1, it is effective in speeding up the circuit operation.

[Brief description of drawings]

1 and 2 are explanatory diagrams of multistage logic, FIG. 3 is a conventional domino type multistage logic circuit diagram, FIG. 4 is its operation timing diagram, FIG. 5 is a multistage logic circuit diagram of the present invention, and FIG. FIG. 6 shows the operation timing diagram, and FIG. 7 shows the multi-stage logic circuit of the present invention as a PL.
FIG. 8 is a circuit diagram when applied to A, and FIG. 8 is a circuit diagram when a conventional domino type multi-stage logic circuit is applied to PLA. 8, 11, 18, 22 and 44, 50 ... NOR logic circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshimune Hagiwara 1-280, Higashi Koikekubo, Kokubunji, Tokyo Metropolitan Research Center, Hitachi, Ltd. (72) Inventor Hideo Nakamura 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Laboratory (72) Inventor Hiroyuki Masuda 1479, Kamimizumoto-cho, Kodaira-shi, Tokyo In-house Hitachi Micro-Computer Engineering Co., Ltd. (56) Reference JP-A-52-67557 (JP, A)

Claims (2)

[Claims] 1. A plurality of N-channel first MOSs forming a drain / source path are connected in parallel between an output line and ground, and a drain / source path is provided between the output line and a power supply. Of the P-channel second MOS connected to each other, and the gates of the plurality of N-channel first MOSs connected in parallel to each other respond to respective input signals to be input, A gate of the MOS is a NOR circuit configured to respond to a precharge control signal, and a third N-channel circuit that forms a drain / source path between each gate of the first N-channel MOS and the ground. Of the P-channel fourth MOS which forms a drain / source path between each gate of the N-channel first MOS and the power supply in response to the precharge control signal. Contact And the gate thereof responds to the respective input signals, forms a drain-source path between each gate of the N-channel first MOS and the power supply, and connects the P-channel fourth MOS drain. Connecting a fifth P-channel MOS that forms a series path with the source path, the gate of which has a plurality of control circuits responsive to the precharge control signal for each of the input signals; During the precharge period when the signal level makes the P-channel second MOS conductive, the N-channel third MOS becomes conductive while the P-channel fifth MOS becomes non-conductive, The first M of the N channels are independent of the respective input signals.
In the non-precharge period in which the potential of each gate of OS is controlled to a low level voltage and the level of the precharge control signal makes the second MOS of the P channel nonconductive,
By turning off the N-channel third MOS while turning off the P-channel fifth MOS,
A NOR circuit characterized in that the potential of each gate of the N-channel first MOS responds to each of the input signals via the P-channel fourth MOS. 2. In constructing the NOR circuit in multiple stages,
A delay circuit for delaying the precharge control signal of the NOR circuit of the first stage is provided, and the delayed precharge control signal is used as a precharge control signal of the NOR circuit of the second stage. The NOR circuit according to the first section of the above.