JP2544732B2 - Semiconductor logic circuit - Google Patents

Description

The present invention relates to a read-only memory (hereinafter referred to as ROM) having an AND circuit and an OR circuit, and a PLA (Programmable L).
It relates to a semiconductor logic circuit such as an ogic array circuit.

(Prior Art) Conventionally, as a technology in such a field, for example, there is one as shown in FIG. Hereinafter, the configuration will be described.

FIG. 2 shows a configuration example of a conventional semiconductor logic circuit and is a circuit diagram of a synchronous PLA circuit which operates with one clock pulse.

Here, operating with one clock pulse means a circuit that operates by dividing a half cycle period of a clock pulse that is synchronously input into a precharge period and a signal propagation period, and as such a circuit, for example, ROM or PLA
There is a circuit. That is, RO that operates with one clock pulse
The M or PLA circuit is a circuit that can obtain a stable output within the time of one cycle of the clock pulse.

The PLA circuit of FIG. 2 includes a gate circuit 1 for an input signal and a pull-up circuit 1 for an AND circuit (hereinafter referred to as an AND circuit).
0, AND circuit 20, signal transfer gate circuit 30, pull-up circuit 40 for OR circuit (hereinafter referred to as OR circuit), and OR circuit
Equipped with 50.

The input signal gate circuit 1 is a circuit that takes in the input signals IN1 and IN2 in synchronization with the clock pulse φ, and inverts the inverters 2, 3− for inverting the clock pulse φ and the input signals IN1 and IN2.
1, 3-2 and negative input AND gates 4-1 to 4-4 that take the NAND of the outputs of these inverters 2, 3-1 and 3-2. The first pair of signal lines 21-1, 21-2 and 21-3, 21-4 are connected to the output side of -4.

The AND circuit pull-up circuit 10 includes a first signal line 21-1.
21-4 is a circuit for pulling up the second signal lines 22-1 to 22-4 intersecting to 21-4 to the potential of the power supply voltage VDD in synchronization with the clock pulse φ. -4 connected to P-channel MOS transistors (hereinafter referred to as PMOS) 11-1 to 11-4.

The AND circuit 20 is a circuit that takes the logical product of the input signals IN1 and IN2, and the first signal lines 21-1 to 21-4 and the second signal line 22-
First channel N-channel MOS transistor (hereinafter referred to as NMOS) 23-11, 23-13, 23-22, 23-24, 23-31, 23, which is connected to the intersection of 1 to 22-4. −32,23−
It has 43, 23-44.

The signal transfer gate circuit 30 is a circuit that transfers the signals on the second signal lines 21-1 to 22-4 to the OR circuit 50 in synchronization with the clock pulse φ, and is a delay circuit that delays the clock pulse φ by a predetermined time. 31 and an AND gate 32 that obtains the logical product of this delay circuit output signal and the clock pulse φ, and this AND gate 32
AND gates 33-1 to 33-4 which take the logical product of the output signal of the second signal line and the second signal line 22-1.

The OR circuit pull-up circuit 40 is a circuit that pulls up the third signal lines 51-1 to 51-3 to the potential of the power supply voltage VDD in synchronization with the clock pulse φ, and the third signal line 51-1 ~
It has PMOSs 41-1 to 41-3 connected to 51-3.

The OR circuit 50 is a circuit that takes the logical sum of the output signals of the AND gates 33-1 to 33-4, and outputs the output signals OUT1 to OUT3 by the third signal lines 51-1 to 51-3 and the AND gate 33. -1 to 33
-4 fourth signal lines 52-1 to 52-4 connected to the output side
The second transistor NM connected at the intersection with
It has OS53-11, 53-23, 53-24, 53-32, 53-33.

FIG. 3 is a circuit diagram showing a configuration example of the delay circuit 31 in FIG.

This delay circuit 31 includes inverters 31-1 connected in series.
31-4 and capacitors 31-5 and 31-6 branched and connected thereto, the circuit outputs the clock pulse φ with a delay of a predetermined time.

FIG. 4 is a timing chart showing the operation of FIG. 2, and the operation of FIG. 2 will be described with reference to this figure.

First, during the precharge period when the clock pulse φ is at L level, the PMOS 11-1 to 11-4, 41-1 to 41-3 are turned on, and the second signal lines 22-1 to 22-4 and Three
Signal lines 51-1 to 51-3 are precharged to H level. At this time, in order to eliminate the through current through the NMOS 23-11, 23-13 or 53-11, the AND gates 4-1 to 4-4, 32 are used to make the first signal lines 21-1 to 21-4.
And the output side of the AND gate 32 is set to the L level, and the NMOS 23-11,
Turn off 23-13 and 53-11.

Next, in the signal propagation period in which the clock pulse φ is at the H level, the PMOSs 11-1 to 11-4 and 41-1 to 41-3 are turned off and the precharge is completed. At this time, at the same time, for example, the input signal IN1 is transmitted through the AND gate 4-1 to the first
Of the NMOS 23-11, 23-13,
By selecting the off state, the second signal lines 22-1 to 22-1
The potential of 22-4 is determined and input to the AND gates 33-1 to 33-4. The AND gates 33-1 to 33-4 wait for the potential of the second signal lines 22-1 to 22-4 to be determined before
Signals on the signal lines 22-1 to 22-4 of the fourth signal line 52-1
Tell ~ 52-4. AN controls this timing.
A D gate 32 and a delay circuit 31.

When the signal lines 52-1 to 52-4 in FIG. 4 are at the H level,
For example, the NMOS 53-11 is turned on and the third signal line 51-
1 output signal OUT1 goes to L level, and the fourth signal line
When 52-1 to 52-4 are at L level, for example, NMOS53-11
Is off, the precharged H-level output signal OUT1 is output from the third signal line 51-1 to complete the operation for one cycle.

5 and 6 show an example of the configuration of another conventional semiconductor logic circuit. FIG. 5 is a circuit diagram of an asynchronous resistance load PLA circuit, and FIG. 6 is an asynchronous complementary PLA circuit. It is a circuit diagram of.

In the PLA circuit of FIG. 5, a gate circuit 1A made up of inverters 5-1 and 5-2 and a pull-up circuit 10A made up of load resistors 12-1 to 12-3 are connected to an AND circuit 20 and further loaded. A pull-up circuit 40A composed of resistors 42-1 to 42-3,
The second signal lines 22-1 to 22-4 are connected to the OR circuit 50. When the input signals IN1 and IN2 are supplied to the inverter 1A, the input signals IN1 and IN2 are logically ANDed by the AND circuit 20 and further ORed by the OR circuit 50 to output the desired output signals OUT1 to OUT3 is output. Here, for example, AND circuit 2
At 0, three of the four second signal lines 22-1 to 22-4
A through current always flows through the book.

In the PLA circuit of FIG. 6, a gate circuit 1B composed of inverters 6-1 and 6-2 and a pull-up circuit 10A composed of PMOSs 13-1 to 13-8 are connected to an AND circuit 20 and further a PMOS 43.
The pull-up circuit 40B including -1 to 44-5 and the second signal lines 52-1 to 52-4 are connected to the OR circuit 50.
Here, the PMOS in the pull-up circuit 10B and the NM in the AND circuit 20
Complementary MOS transistor (hereinafter referred to as CMOS) is configured with OS, and the PMOS in pull-up circuit 40B and OR circuit 5
The CMOS is composed of the NMOS in 0. Then, after the AND signals of the input signals IN1 and IN2 are ANDed by the AND circuit 20, the OR circuit 50
Is ORed to obtain desired output signals OUT1 to OUT3.

(Problems to be Solved by the Invention) However, the semiconductor logic circuit having the above configuration has the following problems. In the synchronous PLA circuit of FIG. 2, A
Since the circuit configurations of the ND circuit 20 and the like and the delay circuit 31 are largely different, the signal delay time thereof also changes due to the change of the power supply voltage VDD and the like. Therefore, it is impossible to properly set the delay time of the delay circuit 31. Even if the delay times of the AND circuit 20 and the delay circuit 31 vary, in order to perform a reliable operation, for example, the delay time of the delay circuit 31 is set to the AND circuit 20.
It is necessary to set it larger than the signal delay time of. However, if the delay time of the delay circuit 31 is set to be large, there arises a problem that the operation speed is reduced.

In the asynchronous resistance load type PLA circuit of FIG. 5, there is no problem of difficulty in setting the delay time, but since a direct current always flows between the power supply and the ground, the current consumption increases. In particular, in order to realize high-speed operation, load resistors 12-1 to 12-12
Since it is necessary to reduce −4, 42-1 to 42-3 and reduce the ON resistance of the NMOS in the AND circuit 20 and the OR circuit 50, there is a problem that the current consumption is further increased.

In the asynchronous complementary PLA circuit of FIG. 6, the PLA of FIG.
As with the circuit, there is no problem of difficulty in setting the delay time, but the number of elements required in the pull-up circuits 10B and 40B is large, and PMOSs 13-1 to 13-1 connected in series according to the number of inputs
Since the number of 13-8, 43-1 to 43-5 increases and the input load capacity also increases, there are problems that the operation speed is slow and the number of elements is large.

The present invention has the following problems.
(EN) A semiconductor logic circuit which solves the problems of delay time setting, low speed operation and high power consumption.

(Means for Solving Problems) In order to solve the above problems, the present invention provides a synchronous semiconductor logic circuit including an AND circuit, an OR circuit, a delay circuit, and a gate circuit. .

The AND circuit includes a plurality of first signal line pairs to which a plurality of input signals and their inverted signals are input in synchronization with a clock pulse, and a pull-up in synchronization with the clock pulse, and the first signal line. A plurality of second signal lines intersecting the pair, the plurality of first signal line pairs, and the plurality of second signal lines
A plurality of first transistors connected to a desired intersection with the signal line, one end of which is connected to the second signal line, and the gate of which is connected to either one of the first signal line pair. A plurality of first transistors, the plurality of first transistors
Is a circuit for outputting a logical product of a desired signal among the plurality of input signals and its inverted signal from the second signal line by turning on / off the transistor.

The OR circuit is supplied with a plurality of third signal lines that are pulled up in synchronization with the clock pulse and a signal that corresponds to the output signal of the AND circuit, and that intersects with the third signal line. A plurality of second signal lines connected to desired intersections of the plurality of fourth signal lines and the plurality of third signal lines and the plurality of fourth signal lines;
A plurality of second transistors each having one end connected to the signal line and a gate connected to a fourth signal line, and the AND operation is performed by turning on / off the plurality of second transistors.
A circuit for outputting a logical sum of desired signals among the signals corresponding to the output signals of the circuit from the third signal line.

The delay circuit is pulled up in synchronization with the clock pulse and crosses a fifth pair of the first signal lines.
Signal line and at least one of the plurality of first signal line pairs intersects the first signal line pair and the fifth signal line, and controls the potential of the fifth signal line. Do third,
A fourth transistor, one end of which is connected to the fifth signal line and one end of which is connected to the fifth signal line, and whose third gate is connected to one of the first signal line pair, respectively. , A fourth transistor having a gate connected to the other of the first signal line pair, and a delay capacitive element connected to the fifth signal line, and delaying the clock pulse by a predetermined time. It is a circuit that outputs a signal.

The gate circuit has an input connected to the delay circuit and transfers a signal corresponding to the output signal of the AND circuit to the fourth signal line in synchronization with a signal obtained by delaying the clock pulse by a predetermined time. It is a circuit to do.

(Operation) According to the present invention, since the synchronous semiconductor logic circuit is configured as described above, a plurality of input signals and their inverted signals are input to the plurality of first signal line pairs in synchronization with the clock pulse. Then, the plurality of first transistors are turned on and off by the signal on the first signal line pair, and the third transistor is turned on and off.
Alternatively, one of the fourth transistors is turned on. By turning on and off the plurality of first transistors, a logical product of a desired signal among the input signal and the inverted signal is output from the plurality of second signal lines and sent to the gate circuit. Further, by turning on one of the third and fourth transistors, the potential of the fifth signal line is controlled, and after the potential (signal) is delayed by the capacitor, the gate circuit is driven. To be done.

When the gate circuit is driven, a signal corresponding to the output signal of the second signal line is transferred to the plurality of fourth signal lines,
The plurality of second transistors are turned on and off. Then, by turning on and off the plurality of second transistors, among the signals corresponding to the output signal of the AND circuit,
The logical sum of desired signals is output from the plurality of third signal lines.

(Embodiment) FIG. 1 shows a semiconductor logic circuit showing an embodiment of the present invention, and is a circuit diagram of a synchronous PLA circuit having a CMOS structure which operates with one clock pulse. The same elements as those in the conventional FIG. 2 are designated by the same reference numerals.

This PLA circuit differs from the conventional PLA circuit of FIG. 2 in that
The signal transfer gate circuit 30 of FIG.
31 is replaced with a signal transfer gate circuit 30A composed only of AND gates 32, 33-1 to 33-4, and the delay circuit 100 is provided on the AND circuit 20 side instead of the delay circuit 31. That is.

This delay circuit 100 has a PMOS 101 whose source is supplied with a power supply voltage VDD and whose gate is supplied with a clock pulse φ.
The fifth signal line 102 is connected to the drain of the MOS 101. The fifth signal line 102 has a third transistor N
The drain of the MOS 103-1 and the NMOS which is the fourth transistor
103-2 is connected to the drain of each of these NMOS103−
The source of 1,103-2 is grounded and one of the NMOS103
The gate of -1 is connected to one of the first signal line pairs 21-1 and the other
The gate of the NMOS 103-2 is connected to the other 21-2 of the first signal line pair. Here, NMOS 103-1, 103-2
Is a combination such that one of them becomes H level during the signal propagation period, and usually the combination can be easily set. Further, the fifth signal line 102 is connected to the first signal lines 21-3, 21-
Capacitor elements 104-1 and 104 for delay are provided at the intersections with 4 respectively.
-2 is connected, these capacitance elements 104-1 and 104-2 are grounded, and the fifth signal line 102 is connected to the AND gate 32 of the signal transfer gate circuit 30A via the inverter 105.

7 (1), (2) to 9 (1), (2) are AN
3 is a diagram showing a configuration example of element shapes in a D circuit 20 and a delay circuit 100. FIG.

FIG. 7 (1) is a wiring diagram of the intersection of the first and second signal lines 21-1 to 21-4, 22-1 to 22-4 in the AND circuit 20,
FIG. 7 (2) is its structural drawing. As shown in FIG. 7B, for example, in the lateral direction on the semiconductor substrate 200, a strip-shaped N-type active layer 201 and first signal lines 21-1 to 21-4 are provided.
And a strip-shaped polysilicon layer 202 that forms the second signal line 22-1 to 22-4 or the metal that forms the fifth signal line 102 in the vertical direction on the polysilicon layer 202. The layer 203 is formed.

8 (1) shows the NM in the AND circuit 20 and the delay circuit 100.
A wiring diagram of OSs 23-11 to 23-44, 103-1 to 103-2, and FIG. 8 (2) are structural diagrams thereof. In FIG. 8 (2), an N-type active layer 201 is provided in the vertical direction in the N-type active layer 201 extending in the horizontal direction.
Are connected to the metal layer 203 through contacts 205. Here, the N-type active layer 201 is a source, the N-type active layer 204 is a drain, and the polysilicon layer 202 is a gate.

9 (1) shows the capacitors 104-1 and 104-2 in the delay circuit 100.
FIG. 9 (2) is a wiring diagram thereof. In FIG. 9 (2), one N-type active layer 204A is formed in the semiconductor substrate 200 separately from the other N-type active layer 201, and the capacitive elements 104-1 and 104-2 are the N-type active layers. It is formed as a junction capacitance of 204A and is connected to the fifth signal line 102 formed of the metal layer 203 through the contact 205. The capacitive elements 104-1 and 104-2 of FIG. 9 (2)
Is the NMOS 23-11 to 23-44, 103-1, 103- of FIG.
It has a shape similar to 2.

FIG. 10 is a time chart showing the operation of FIG.
The operation of FIG. 1 will be described with reference to FIG.

First, during the precharge period when the clock pulse φ is at the L level, the PMOSs 11-1 to 11-4, 41-1 to 41-3, 101 are turned on, and the second signal lines 22-1 to 22-4 and the third Signal line
51-1 to 51-3 and the fifth signal line 102 thereof are connected to the power supply voltage V
Precharged by DD and becomes H level. At this time, NMOS 23-11 to 23-44,53-11 to 53-33,103-1,103-
AND gate 4-
The first signal lines 21-1 to 21-4 and 1 to 4-4 and 32 are used.
The output side of the AND gate 32 is set to L level, and the NMOS 23-11 to 23
Turn off all of -44,53-11 to 53-33,103-1,103-2.

Next, when the clock pulse φ enters the H level signal propagation period, the PMOSs 11-1 to 11-4, 41-1 to 41-3, 101 are turned off, and the precharge is completed. At the same time, for example, the input signal IN1 is transmitted to the first signal line 21-1 through the inverter 3-1 and the AND gate 4-1 and is transmitted to the first signal line 21-2 through the AND gate 4-2. Then, the on / off states of the NMOSs 23-11 to 23-24 are selected to determine the potentials of the second signal lines 22-1 to 22-4, and these potentials are AND gates 33-1 to 33-4. Entered in. On the other hand, due to the inverting operation of the inverter 3-1, either the first signal line 21-1 or 21-2 is at the H level, so that either the NMOS 103-1 or 103-2 is turned on, The fifth signal line 102 is set to L level.

Here, regarding the load capacitances of the second signal lines 22-1 to 22-4 and the fifth signal line 102, the fifth signal line 102 has a larger load capacitance because the capacitive elements 104-1 and 104-2 are connected. The potential of the second signal lines 22-1 to 22-4 is determined earlier than that of the fifth signal line 102. Therefore, this output signal becomes H level by the AND gate 32, and AND gates 33-1 to 33-
When a signal is propagated to the fourth signal lines 52-1 to 52-4 through No. 4, the potentials of the second signal lines 22-1 to 22-4 are already determined.

The signals propagated to the fourth signal lines 52-1 to 52-4 of the OR circuit 50 determine the ON / OFF state of the NMOS 53-11N, for example, and output the output signal OUT1 through the third signal line 51-1. One operation ends.

In this embodiment, a delay circuit 10 having an element adjacent to the AND circuit 20 and having the same or similar shape as that of the circuit 20 is provided.
Since 0 is provided, the AND circuit 20 and the delay circuit 100 exhibit the same characteristics with respect to manufacturing variations and operating condition variations. Therefore, the delay time of the delay circuit 100 can be set easily and accurately, and thereby the operating speed can be increased. Further, since the present embodiment has the synchronous circuit configuration, it has the advantages that it consumes less power and has a smaller number of elements than the conventional asynchronous circuit. Therefore, it can be applied to various integrated circuits such as a high speed microprocessor and a high speed signal processor.

Note that the present invention is not limited to the illustrated embodiment, and for example, the capacitive elements 104-1 and 104-2 of FIG. 9 may be configured by other elements such as a P-type active layer, or the NMOS of the circuit of FIG. To
Set PMOS to NMOS, change the number of input / output signals to other numbers,
Alternatively, instead of the CMOS configuration, an enhancement type / depletion type circuit configuration (that is, also referred to as an E / D type circuit configuration or a load resistance type circuit configuration) may be used. Furthermore, various modifications are possible, such as applying the PLA circuit of FIG. 1 to a ROM circuit.

(Effect of the Invention) As described in detail above, according to the present invention, since the gates of the plurality of first transistors and the third and fourth transistors are connected to the first signal line pair, It is possible to more effectively give the same characteristics to manufacturing variations. Moreover, in the present invention, the gates of the third and fourth transistors are connected to the first signal line pair to which the input signal and the inverted signal are input, and during circuit operation, the third and fourth transistors are connected. The potential of the fifth signal line is controlled by utilizing the fact that either one is always turned on, and the potential (signal) is delayed by the capacitor to drive the gate circuit. Therefore, even if the propagation of the input signal is delayed or accelerated in the AND circuit for some reason, the signal can be appropriately transferred from the AND circuit to the OR circuit.

Therefore, the delay time of the delay circuit can be set easily and accurately, the operation speed can be increased, and the effects of low power consumption and reduction of the number of elements can be expected.

[Brief description of drawings]

1 is a circuit diagram of a synchronous PLA circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional synchronous PLA circuit, FIG. 3 is a circuit diagram of a delay circuit in FIG. 2, and FIG. The figure shows the timing chart of Fig. 2, and Fig. 5 shows the conventional asynchronous resistance load type PLA.
A circuit diagram of the circuit, FIG. 6 is a circuit diagram of a conventional asynchronous complementary PLA circuit, FIGS. 7 (1) and 7 (2) are configuration diagrams of intersections of signal lines in FIG. 1, and FIG. 1) and (2) are shown in FIG.
9 is a configuration diagram of the PMOS, FIGS. 9 (1) and 9 (2) are configuration diagrams of the capacitor in FIG. 1, and FIG. 10 is a time chart of FIG. 1 ... Input signal gate circuit, 10 ... AND circuit pull-up circuit, 20 ... AND circuit, 21-1 to 21-4 ... First signal line, 22-1 to 22-4 ... 2 signal lines, 23-11 to 23
−44 …… NMOS, 30A …… Gate circuit for signal transfer, 40 …… O
Pull-up circuit for R circuit, 50 ... OR circuit, 51-1 to 51
-3 ... third signal line, 52-1 to 52-4 ... fourth signal line, 53-11 to 53-33 ... NMOS, 100 ... delay circuit, 101 ...
... PMOS, 102 ... Fifth signal line, 103-1, 103-2 ... NMO
S, 104-1, 104-2 ... Capacity, 105 ... Inverter, IN1,
IN2 …… input signal, OUT1 to OUT3 …… output signal, φ …… clock pulse.

Claims (1)

(57) [Claims] 1. A plurality of first signal line pairs to which a plurality of input signals and their inverted signals are input in synchronization with a clock pulse; and a first signal line that is pulled up in synchronization with the clock pulse. A plurality of second signal lines intersecting the pair, a plurality of the first signal line pairs, and a plurality of first transistors connected to desired intersections of the plurality of second signal lines And one end of which is connected to the second signal line,
A plurality of first transistors whose gates are connected to either one of the signal line pairs of, and a plurality of the input signals and the inverted signals thereof among the plurality of input signals by turning on and off the plurality of first transistors. It corresponds to an AND circuit that outputs a logical product of desired signals from the second signal line, a plurality of third signal lines that are pulled up in synchronization with the clock pulse, and an output signal of the AND circuit. A plurality of fourth signal lines that are supplied with a signal and intersect the third signal line, and a desired intersection of the plurality of third signal lines and the plurality of fourth signal lines. A plurality of second transistors connected to the third signal line, one end of which is connected to the third signal line, and a plurality of second transistors whose gates are connected to the fourth signal line. Before due to the on / off operation of the second transistor An OR circuit that outputs a logical sum of desired signals from the signals corresponding to the output signals of the AND circuit from the third signal line; and a plurality of first signals that are pulled up in synchronization with the clock pulse. A fifth signal line intersecting the line pair, and a first signal line of at least one of the plurality of first signal line pairs
Third and fourth transistors connected to the intersection of the signal line pair and the fifth signal line to control the potential of the fifth signal line, one end of which is connected to the fifth signal line. And a gate connected to one of the first pair of signal lines, respectively.
And a fifth signal line, one end of which is connected to the transistor and the other of the first signal line pair is connected to the gate of the fourth signal line.
And a delay capacitive element connected to the fifth signal line, the delay circuit outputting a signal obtained by delaying the clock pulse for a predetermined time, and an input section connected to the delay circuit. And a gate circuit for transferring a signal corresponding to the output signal of the AND circuit to the fourth signal line in synchronization with the signal obtained by delaying the clock pulse by a certain time, and a semiconductor logic circuit. .