JPH0329419A - Dynamic programmable logic array - Google Patents

Abstract

PURPOSE:To decrease a charge/discharge current and a through-current and to reduce the power consumption by adding a gate controlling a product term line from an AND plane while giving an optional delay to a precharge clock. CONSTITUTION:A gate is provided, which controls a product term line from an AND plane while giving an optional delay to a precharge clock. That is, AND circuits 13-15 are controlled with a precharge clock PC via a delay gate 1 and a signal from a product term line from an AND plane being an input to an OR plane and the OR plane is synchronized with the AND plane. Thus, a dynamic programmable logic array saving the power consumption is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dynamic programmable logic array composed of MOS circuits.

[Conventional technology] Conventional basic programmable logic array (hereinafter referred to as
An example of the structure of PLA) is shown in FIG.

This example uses two human forces (A, B) and four product terms (Tl, T
It is composed of an AND plane 39 and an OR plane 30, which have two outputs (Ql, Q2), and the human power signal to the AND plane 39 is expressed as a human power variable.
Two-stage AN that uses the output signal from the R plane 30 as an output variable
Any logical function with a D-OR configuration can be expressed. In this example, it is a NOR-NOR type, and the desired logic function can be obtained depending on the presence or absence of a MOS transistor.

31 is a load transistor on the AND side 39, 32 is an OR transistor
The load transistors 33, 34 in the plane 30 are buffer inverters.

[The problem to be solved by the invention is the above-mentioned conventional PLA! ．． The gates of P-channel transistors 31 and 32, which are load transistors on the tAND, OR plane, are lowered to the ground potential, and the product term line TI-74
Since it is an asynchronous type in which current is always flowing through the output lines Ql and Q2, there is a drawback that power consumption is large.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to provide a dynamic programmable logic array with reduced power consumption.

[Differences between the invention and the prior art] The product term line and output line of the AND plane and OR plane of the conventional PLA described above have a configuration in which each load transistor is always on and the current drips, whereas the present invention The difference is that a gate is added to control the product term line with an arbitrary delay to the precharge clock of the AND plane, thereby reducing power consumption.

[Means for Solving the Problems] The dynamic programmable logic array of the present invention converts AND planes and OR planes using MOS circuits into NOR-N
In a programmable logic array configured in an OR type and having precharge circuits on the AND plane and the OR plane,
The present invention is characterized in that it includes a gate that controls the product term line that enters the OR plane from the AND plane by giving an arbitrary delay to the precharge clock.

[Example] An embodiment of the present invention will be described with reference to FIG.

In this embodiment, the AND plane 39 which becomes the human power of the OR plane 30 with the precharge clock PC via the delay gate 11
The product term line of A is used to control the AND circuits 13, 14, and 15.
The OR plane 30 is also synchronized with the ND plane 39. 1 is a load P-channel transistor on the AND plane 39; 2 and 3 are N-channel transistors on the AND plane 390; 4 is a load P-channel transistor on the OR plane 30;
5 and 6 are N-channel transistors on the OR plane 30. AND plane N-channel transistors 2, 3, O
Logic is generated by N-channel transistors 5, 6, etc. on the R plane. 12 is a delay circuit, IO1 and 102 are inputs of the PLA, and 001 to OOi are outputs. Also a, b, C, d
, e, f indicate nodes.

Next, the operation will be described.

FIG. 3 shows the waveforms of each node a to f in an example in which a precharge clock PC and input data 101 are applied manually. First, when IOI is O, when PC rises to high level, the load P-channel transistor I on the AND side and the load P-channel transistor 4 on the OR side are turned on via the delay circuit 12, and the product term line d and the output line f is charged to a high level. The precharge signal passed through the delay circuit 11 is input to the input data IO due to the falling edge of the node C.
1, 102..., and the product term line d are disabled by the AND circuit l3, and the AND side load P-channel transistor 1 and N-channel transistor 2 are both turned on, and the OR side load P-channel transistor 4 is turned on.
, N-channel transistor 5 are both turned on and controlled so that no through current flows. When PC falls, node C rises, node b remains as it is because IOI is at a low level, and N-channel transistor 2 remains off. During the delay time, the signal at node d becomes a through state at node e and becomes high level.
N-channel transistor 5 is turned on, and node f becomes low level. Therefore, the output OO1 becomes high level.
Tacl is the access time from input, T
ac2 is the access time from the trailing edge of the precharge clock PC.

When the human power data 101 is 1, as described above, when PC rises to high level, node a falls, and product term line d and output line f are charged to high level. On the other hand, node b
falls, and the N-channel transistor 2 is turned off. When PC becomes low level, node b becomes high level, N-channel transistor 2 is turned on, and product term line d
becomes low level. Node e remains at low level,
N-channel transistor 5 remains off.

Therefore, the output &If remains charged and 00
1 is its inverse.

Here, although the desired purpose can be achieved in the above-described embodiment, it is conceivable that the potential level of the product term line d and the output line f decreases due to leakage if the clock cycle time is long. Therefore, it is preferable to configure the circuit for controlling the product term line by combining an inverter 21 and a NOR gate 22 as shown in FIG.

[Effects of the invention] As explained above, by adding a gate that controls the product term line from the AND plane by giving an arbitrary delay to the precharge clock, charging/discharging current and through current are reduced, and power consumption is reduced. This has the effect of making it smaller.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a dynamic PLA according to an embodiment of the present invention, FIG. 2 is a block diagram showing a modification of the control circuit, and FIG.
The figure is an operating wave system diagram of a dynamic PLA, and FIG. 4 is a configuration diagram of a conventional example. 1, 31... Load P-channel transistor in AND plane, 2, 3... N-channel transistor in AND plane, 4, 32... Load P-channel transistor in OR plane, 5, 6... ...N-channel transistor in OR plane, 11.12...Circuit with arbitrary delay, 13,14,
15...AND circuit that controls the product term line, 21, 33.34・◆・Inverter, 22 ・ ● ・ ● ・ ・ ・ ・ ・ NOR gate, 30●◆●◆・◆・◆◆OR plane, 39・・・・・・・・・AND plane, Tacl ・・・Access time from human power to output,
T ac2: Access time from the trailing edge of precharge clock PC.

Claims (1)

[Claims] AND plane and OR plane by MOS circuit are NOR-N
In a programmable logic array configured in an OR type and having precharge circuits on the AND plane and the OR plane,
1. A dynamic programmable logic array comprising a gate for controlling a product term line entering from an AND plane to an OR plane by giving an arbitrary delay to a precharge clock.