JPS6020632A - Nor circuit - Google Patents

Abstract

PURPOSE:To vary the speed of the circuit operation by bringing a signal inputted to an N-channel MOS gate of the NOR logic into an L level in precharging an output line. CONSTITUTION:The 1st stage NOR logic consists of N-channel MOSes 33, 34 and 35. The input of this logic is an output 26 of a driver comprising P-channel MOSes 30, 15 and an N-channel MOS 16 and an output is a potential at a terminal 17. The P-channel MOS 13 is utilized for precharging an output terminal. When inputs 26 or the like to the NOR logic are all at L level, since the N-channel MOSes 33-35 are turned off, the output 17 is not grounded and a precharged electric charge is not discharged, then the level is kept to H level. When any one input goes to H, the output 17 is grounded and the output is transited to the L lveel. The next stage NOR logic consists of N-channel MOSes 37-39. A clock signal line 25 designates a precharge period.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a multi-stage logic circuit, and particularly to a circuit configuration method suitable for a dynamic multi-stage logic circuit incorporating a precharge method.

[Background of the invention]

Conventionally, PLA etc. used as multi-stage logic are multi-stage logic with NAND configuration shown in Figure 1 or NAND configuration shown in Figure 2.
It is composed of multi-stage logic with an OR configuration. In order to increase the speed of this multi-stage logic, the sib□ recharge method has conventionally been adopted. However, in the precharge method, many types of clock signals are required to control the precharge period.

However, in LSIs, the types of input clocks are limited, making it difficult to generate many types of clock signals.

A domino-type multi-stage logic circuit shown in FIG. 3 was shown under such circumstances. N using this domino method
The operation of a multistage logic circuit having an OR logic configuration will be explained using FIGS. 3 and 4. During the period when clock signal 1 is L, P channel MO82, 3 is ONL, N channel MO89, 1
2 turns OFF, the outputs 4 and 5 of NOR logic 8 and 11
are precharged to H level. The input signal 7 is determined during this precharge period.

When clock signal 1 becomes H level, P channel MO8
2 and 3 are turned OFF', and N channel MO89 is turned OFF'.
NOR logic 8 operates.

If all of the input cuffs are at L, output 4 remains at H; otherwise, output 4 transitions to L. Next stage 0NOR logic 11
is provided with means for delaying the clock signal 1 so as not to operate until the human power 4, 6 is determined. NO
The propagation signals 10 of the clock signal 1, delayed until the time when the inputs 4.6 of the R logic 11 are determined, cause them to become H at the determined time, and the NOR logic 11 operates.

In a logic circuit adopting the precharge method, the smaller the number of NMO8Os connected in series between the output line and GND, the faster the operation will be. In other words, the time it takes to discharge the charges held on the output line is the operating time of the logic circuit, so the lower the resistance value of the discharge path, the faster the operating time. Therefore, when increasing the speed of a logic circuit, its logic structure is NAN
The NOR configuration is more advantageous than the D configuration.

The domino system shown in FIG. 3 satisfies the conditions for speeding up in terms of the above points. However, when attempting to further increase the speed, the following problems arise. In the domino system, the N-channel MOs 89 and 12 are prohibited from being grounded so that the charges accumulated on the output lines 4 and 5 during the precharge period do not leak until the logic operation time begins. Therefore, in a simple NOR configuration, only one NMO8 is required to be connected in series between the output line and GND, whereas two NMO3 are required. Furthermore, during the precharge period, not only the drain capacitance of the N-channel MO8 constituting the NOR logic 8, 11 on the output line 4.5 but also the drain capacitance connected to the N-channel MO89, 12 on the ground side is Electric charge can also be stored with respect to quantity. Therefore, more charges must be discharged during the operating time of the logic circuit than in a NOR circuit in which only one N-channel MO8 exists between the output line and the GND line.

Therefore, in order to operate the domino-type NOR configuration logic circuit shown in FIG. 3 at higher speed, the number of N-channel MO8s connected in series between the output line and GND is set to one.
The series resistance must be reduced and the amount of charge stored during the precharge period must be reduced.

[Purpose of the invention]

The object of the present invention is to provide a multi-stage logic circuit constructed by serially connecting NOR logic circuits in which the number of serial NMO8s is 1 and is connected between an output line and GND, which is suitable for high speed in a precharge method. The object of the present invention is to provide a circuit that can operate continuously with only one clock signal.

[Summary of the invention]

When precharging the output line, the signal input to the NOR logic N-channel MO8 gate is set to L level to prevent the output line from being grounded. The number of NMO8O connected to was set to 1.

In the above circuit, the signal line specifying the precharge period is delayed using a delay means, and the next stage N connected in series
By using OR logic signal lines, it is possible to configure multi-stage logic similar to the domino system.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 5 and 6.

In FIG. 5, the first stage NOR logic is an N-channel MO83.
It is composed of 3, 34, 35 and so on. The input of this logic is P
This is the output 26 of a driver composed of channel MOs 830 and 15 and N-channel MO 816, and the output is at a potential of 17. P channel M0813 is used for precharging the output terminal. Input 26 to NOR logic
etc. are all I, I+, N channel MO833
34.35 is in the OFF state, so the output 17 is not grounded and the precharged charge is not discharged, so it remains at H. If even one of the inputs becomes "H", the output 17 is grounded and the output changes to "L". Next stage NOR
The logic is composed of N-channel MOs 837, 38, and 39.

Clock signal line 25 specifies the precharge period. While the clock signal 25 is at H level (see FIG. 6), the output 17 is precharged. That is, signal 2
Since the level of 5 is inverted by the inverter 32 and the L level is inputted to the P-channel MO 813, 13 is turned on and charges are supplied to the IC 117.

On the other hand, the signal 25 is also input to the P-channel MO 815 and N-channel MO 816 of the driver circuit that perform input to the NOR logic. During the precharge period, the signal 251'
Since it is iH, the P channel MO815 is in the OFF state, the 1N channel MO816 is in the ON state, and the NO
Since the input 26 to the R logic is grounded and becomes L level, the N channel MO833, 34 forming the NOR logic
, 35 are in the OFF state to prevent the output 17 from being grounded. The signal 25 is delayed through the delay means and is also input as the signal 23 to the next stage NOR logic.

The next stage NOR logic has the same structure as the first stage NOR logic, and precharging is performed in the same way at a slightly delayed time compared to the first stage. When precharging is completed, 1. each N
The outputs 17 and 28 of the OR logic become H level. Shodan NO
The R logic starts operating when the clock signal 25 becomes L level. Before that, signal 2 that should be input to the first stage NOR logic
Confirm 9. When the clock signal 25 becomes L level, an H signal is input to the P-channel MO 813 through the inverter 32, and the connection between the output 17 and the power supply is cut off. On the other hand, the P-channel MO815 of the driver is not in the QN state.
N-channel MO 816 is in the OFF state. At this time, if the input 29 to the driver is at H level, the P channel MO8
30 is in the OFF state, the driver output 26 holds L.

On the other hand, when 29 is at L level, P channel MO830 is at O
It enters the N state, and the output 26 transitions to H level through the P channel MO 830.degree. 15, and when the N channel MO 833 forming the NOR logic is in the ON state, the output 17 transitions to the L level. At this time, looking at the relationship between the driver's human power 29 and the inverted signal 20 after passing through the inverter 19 of the output 17 of the first stage NOR logic 18, all the signals 29 are II H"
When the level is high, the signal 20 becomes "L" level, and if even one of the signals 29 becomes "L" level, the signal 20 becomes "H" level. Therefore, logically, this is equivalent to the NAND configuration shown in FIG. Become.

Until the output 17 of the first stage NOR logic 18 is determined, the next stage N
A means for delaying the clock signal 25 is provided so that the OR logic 24 does not operate, and the delayed signal 23 is applied to the next stage NOR logic 24.
Logic driver section P channel MO821, N channel M
O822 and a signal whose level is inverted by the inverter 36 of the delayed signal 23 is sent to the P-channel MO814 for precharging.
Enter. The operation of the next stage NOR logic 24 is also the same as the first stage NO
Similar to R logic, the P channel MO814 for precharging is in the OFF state during operation time, and the P channel of the driver section is in the OFF state.
Channel MO8121 is in the ON state, and N channel M
O822 is in the OFF state, and when the driver power 20 is all at H" level, the output 28 remains at H level,
20 is the L level.

FIG. 7 shows an example in which the multistage logic circuit configured in FIG. 5 is applied to a PLA. A signal 55 corresponds to the clock signal 25, and a signal 56 corresponds to the delayed color code 23. First stage driver P
Channel MO830 corresponds to 42, and channel MO15 corresponds to 43. 45 corresponds to the N-channel MO 816. Also,
44 for the N-channel MO833 etc. that constitute the NOR logic.
corresponds. 54 corresponds to the P-channel MO 813 for precharging. The output of the first stage NOR logic is 57, and the inverter 19 corresponds to 46. 47 corresponds to the P-channel MO 831 of the next stage driver, 48 corresponds to 21, and 51 corresponds to the N-channel MO 822. 50 corresponds to the N-channel MO 837 and the like constituting the next stage NOR logic.

49 corresponds to the P-channel MO 814 for precharging. The circuit configuration is exactly the same as the multistage logic shown in FIG.

〔Effect of the invention〕

According to the present invention, by using only one clock signal, a multi-stage logic circuit can be used to
Since the OR logic can be configured with one MOS connected in series between the output line and GND, it is effective in speeding up the circuit operation.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams of multi-stage logic, FIG. 3 is a conventional domino-type multi-stage logic circuit diagram, FIG. 4 is an operation timing diagram thereof, and FIG. 5 is a multi-stage logic circuit diagram of the present invention. Figure 6 is its operation timing diagram, and Figure 7 is the PL of the multistage logic circuit of the present invention.
It is a circuit diagram when applied to A. 8.11, 18.22 and 44.50...NOR Theory No. 1 Figure Z Figure γ 3 Figure ■ 4 Figure 20ヅ7荏脣l ふ4工4-／ Side repair p 拮名 lθ Fan 5Figure/

Claims (1)

[Claims] 1. N-channel MO8 connected in parallel between the output line and ground to configure NOR logic, and connected between the power supply and the output line to precharge the output line. A NOR circuit consisting of a circuit that outputs the full voltage to set the gate potential of the P-channel MO8 and the N-channel MO8 to the L level during the precharge period and to the level corresponding to the input level during the logic period. circuit. 2. In a multi-stage logic in which the output signal of the NOR circuit is completely inverted and is input to another NOR circuit with the same circuit configuration, the timing t1 of the precharge period is on the delayed signal of the precharge timing signal of the previous stage NOR circuit. The NOR four-way of the first term is characterized in that it is used.