JP2647460B2 - Bus precharge circuit and high-speed logic system - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus precharge circuit and a high-speed logic system including the same, and more particularly, to a bus precharge circuit and a high-speed logic system suitable for a large bus width. .

[Prior Art] In a logic system using a CMOS circuit, a dynamic bus is frequently used, and a bus precharge circuit using a p-channel MOS transistor (hereinafter, referred to as a pMOS) is well known.

FIG. 10 is a configuration diagram of a conventional bus precharge circuit. In FIG. 10, pMOSs 2 _-1 to 2 _-n are prepared corresponding to the respective bit lines 1 _-1 to 1 _-n of the n-bit bus 1, and the drains of the respective pMOSs are connected to the corresponding bit lines, and the source is The gate is commonly connected to a power supply, and the gate is commonly connected to a clock signal line. For example, the logic circuit 3 which is connected to the bit line 1 _-1, two series-connected n-channel MOS transistors (hereinafter, referred to as nMOS.) 4, 5 provided with a source to the bit line 1 _-1 of nMOS 4, The drain of the nMOS 5 is connected to a reference potential (hereinafter, referred to as a ground potential “GND”). Each nMOS4,5 clock signal φ inputted to the gate of, depending on the level of the data signal D, pMOS2 _-1 by the other to GND bit line 1 _-1 which is set to a predetermined potential of a predetermined potential (In this case, GND potential).

FIG. 11 is a waveform chart for explaining the operation of the conventional bus precharge circuit shown in FIG. In this example, the bus is precharged during a period T ₁ of the "0" of the clock phi. In this precharge, as the precharge current by the pMOS2 increases to →→, the bus potential also changes to →→
And its rise becomes faster. Must be shortened period T ₁ of the clock φ in accordance with the bus width increases (Configuration bit line number is a number) must quickly launch of bus voltage accordingly. That is, a large precharge current needs to flow in a short time.

Incidentally, Japanese Patent Application Laid-Open No. 54-8955
There is No. 8.

[Problems to be Solved by the Invention] Generally, a dynamic logic system has a plurality of sets of dynamic buses, and the bus width of each set is also increased (for example,
32 bit configuration). If the above-described conventional technique is applied to precharging such a large bus, there is a problem that the precharge current concentrates in a short time, thereby causing power supply noise. In order to keep the power supply noise below an allowable level, it is necessary to lengthen the precharge time and make the current change gradual, but this will hinder the speeding up of the system. In order to increase the speed of the system, it is necessary to solve the problem of the power supply noise, and this problem has become unavoidable as the performance and speed of the semiconductor element increase.

An object of the present invention is to provide a bus precharge circuit that reduces a bus precharge time and suppresses power supply noise to an allowable level or less, and a high-speed logic system using the same.

[Means for Solving the Problems] The object of the present invention is to precharge the bus in a two-stage configuration. First, the bus is precharged by the first precharge means, and when the bus potential reaches a certain potential, the second precharge is performed. This is achieved by activating the precharge means and setting the bus potential to a predetermined potential. Further, this can be achieved by providing a bus precharge circuit provided in the logic system, the bus system including the first precharge unit, the second precharge unit, and a unit for detecting that the bus potential has reached a certain potential.

[Operation] When the bus is precharged by the bus precharge circuit of the present invention, the bus potential is raised to some extent by the first precharge means and then by the second precharge means and the first precharge means, or by the second precharge means. The bus potential is set to a predetermined potential within the precharge period by only means. As a result, immediately after the start of precharge (immediately after the clock signal)
The charging current does not concentrate on the battery. Therefore, by using this bus precharge circuit alone or in common with the conventional bus precharge circuit, the transient precharge current can be dispersed, and the power supply noise can be reduced to an allowable level or less during short-time bus precharge in a high-speed logic system. It becomes possible to suppress.

Embodiment A preferred embodiment of the present invention will be described below with reference to FIGS.

FIG. 1A is a configuration diagram of a main part of a high-speed logic system including a bus precharge circuit according to a first embodiment of the present invention. The bus precharge circuits 6 _{-1 to} 6 _-n and the logic circuits 3 _-1 to 3 _-3 correspond to the respective bit lines _-1 to 1 _{-n of the} n-bit bus 1.
_-n is connected. Reference numeral 7 denotes a power supply terminal, and reference numeral 8 denotes a clock signal (φ) line. The configuration of each of the logic circuits _{3-1 to} 3- _n is the same as that of the logic circuit 3 in FIG.

FIG. 1B is a waveform diagram of the clock signal φ. Each bus precharge circuit 6 _-1 to 6 _-n clock signal φ is "0"
It is activated period T ₁ showing the corresponding bit line 1 _-1 to 1 _-n
Is precharged as described later. Each logic circuit 3 _{-1 to} 3 _-n
Is activated in period T ₂ showing the clock signal φ is "1", and outputs the data signal to the corresponding bit line 1 _-1 to 1 _-n. When the data signal is "1", it means that the potential of the connected bit line is lowered, and when it is "0", it means that the potential of the connected bus bit line does not change.

FIG. 2 is a detailed configuration diagram of the bus precharge circuit shown in FIG. 1 (a). Each bus precharge circuit 6 _-1
To 6 _-n because the same configuration, illustrated only circuit _6-1.

This bus precharge circuit includes a pMOS 10 constituting a first bus precharge unit, two pMOSs 11 and 12 and an npn transistor 13 constituting a second bus precharge unit, and an inverter 14 constituting a bus potential identification unit. Prepare. pM
OS10 has a source to the power supply terminal 7, a gate clock signal line 8, and the drain is connected to the bus bit line 1 _-1. The pMOS 11 has a source connected to the power supply terminal 7, a gate connected to the clock signal line 8, and a drain connected to the source of the pMOS 12. The drain and gate of pMOS12 is connected to the output of the gate and inverter 14 of each npn transistor 13, the collector and emitter of npn transistor 13 is connected to each power supply terminal 7 and the bus bit line 1 _-1. The input of the inverter 14 is connected to the bus bit line _1-1 . Incidentally, 15 is a base electric discharge means provided between the base and the bus bit line 1 _-1 of the npn transistor 13, 16 is a capacitive load coupled to the bus bit line 1 _-1.

Next, the operation of the above bus precharge circuit will be described with reference to the waveform diagram of FIG.

Now, when the potential of the bus bit line 1 _-1 "0" clock signal φ when the level is changed to "0" level from "1" level, PMOS10,11 is turned on. On the other hand, the output of inverter 14 is the potential of the bus bit line 1 _-1 "0" because the level "1"
It has become. Therefore, pMOS12 is off and npn
The transistor 13 is off because the base current is zero. Therefore, the time t ₁ from when the switch to the clock signal φ is "0" level until a potential H which is a bus bit line 1 _-1, only pMOS10 contributes to precharge the bus bit line 1 _-1 . Upon reaching the potential H which have the potential of the bus bit line 1 _-1, the output of inverter 14 is inverted to "0" and, PMOS 12 is turned on. Thus npn transistor 13 is turned on, flowing a large charging current to the bus bit line 1 _-1 from the power supply terminal 7 through the npn transistor 13. In other words, both pMOS10 and npn transistor 13 during the period t ₂ contributes to precharge the bus bit line 1 _-1.

As described above, in the present embodiment, in the initial stage of precharge, precharge is performed by the pMOS 10 having a relatively small drive current to reduce the concentration of the charge current, and the bus potential is set to a certain potential H (H
Depends on the characteristics of the inverter 14. After reaching)
Since the precharge is performed by both the pMOS 10 and the npn transistor 13 having a large drive current, the precharge can be completed within the time (precharge period) when the clock signal φ is “0”. Therefore, both high-speed precharge and current concentration elimination can be achieved.

FIG. 4 is a configuration diagram of a bus precharge circuit according to a second embodiment of the present invention. In the first embodiment, instead of the large npn transistor 13 of the drive current as a second precharge means, in the present embodiment to omit this npn transistors, it is connected directly to the bus bit line 1 _-1 drain of pMOS12 Are different. Thus, after reaching the potential H which have the potential of the bus bit line 1 _-1, a charge current through the PMOS11,12, precharging is performed at a charging current through the PMOS 10.

Although the dynamic logic system has a plurality of sets of dynamic buses, it is not necessary to precharge all the buses with the bus precharge circuit according to the present invention. The point is that it is only necessary to eliminate the concentration of the charging current, so that it can be used in combination with a conventional single-type precharge circuit.

FIG. 5 is a configuration diagram of a main part of the dynamic logic system. This logical system includes two sets of buses 1 and 20 each having an npn bit configuration. The precharge of the bus 1 is performed by the precharge circuits 6 _{-1 to} 6-6 described in FIG. 2 or FIG.
_-n , and the bus 20 is precharged by a single precharge circuit 9 _{-1 to} 9 _-n similar to the conventional one. FIG. 6A is a configuration diagram of a precharge circuit having a single configuration. In this single-configuration precharge circuit, when the clock signal φ becomes “0”, the pMOS 21 is turned on.
The npn transistor 22 is turned on, whereby a charging current larger than the power supply flows into the bus bit line 20- _i . As a result, as shown in FIG. 6 (b), a large charging current is concentrated at the beginning of the precharge. But bus
Be precharged as in the prior art to 20, since the pre-charge bus 1 in the precharge circuit 6 _-1 to 6 _-n of the present invention embodiment, even if the pre-charge current is concentrated to generate the time power The noise is kept below the allowable level, and there is no problem. Therefore, high speed and low noise can be achieved by configuring the system in this manner.

In FIG. 5, a bus precharge circuit having different precharge characteristics is used for each bus. However, even when a part of the bit lines of the bus and the other are precharged using precharge circuits having different characteristics, the precharge circuit can be used. Concentration of charge current can be eliminated, and high speed and low noise can be achieved.

In the high-speed logic system shown in FIG.
When precharging 30, the odd-numbered bit lines
Precharge circuit 6 _{-Odd1 to} 6 explained in FIG. 4 or FIG.
_-Odd31 , and the even-numbered bit lines have a single-structured precharge circuit 9 described in FIG. 6 _{-even2 to} 9
_I precharge with _-even32 . In the high-speed logic system shown in FIG. 8, when precharging the bus 30 having a 32-bit configuration, the first to sixteenth bits are replaced by the precharge circuits 6 _{-1 to} 6 -6 shown in FIG. 2 or FIG.
_The precharge is performed at _-16 , and the 17th to 32nd lower bits are precharged by the single-structure precharge circuit described with reference to FIG.

FIG. 9 is a configuration diagram of a domino logic circuit in which a logic circuit is combined with a bus precharge circuit according to a third embodiment of the present invention. Since the configuration of the bus precharge circuit is the same as that of the second embodiment shown in FIG. 4, the same components are denoted by the same reference numerals, and the description thereof will be omitted. Only different portions will be described.
In FIG. 9, the bus bit line _1-1 is not a line but an internal node (point) _1-1 .

The gate of the nMOS 33 is connected to the clock signal line 8, and the source is connected to a reference potential (in this case, GND). Then, between the drain and the bus bit line 1 _-1, two series-connected nMOS31,32 constituting the combinational logic unit is connected.

The domino logic circuit, when the clock signal φ is "1" level, in the period T ₂ of the words first view (b), pMOS
10 and 11 are off and nMOS 33 is on. In this state, nMO
The logic operation is performed by the gate inputs A and B of S31 and S32.
Now, A, if B a are "1" level, NMOS31,32,33 all bus bit line 1 _-1 in the ON to switch to the "0" level. As a result, the output of the inverter 14 becomes "1" level. When at least one of A and B is at "0" level, no dielectric path is formed between bus bit line _1-1 and the reference potential, and bus bit line _1-1 is in a precharged state. The output remains at “1” level, and the output of the inverter 14 also remains at “0” level. The operation at the time of precharging is the same as that of the embodiment shown in FIGS.

[Effects of the Invention] According to the precharge circuit of the present invention, it is possible to avoid the current from being concentrated at the beginning of the precharge. Therefore, by incorporating this precharge circuit into a logic system, both high-speed and low-noise operation of the system can be achieved.

[Brief description of the drawings]

FIG. 1A is a configuration diagram of a main part of a high-speed logic system incorporating a bus precharge circuit according to a first embodiment of the present invention;
FIG. 2B is a waveform diagram of the clock signal, FIG. 2 is a detailed configuration diagram of the bus precharge circuit shown in FIG. 1, and FIG.
FIG. 4 is a waveform diagram for explaining the operation of the bus precharge circuit shown in FIG. 4, FIG. 4 is a configuration diagram of the bus precharge circuit according to the second embodiment of the present invention, and FIG. 5 incorporates the bus precharge circuit according to the present invention. 6 (a) is a configuration diagram of a single-configuration bus precharge circuit, FIG. 6 (b) is a waveform diagram illustrating the operation of the single-configuration precharge circuit, FIG. 7 and FIG. 8 are main part configuration diagrams of a high-speed logic system for explaining a connection configuration of a bus precharge circuit according to the present invention to a bus. FIG. 9 is a diagram showing a bus precharge circuit and a bus precharge circuit according to an embodiment of the present invention. FIG. 10 is a configuration diagram of a domino type logic circuit combined with a logic circuit, FIG. 10 is a configuration diagram of a main part of a logic system incorporating a conventional bus precharge circuit,
FIG. 11 is a waveform diagram illustrating the operation of the conventional bus precharge circuit. 1,20,30… bus, 1 _-i , 20 _-i , 30 _-i … bus bit line, 6
_-i ... bus precharge circuit, 7 ... power supply terminal, 8 ...
Clock signal lines, 10, 11, 12 ... pMOS, 13 ... npn transistors, 14 ... inverters, 31, 32, 33 ... nMOS.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Tatsuo Nojiri 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside the Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Hisashi Tada 3-1-1 Sachimachi, Hitachi City, Ibaraki Co., Ltd. Hitachi, Ltd. Hitachi Plant (72) Inventor Tetsuo Nakano 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (56) References JP-A-61-126683 (JP, A) JP-A-63-39196 (JP, A) JP-A-61-34619 (JP, A) JP-A-58-33739 (JP, A) JP-A-62-53517 (JP, A) JP-A-58-211226 (JP, A)

Claims (10)

(57) [Claims] In a bus precharge circuit for setting a bus potential to a predetermined potential during a precharge period, a first precharge means for starting operation and precharging the bus in response to the start of the precharge period, A bus potential identifying means for identifying, and a second means for operating the remaining period of the precharge period to precharge the bus when the bus potential identifying means detects a certain potential lower than a predetermined potential of the bus potential during the precharge period; A bus precharge circuit comprising: a precharge unit. 2. The bus precharge circuit according to claim 1, wherein the first precharge means and the second precharge means have different precharge performances. 3. The bus precharge circuit according to claim 2, wherein the precharge performance of the second precharge means is higher than the precharge performance of the first precharge means. 4. A high-speed logic system comprising a bus precharge circuit and a plurality of sets of buses precharged by the bus precharge circuit, wherein at least one set of buses is precharged. A high-speed logic system comprising the bus precharge circuit described above. 5. A high-speed logic system comprising a bus precharge circuit and a bus precharged by the bus precharge circuit, wherein a part of a bit line constituting the bus is precharged. A high-speed logic system comprising the bus precharge circuit according to item 1. 6. The method according to claim 5, wherein:
The bus precharge circuit according to any one of the above, precharges either an odd bit or an even bit of the bus. 7. The method according to claim 5, wherein:
Wherein the bus precharge circuit precharges either the upper bit or the lower bit of the bus. 8. The first precharge means according to claim 1, wherein the first precharge means comprises a first p-channel MOS transistor, the source, drain and gate of which are connected to a power supply, a bus and a clock signal line, respectively. The source, gate and drain of the second p-channel MOS transistor are a power source, a clock signal line, and a third p-channel MOS transistor, respectively.
Connected to the source of the transistor, the gate and the source of the third p-channel MOS transistor are connected to the output of the bus potential identifying means, the gate of the npn transistor, and the collector and the emitter of the npn transistor are connected to the power supply and the bus, respectively A bus precharge circuit. 9. The first precharge means according to claim 1, wherein said first precharge means comprises a first p-channel MOS transistor, and its source, drain and gate are connected to a power supply, a bus and a clock signal line, respectively. The source, gate, and drain of the second p-channel MOS transistor are connected to a power source, a clock signal line, and the source of the third p-channel MOS transistor, respectively. And a drain connected to the output of the bus potential identification means and the bus, respectively. 10. A high-speed logic system comprising a bus precharge circuit according to claim 8 or 9, wherein a logic comprising a combination of n-channel MOS transistors connected to said bus precharge circuit via a bus bit line. A high-speed logic system comprising: a circuit; and an n-channel MOS transistor having a drain connected to the logic circuit, a source connected to a reference potential, and a gate connected to a clock signal line.