JP2004304609A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a CMOS dynamic circuit capable of determining transition of the output signal level simultaneously with starting of a precharge period without waiting for charging of a dynamic node. <P>SOLUTION: The semiconductor integrated circuit comprises first and second inverters cascaded between the gates of a plurality of N channel MOS transistors where the source and drain are connected commonly between the drain of a P channel MOS transistor PM11 connected with the power supply potential node and the drain of an NMOS transistor NM21 connected with the ground potential node and an input signal is inputted to each gate, and a two-input NOR logic circuit having one side input being connected with the output node of the first inverter, the other side input being connected with the commonly connected drains of the plurality of N channel MOS transistors and an output node becoming a signal output node. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a precharge type CMOS dynamic circuit.
[0002]
[Prior art]
CMOS dynamic circuits capable of high-speed operation are widely used for various applications.
[0003]
FIG. 5 is a circuit diagram showing an example of a conventional CMOS dynamic circuit.
[0004]
In the conventional CMOS dynamic circuit, a P-channel MOS transistor PM11 having a source connected to a power supply potential node, a drain commonly connected to a drain of the P-channel MOS transistor PM11, and an input signal In input to each gate. The n-th (n is a natural number) N-channel MOS transistors NM11,. . . , NM1n and drains of the first to n-th N-channel MOS transistors NM11,. . . , NM1n connected to a commonly connected source, the source of which is connected to the ground potential node, an (n + 1) th N-channel MOS transistor NM21, a precharge signal input node, a P-channel MOS transistor PM11 and an (n + 1) th N-channel MOS transistor NM21, the first and second inverters INV1 and INV2 connected in cascade with the first to n-th N-channel MOS transistors NM11,. . . , NM1n, and a third inverter INV3 connected between the commonly connected drains and the signal output node.
[0005]
The first to n-th N-channel MOS transistors NM11,. . . , NM1n is a dynamic node Dy_node that is charged to H (High) level by precharge and outputs an H level signal or an L (Low) level signal according to the input signal In.
[0006]
When the precharge signal Prchg goes low, the precharge period of the circuit starts, the P-channel MOS transistor PM11 is turned on, the (n + 1) th N-channel MOS transistor NM21 is turned off, and the dynamic node Dy_node is charged to the H level.
[0007]
Thereafter, when the precharge signal Prchg becomes H level, the evaluation period of the circuit is started, the P-channel MOS transistor PM11 is turned off, and the (n + 1) th N-channel MOS transistor NM21 is turned on. During the evaluation period, as long as the input signal In is at the L level, the dynamic node Dy_node is maintained at the H level, and the signal output node outputs the output signal Out at the L level. On the other hand, when the input signal In goes high, the first to n-th N-channel MOS transistors NM11,. . . , NM1n are turned on, and the first to n-th N-channel MOS transistors NM11,. . . , NM1n and the (n + 1) th N-channel MOS transistor NM21, the dynamic node Dy_node is discharged, and the potential goes to L level. Therefore, the output signal Out at the H level is output from the signal output node.
[0008]
When the evaluation period ends, the process shifts to the precharge period again, and thereafter, the same operation as described above is repeated.
[0009]
[Problems to be solved by the invention]
However, in the above-described conventional precharge-type multi-input dynamic circuit, a large number of N-channel MOS transistors, that is, first to n-th N-channel MOS transistors NM11,. . . , NM1n, and the first to n-th N-channel MOS transistors NM11,. . . , NM1n are turned on, the drain diffusion capacitance of the (n + 1) -th N-channel MOS transistor NM21 which is visible ahead is added to the dynamic node Dy_node, so that the dynamic node after shifting from the evaluation period of the circuit to the precharge period The charging of Dy_node is delayed, so that the transition of the output signal Out is delayed, and the transition of the potential level at the next and subsequent nodes connected to the signal output node is delayed.
[0010]
The first to n-th N-channel MOS transistors NM11,. . . , NM1n increase as the number of N-channel MOS transistors increases, that is, as the number of inputs to the circuit increases, and the charging of the dynamic node Dy_node is further delayed, so that the transition of the output signal Out is also delayed.
[0011]
As a result, there has been a problem that a malfunction may occur in relation to other circuits connected to the next and subsequent stages of the circuit.
[0012]
SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to determine the transition of the output signal level at the same time as the start of the precharge period without waiting for the charging of the dynamic node, and to connect to the next and subsequent stages of the circuit. It is an object of the present invention to provide a CMOS dynamic circuit capable of preventing a malfunction in relation to another circuit.
[0013]
[Means for Solving the Problems]
According to one embodiment of the semiconductor integrated circuit according to the present invention,
A P-channel MOS transistor having a source connected to the power supply potential node;
A first to an n-th (n is a natural number) N-channel MOS transistors whose drains are commonly connected to the drains of the P-channel MOS transistors, and whose gates receive input signals;
An (n + 1) th N-channel MOS transistor having a drain connected to a commonly connected source of the first to n-th N-channel MOS transistors and a source connected to a ground potential node;
First and second inverters cascaded between a precharge signal input node and the gates of the P-channel MOS transistor and the (n + 1) -th N-channel MOS transistor;
An output node of the first inverter is connected to one input, a commonly connected drain of the first to nth N-channel MOS transistors is connected to the other input, and an output node is a signal output node. A two-input NOR logic circuit;
It is characterized by having.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings.
[0015]
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to the first embodiment of the present invention.
[0016]
In the semiconductor integrated circuit according to the first embodiment of the present invention, the P-channel MOS transistor PM11 whose source is connected to the power supply potential node, the drain is commonly connected to the drain of the P-channel MOS transistor PM11, and each gate has an input. The first to n-th (n is a natural number) N-channel MOS transistors NM11,. . . , NM1n and drains of the first to n-th N-channel MOS transistors NM11,. . . , NM1n connected to a commonly connected source, the source of which is connected to the ground potential node, an (n + 1) th N-channel MOS transistor NM21, a precharge signal input node, a P-channel MOS transistor PM11 and an (n + 1) th N-channel MOS transistor The first and second inverters INV1 and INV2 cascade-connected to the gate of the NM21, the output node of the first inverter INV1 is connected to one input, and the first to nth Nth inverters are connected to the other input. The channel MOS transistors NM11,. . . , NM1n, and a two-input NOR logic circuit NOR1 whose output node is a signal output node.
[0017]
The first to n-th N-channel MOS transistors NM11,. . . , NM1n is a dynamic node Dy_node that is charged to H (High) level by precharge and outputs an H level signal or an L (Low) level signal according to the input signal In.
[0018]
FIG. 2 is a timing chart showing signal waveforms at main nodes of the semiconductor integrated circuit according to the first embodiment of the present invention.
[0019]
The operation of the semiconductor integrated circuit according to the first embodiment of the present invention will be described with reference to FIGS.
[0020]
At time t1, when the precharge signal Prchg goes to L level, the circuit is in the precharge period, the P-channel MOS transistor PM11 is turned on, the (n + 1) th N-channel MOS transistor NM21 is turned off, and the dynamic node Dy_node is charged to H level. Is done. In the timing chart of FIG. 2, the input signal is at the L level during the evaluation period immediately before the time t1, and the dynamic node Dy_node is maintained at the H level. Therefore, in the precharge period started from the time t1, Is that the dynamic node Dy_node is already at the H level from time t1.
[0021]
Thereafter, at time t2, the input signal In goes high, and at time t3, when the precharge signal Prchg goes high, the circuit is in the evaluation period, the P-channel MOS transistor PM11 is turned off, and the (n + 1) th N-channel MOS transistor is turned off. The transistor NM21 turns on. At this time, since the input signal In is already at the H level, the first to n-th N-channel MOS transistors NM11,. . . , NM1n are turned on, and the first to n-th N-channel MOS transistors NM11,. . . , NM1n and the (n + 1) th N-channel MOS transistor NM21, the dynamic node Dy_node is discharged, and the potential goes to L level. Therefore, the output signal Out at the H level is output from the signal output node.
[0022]
At time t4, when the precharge signal Prchg goes to the L level, the evaluation period of the circuit ends and the process shifts to the precharge period again. After time t4, the dynamic node Dy_node is gradually charged.
[0023]
In the conventional circuit shown in FIG. 5, since the third inverter INV3 outputs the output signal Out according to the potential of the dynamic node Dy_node, in the process of gradually charging the dynamic node Dy_node, the third inverter INV3 outputs the output signal Out. The transition of the level of the output signal Out to the L level corresponding to the precharge completed state cannot be determined until the potential exceeds the separation threshold of the inverter, for example, until time t5.
[0024]
On the other hand, in the semiconductor integrated circuit according to the first embodiment of the present invention, a two-input NOR logic circuit NOR1 is provided instead of the third inverter INV3, and one input of the NOR logic circuit NOR1 has a precharge signal Prchg. The inverted signal is input, and the potential of the dynamic node Dy_node is input to the other input.
[0025]
Therefore, at time t4, when the precharge signal Prchg goes to L level, the output of the NOR logic circuit NOR1 goes to L level immediately, and without waiting for the charging of the dynamic node Dy_node, the start of the precharge period and the next stage of the circuit The transition of the level of the output signal Out as an input signal to the subsequent state can be determined to the L level corresponding to the precharge completion state.
[0026]
As a result, in the semiconductor integrated circuit according to the first embodiment of the present invention, it is possible to prevent a malfunction in relation to other circuits connected to the next and subsequent stages of the circuit.
[0027]
FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to the second embodiment of the present invention.
[0028]
In the semiconductor integrated circuit according to the second embodiment of the present invention, the first P-channel MOS transistor PM11 whose source is connected to the power supply potential node and the drain are commonly connected to the drain of the first P-channel MOS transistor PM11 The first to n-th (n is a natural number) N-channel MOS transistors NM11,. . . , NM1n and drains of the first to n-th N-channel MOS transistors NM11,. . . , NM1n connected to a commonly connected source, the source of which is connected to the ground potential node, an (n + 1) th N-channel MOS transistor NM21, a precharge signal input node, a first P-channel MOS transistor PM11 and an (n + 1) th N-channel MOS transistor PM11. First and second inverters INV1 and INV2 connected in cascade between the gates of the channel MOS transistors NM21, an output node of the first inverter INV1 is connected to one input, and a first to a second input is connected to the other input. n N-channel MOS transistors NM11,. . . , NM1n are connected to each other, and a two-input NOR logic circuit NOR1 whose output node is a signal output node is connected to one input, the output node of the second inverter INV2 is connected, and the other input is connected to the other input. A two-input OR logic circuit OR1 to which an output node of the input NOR logic circuit NOR1 is connected, a power supply potential node and first to n-th N-channel MOS transistors NM11,. . . , NM1n, and a second P-channel MOS transistor PM12 having a gate connected to the output node of the two-input OR logic circuit OR1.
[0029]
That is, the semiconductor integrated circuit according to the second embodiment of the present invention includes a two-input OR logic circuit OR1 and a precharge in addition to the configuration of the semiconductor integrated circuit according to the above-described first embodiment of the present invention. An auxiliary second P-channel MOS transistor PM12 is further provided.
[0030]
FIG. 4 is a timing chart showing signal waveforms at main nodes of the semiconductor integrated circuit according to the second embodiment of the present invention.
[0031]
The operation of the semiconductor integrated circuit according to the second embodiment of the present invention will be described with reference to FIGS.
[0032]
The operation of the semiconductor integrated circuit according to the second embodiment of the present invention is completely the same as the operation of the semiconductor integrated circuit according to the first embodiment of the present invention before time t4, and after time t4. The operations relating to the determination of the transition of the level of the output signal Out are exactly the same, so that the description of those operations will be omitted, and only different operations will be described.
[0033]
At time t4, when the precharge signal Prchg goes to L level, the evaluation period of the circuit ends and the precharge period starts, and after time t4, the dynamic node Dy_node is gradually charged. In the semiconductor integrated circuit according to this embodiment, the output signal Out, which is the output of the NOR logic circuit NOR1, also goes low at the same time that the precharge signal Prchg goes low, so that the output of the OR logic circuit OR1 also goes low. And the second P-channel MOS transistor PM12 is turned on.
[0034]
Therefore, the dynamic node Dy_node is charged not only by the first P-channel MOS transistor PM11 but also by the second P-channel MOS transistor PM12. As a result, the charging time of the dynamic node Dy_node can be reduced to about half.
[0035]
In the case where the dynamic node Dy_node is charged only by the first P-channel MOS transistor PM11, the potential of the dynamic node Dy_node completely reaches the H level, for example, until the time T6. In the semiconductor integrated circuit according to the second embodiment, since the dynamic node Dy_node is charged by the two P-channel MOS transistors, the charging of the dynamic node Dy_node can be completed, for example, by time t5.
[0036]
During the evaluation period, the output of the OR logic circuit OR1 is at the H level and the second P-channel MOS transistor PM12 is turned off, so that the potential control of the dynamic node Dy_node is not adversely affected.
[0037]
【The invention's effect】
According to the embodiment of the semiconductor integrated circuit according to the present invention, the transition of the level of the output signal can be determined at the same time as the start of the precharge period without waiting for the charging of the dynamic node using the precharge signal. In addition, it is possible to prevent a malfunction in relation to another circuit connected to the next and subsequent stages of the circuit.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart showing signal waveforms at main nodes of the semiconductor integrated circuit according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 4 is a timing chart showing signal waveforms at main nodes of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing an example of a conventional CMOS dynamic circuit.
[Explanation of symbols]
PM11, PM12 P-channel MOS transistors NM11,. . . , NM1n, NM21 N-channel MOS transistors INV1, INV2, INV3 Inverter NOR1 NOR logic circuit OR1 OR logic circuit

Claims (2)

A P-channel MOS transistor having a source connected to the power supply potential node;
A first to an n-th (n is a natural number) N-channel MOS transistors each having a drain commonly connected to a drain of the P-channel MOS transistor and an input signal input to each gate;
An (n + 1) th N-channel MOS transistor having a drain connected to a commonly connected source of the first to n-th N-channel MOS transistors and a source connected to a ground potential node;
First and second inverters cascaded between a precharge signal input node and gates of the P-channel MOS transistor and the (n + 1) -th N-channel MOS transistor;
An output node of the first inverter is connected to one input, a commonly connected drain of the first to nth N-channel MOS transistors is connected to the other input, and the output node is a signal output node. A two-input NOR logic circuit;
A semiconductor integrated circuit comprising: A two-input OR logic circuit having one output connected to the output node of the second inverter and the other input connected to the output node of the two-input NOR logic circuit;
A precharge auxiliary P-channel MOS connected between a power supply potential node and a commonly connected drain of the first to n-th N-channel MOS transistors, and having a gate connected to an output node of the two-input OR logic circuit Transistors and
The semiconductor integrated circuit according to claim 1, further comprising:

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