JPH02186827A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a pre-charge control means to stop pre-charge when an input transistor is energized. CONSTITUTION:The pre-charge control means 10 consisting of an N-channel transistor 4 for pre-charge control, a P-channel transistor 5 which sets a node B at 'H', and an N-channel transistor 6 which sets the node B at 'L' setting the node A of the common connection point of an N-channel transistor 3b as the input transistor and an N-channel transistor 2b for discharge as a control signal is provided. When the input transistor 3b is energized and the discharge of an output node is decided, the pre-charge is stopped by the pre-charge control means 10. In such a manner, it is possible to suppress wasteful pre-charge to a minimum, and to obtain a semiconductor integrated circuit with low power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to reducing power consumption in dynamic logic circuits such as PLA.

[Conventional technology]

A conventional dynamic logic circuit, here, a two-phase lock type PLA as shown in FIG. 6 described in "How to Make and Use an rPLA (Nikkan Kogyo Shimbun)" will be explained. In FIG. 6, 1a is a P-channel transistor that precharges the AND plane, 1b is a P-channel transistor that precharges the OR plane, 2a is A,
2b is an N-channel transistor that discharges the ND plane, 2b is an N-channel transistor that discharges the OR plane, 3a is an N-channel transistor that configures the logic of the AND plane, 3b is an N-channel transistor that configures the logic of the OR plane, and 8 is a 1-bit transistor. Decoder 9 is an output buffer.

In addition, XI + 2 + x3 are human signals,
:JI+y2+'i3 are AND plane output signals, and f, , f2 are output signals, respectively.

Next, the operation will be explained. Here, in order to explain the operation shown in FIG.
This will be explained using an equivalent circuit as shown in the figure.

The entire system including this PLA has clocks φA, φB
, φC2φD, x+=“L”
It is assumed that the signal is fixed at x3=“H”. At this time,
y, is fixed at ``L''. PLA is clock φ
Precharge the AND plane with A and OR with clock φB
Precharging the plane. Now, the input signal x2 is “
Consider the case where the output signal y2 changes from "H" to "L" or the case where it remains "L". At this time, it is assumed that the output signal y2 is sufficiently determined by the fall of the clock φB, and
2=“H”. The output signal f1 is precharged at one end by the clock φB, but since y2="H", the output signal f1 is eventually discharged to "L". A timing chart at this time is shown in FIG.

[Problem to be solved by the invention]

In this way, in conventional dynamic logic circuits,
In the case of a circuit where the input signal (output signal y2 in this case) is determined before precharging the output node, unnecessary precharging may occur even when the output node is discharged depending on the value of the input signal. Therefore, there was a problem that power consumption increased.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a dynamic logic circuit that can reduce power consumption by controlling unnecessary precharging of an output node.

(Means for Solving the Problems) A semiconductor integrated circuit according to the present invention is provided with a precharge control means that stops precharging when a human-powered transistor becomes conductive.

[Effect]

In this invention, when it is determined that the human transistor is conductive and the output node is discharged, the precharge control means stops the precharge.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a configuration diagram for explaining an embodiment of the semiconductor integrated circuit (OR plane of CMO3 type PLA) of the present invention.

In this figure, the same symbols as in FIG. 6 indicate the same things, and 4 is an N-channel transistor for precharge control;
5 is a P-channel transistor that makes node B H''; 6
are the N-channel transistor 3b as an input transistor and the N-channel transistor 2b for decharging.
The common connection point of node A is used as a control signal, and node B is “
10 is a precharge control means, and φB is a clock.

Here, all human output signals y2 to yn are “L”
It is assumed that the output signal y1 is sufficiently determined by the falling edge of the clock φB.

Now, when the output signal y1 is "L", the node A is "L" and the N-channel transistor 6 is in the OFF state.

In addition, except when φB="L", that is, when precharging is not being performed, the P channel transistor 5 is in the ON state by the clock φB, and the node B is at H''. N-channel transistor 4 is in the ON state, and φB="
When it becomes "L", the P-channel transistor 1b turns on and starts precharging, and the output signal f1 becomes "H".
becomes. At this time, all output signals yI to y2 are “L”
Therefore, node A remains at "L" and there is no change in the voltage at node B, so a normal precharge operation is performed.

Next, the case where yl; "H" will be explained.

11="L", the node A becomes "L". Therefore, N-channel transistor 6 is in an OFF state. Furthermore, since φB="L", the P channel transistor 5 is in the ON state, and the node B is in the "H" state. Therefore, the N-channel transistor 4 for precharge control is in the ON state. Then, when φB becomes “L”, the P-channel transistor 1b for precharging is turned on.
state and starts precharging. At this time 3't
="H", the transistor to which the output signal y1 is input of the N-channel transistor 3b is in the ON state, and the node A also begins to be recharged. As a result, N-channel transistor 6 is turned on. So φ
Since the P-channel transistor 5 is in the OFF state due to B="H", the node B is discharged "
Therefore, the N-channel transistor 4 for precharge control becomes OFF, and the precharge ends in the middle of the precharge period.In other words, φB becomes "H" and the N channel transistor 4 for discharge becomes OFF.
This means that the channel transistor 2b is turned on, and wasteful discharge when discharging the output signal f1 and the capacitance of the node A is minimized.

A timing chart at this time is shown in FIG.

In the above embodiment, the precharge control transistor is composed of the N channel transistor 4, but the P
It may also be configured with a channel transistor. In this case, the circuit becomes as shown in FIG. 7 is an inverter.

Further, in the above embodiment, the OR plane of PLA has been described, but it can also be applied to other dynamic logic circuits. The configuration diagrams at that time are shown in FIGS. 4 and 5.

In these figures, the same symbols as in FIG. 1 indicate the same things, and 1 is a P-channel transistor for precharging;
2 is an N-channel transistor for discharge, 3 is a logic gate group, φ1. φ1 is a clock.

(Effects of the Invention) As described above, according to the present invention, since a precharge control means is provided that stops precharging when the input transistor becomes conductive, unnecessary precharging is minimized without increasing the layout area. This has the effect that a semiconductor integrated circuit with low power consumption can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a timing chart showing the operation of FIG. 1, and FIGS. 3 to 5 are block diagrams showing other embodiments. Figure 6 is a circuit diagram of a conventional two-phase lock type PLA, and Figure 7 is a circuit diagram of a conventional two-phase lock type PLA.
FIG. 8 is a timing chart showing the operation of FIG. 7. In the figure, 1. la, 1b, and 5 are P-channel transistors; 2.2a, 2b, 3a, 3b, and 4 are N-channel transistors; and 3 is a logic gate group. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) 1st stomach diagram

Claims (1)

[Claims] A precharging transistor and a discharging transistor are connected in series between a first power source and a second power source and are alternately conductive, and an input transistor is connected in series between these transistors. 1. A semiconductor integrated circuit having an output node between a charging transistor and an input transistor, characterized in that the semiconductor integrated circuit is provided with precharge control means for stopping precharging when the input transistor becomes conductive.