JPH01248827A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the competition of an inverter 3 and a 3-state output buffer by assuring a bus level with a holding circuit composed of an inverter and the switching transistor in a connecting state only when a bus goes to floating condition for a long period and while is in a state of the bus always being driven, a switching transistor is turned into a non-connecting state. CONSTITUTION:The output of a control circuit 9 is added to a control terminal C of a 3-state circuit 8, and thus, when a bus goes to a long period floating, a transistor switch 7 is energized, the output of an inverter 2 is connected through a terminal 3 to the bus and when a holding circuit is formed by an inverter 1.2, the potential of the bus is stabilized. While the bus is always being driven, the transistor switch 7 turns to the non-energizing state, the bus connected through the inverter 2 and the terminal 3 is disconnected and the competition of all 3-state buffers connected to the bus is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that has a three-state output buffer and specifies an output level when the buffer is in a signal propagation inhibited state.

[Conventional technology]

Conventionally, in a three-state output buffer of a semiconductor integrated circuit (hereinafter abbreviated as IC), multiple drive systems, typified by the address bus and data bus of a computer system, are connected to a single wire, as shown in Figure 4. It is used to drive buses.

However, the bus is driven by at most one 3-state output buffer, and in some cases has a state in which it is not driven by any drive system for a long time, i.e., the bus is in a floating state and the bus potential is It changes over time due to the discharge of the charge stored in the capacitor.

At this time, the intermediate potential of the gate input connected to the bus remains in a very unstable state for a long period of time, leading to the generation of erroneous signals and, in the case of CMOS ICs, to the destruction of the IC due to the through current. .

Recently, as shown in Figure 2, a holding circuit 10 consisting of a loop of two inverters has been added to the 3-speed output buffer of an IC containing a CPU that has the right to use the bus. The bus potential is now guaranteed when the device is in a floating state.

[Problem to be solved by the invention]

In the holding circuit 10 using the inverter 2 loop attached to the conventional three-state output buffer described above, the inverter 2 is always in the state of driving the bus, which is good when the bus is in a floating state for a long period of time. However, as shown in FIG. 3, once the 3-state output buffer 4 enters the signal propagation state and attempts to drive the bus 12, the output of the inverter 2 and the output of the 3-state output buffer 4 compete, and the 3-state output buffer 4 4, a sum current i of the charge/discharge current i1 of the large capacitor 11 attached to the bus 12 flowing in the same direction and the through current 12 flowing between the inverter 2 flows.

However, the maximum value of the current i that can flow through the 3-state output buffer 4 is determined by the dimensions of the drive MOS transistors 5 and 6, and the current 11 that charges and discharges the stray capacitance 11 of the bus by the amount of through current 12 flowing = i - i2 becomes smaller. That is, the ability of the 3-state output buffer 4 to drive the bus 12 is weakened, resulting in a slow signal propagation speed.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a 3-state output buffer, and includes a 3-state circuit whose input and output terminals are connected to the 3-state output buffer and whose inputs and outputs are in phase with each other, and the 3-state circuit. The device is configured with a control circuit that controls the output state of the device.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention.

A 3-state output buffer 4 is connected to a terminal 3 of the IC, forming an IC with a 3-state output buffer. Here, when a high level is applied to the inverter 2 and the control terminal C, the input I and output O of the 3-state circuit 8 formed by the transistor switch 7 which becomes conductive are connected to the terminal 3 of the IC.
It is connected to the. In addition, the control terminal C of the 3-state circuit 8
The output of the control circuit 9 is connected to.

Here, the control circuit 9 receives signals that cause the bus to be in a floating state for a long period of time in a general computer system, as well as reset (RESET) and hold (HOLD) signals, and creates a logical sum thereof. Therefore, the output of the control circuit 9 is a signal indicating that the bus will be floating for a long period of time. Therefore, by applying the output of the control circuit 9 to the control terminal C of the three-state circuit 8, when the bus is floating for a long period of time, the transistor switch 7 becomes conductive, and the output of the inverter 2 is connected to the bus via the terminal 3. The inverter 2 forms a holding circuit and stabilizes the bus potential.

In addition, when the bus is constantly driven, that is, when the output of the control circuit 9 is at a low level, the transistor switch 7 becomes non-conductive, and the bus connected to the inverter 2 through the terminal 3 is disconnected. This prevents conflicts with all 3-state buffers that are used.

Therefore, the through current 12 flowing between the inverter 2 and the 3-state output buffer 4 shown in FIG. 3 does not occur.

In the above explanation, a 3-state output buffer is used as an example, but the same is true for a human output buffer, and the 3-state circuit 8 and control circuit 9 have not only the same structure but also the same function as shown in FIG. It is clear that similar effects can be obtained with other configurations and the object of the present invention can be achieved.

〔Effect of the invention〕

As explained above, the present invention guarantees the bus level using the holding circuit consisting of the inverter 2 and the switching transistor 7 in the conductive state only when the bus is in a floating state for a long period of time, thereby preventing malfunctions of the peripheral circuits. In order to prevent destruction, and in a state where the bus is constantly driven, the switching transistor 7 is made non-conductive, so that the inverters 2 and 3 are
This has the effect of preventing contention with the state output buffer 4 and enabling high-speed signal propagation.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, Fig. 2 is an example of a conventional circuit, and Fig. 3 is a diagram showing current paths in a conventional circuit. Figure 4 shows an example of bus configuration in a general computer system. 1, 2... Inverter, 3... IC terminal, 4...
・3-state output buffer, 5...P channel MOS
Transistor, 6... N-channel MoS transistor, 7... Transistor switch, 8... 3-state circuit, 9... Control circuit.

Claims (1)

[Claims] In a semiconductor integrated circuit having a 3-state output buffer, a 3-state circuit whose input and output terminals are connected to the 3-state output buffer and whose input and output are in phase, and a control circuit that controls the output state of the 3-state circuit. A semiconductor integrated circuit characterized by comprising: