JPS58179994A - Latching circuit - Google Patents

Abstract

PURPOSE:To accelerate the operation and to reduce the pattern area, by providing a clocked inverter circuit to each output terminal of plural ROMs and supplying the output of an NAND circuit which works synchronously with the clock of the clocked inverter circuit to a refresh circuit. CONSTITUTION:The outputs B and C of ROM111 and 112 have the rise up to level ''1'' while a clock signal phiA is set at level ''0'' and then exceed the threshold values Vth3 and Vth4 of clocked inverter circuits 161 and 162 respectively. Thus the outputs D and E are inverted and supplied to an NAND circuit 20. The circuit 20 is synchronized with a signal phiA. The output F of the circuit 20 is set at level ''1'' if the outputs D and E of the circuits 161 and 162 are set at level ''0'' while the signal phiA is kept at level ''0''. This state is kept by refresh circuits 21 and 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a latch circuit used, for example, in a multi-stage serial type read-only memory (ROM) that requires high-speed logic operation.

[Technical background of the invention and its problems]

Generally, the output latch circuit of a multi-stage series ROM is the first
It is configured as shown in the figure. That is, ROM11
The clock signal φ is supplied to the N-channel type MU8) transistor Tr1 for precharging, which is arranged between the power supply voltage and the power supply voltage, and the conduction is controlled. Since the address line maintains a discharged or charged state, the stored information can be read by detecting this state. The charge/discharge signal is latched by the clocked inverter circuit 11 synchronized with the clock signal -A, and the output of the inverter circuit 12 is outputted from the inverter circuit IS and the clocked inverter circuit 11 synchronized with the clock signal 1A. inverter circuit I4
The output signal is supplied to a four-circuit circuit that maintains the state of the output signal, and is configured to obtain an output OUT corresponding to the information stored in the ROM II.

However, with the above configuration, if the number of series-connected transistors constituting the %ROMJ is large, the time required for one logic to occur will be longer. The number of stages is reduced and each is wrapped with a common clock signal. In this case, ROMI 1. and 11. logic at the same time!
Only when the 0+e level is reached, a 10 level signal is output from the NOR circuit 15 in synchronization with the clock signal φ^.If the ROM is divided into multiple parts in this way, the latch circuit In other words, if the circuit shown in Fig. 2 is configured with a CMO8 circuit, the NOR circuit 15 has a portion where transistors other than the clock input are connected in series when viewed from the output side, so the on-resistance increases. This is because the input of each transistor connected in series has a value close to the intermediate level of the power supply voltage, so the ff-) bias of each transistor is a shallow value, and also because it is a series structure. This is because both transistors are affected by the pack gate, which further increases the on-resistance.Therefore, in this circuit, as shown in FIG.
Compared to the circuit shown in the figure, the circuit threshold value vth of the latch circuit is increased, and it takes a long time for the change in the output of R(')M to be transmitted, so that no great effect can be obtained.

In order to eliminate such drawbacks, it is necessary to reduce as much as possible not only the liJM but also the number of series stages of transistors forming the latch circuit as viewed from the output side. Therefore, 1
A circuit as shown in FIG. 34 can be considered. In this circuit, ROM11, . 21. The outputs of clocked inverter circuits IJ, 16. The outputs of the respective inverter circuits 1138 and 1g are supplied to the inverter circuits 17. , III, and I2. .

The output state is maintained by supplying it to a refresh circuit consisting of I8 snow 12, and the output of this refresh 1 circuit is sent to a NOR circuit 1.
9 to obtain the output OUT.

According to such a configuration, the number of series stages of transistors connected from the output side can be reduced, so that the operation can be made faster. However, because the refresh circuit for holding data latches the output of the RAM set to 1 division, the RO
M.I.I.

Since only the number corresponding to 11, .

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to use a large T4 that can operate at high speed.
The purpose is to provide a latch circuit with a relatively small turn area.

[Summary of the invention]

That is, in this invention, R
A clock Y inverter circuit is provided at each output end of the OM, and the output of each clocked inverter circuit is synchronized with the same clock signal as that of the clocked inverter circuit, or a clock signal with a cycle longer than this clock signal. The output from the -E NAND circuit is supplied to a refresh circuit to maintain the output state.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 5 shows its configuration, with R set as one division.
The output of the OM is latched and shaped using a latch clock, and each shaped output signal is latched and synthesized using the same clock signal. In other words, FLOM that is set to be divided into multiple
II.

11 Supply the output of the clock door synchronized with the clock signal φ/4-9 times y4rgl, rg* twice,
This clocked inverter circuit 1g.

1#1 is supplied to a NAND circuit 20 synchronized with clock signal φA. The output of this NAND circuit 20 is supplied to a refresh circuit consisting of inverter circuits 21 and 21 to hold the state and obtain an output signal OUT.

In the above configuration, the operation will be explained using the timing chart shown in FIG. Clock signal -6 is 10
``ROMIX during the level.

and 11. Outputs B and C are at 11” level (power supply voltage
), the inverter circuit 16. .

16, the circuit threshold values Vths and Vtha are exceeded, and the output thereof, E, is inverted and supplied to the NAND circuit 2o. Since the NAN P circuit 2o is synchronized with the clock signal φ, when the clock signal φA is at the 00'' level, the inverter outputs 1M11111σ, and when both E are at the 0'' level, its output 1 becomes 1. level, and this state is maintained by the refresh circuit.

According to such a configuration, ROMII.

11x output inverter circuit 1g,, 1g.

Therefore, the output state can be set more quickly than the NOR circuit of the circuit shown in FIG. 2 described above. This is because when the NOR circuit is configured with 8 CMO circuits as described above, there is a part where transistors are connected in series when viewed from the output side, so the on-resistance of this transistor becomes high, and ε increases until the output state is set. This is because it requires a long time. Further, the number of elements can be reduced compared to the circuit shown in FIG.

By the way, when the ROM output is unstable or the output rises late, there is a period when both the P-channel type and Nf Yarnel type MOS transistors that make up the inverter circuit are in the on state, and a through current flows. Since latching is performed using the same clock as the latch clock, power consumption does not increase.

In the above embodiment, the clocked inverter circuit 1
! ;1.1g, and the clock signal supplied to the NAND circuit 20 using the same clock signal φ
However, the clock signals supplied to the NAND circuit 20 do not have to be the same as long as they are slower synchronized clock signals than the clock signals supplied to the inverter circuits 1g, 1g.

〔Effect of the invention〕

As explained above, according to the present invention, a latch circuit that is capable of high-speed operation and that does not increase the mother turn area can be obtained.

[Brief explanation of the drawing]

Figures 1 and 9142 are diagrams showing conventional latch circuits, Figure 3 is a timing chart to explain the operating speed of the circuits in Figures 1 and 2, and Figure 4 is a high-speed diagram. FIG. 5 is a diagram showing a latch circuit according to an embodiment of the present invention, and FIG. 6 is a timing chart for explaining the operation of the circuit shown in FIG. 5. 11K, 11 mushrooms...ROM, fσ,, 11j,...
・) ya track input arm-to-back circuit, 2 o... NAND circuit, 21.2: I... inverter circuit (refresh circuit), φ arm, 1 person... rear clock signal. Applicant's Representative Patent Attorney Takehiko Mikie Figure 1 Canopy Figure 2 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] multiple clocked inverter circuits that latch signals;
The output of the clocked inverter circuit is supplied to a NAND circuit which is synchronized with the same clock signal as the clock P inverter circuit or a clock signal slower than this clock signal, and the output of the NAND circuit is supplied with this clock signal. A latch circuit comprising four circuits for holding an output state.