GB2120034A - Clocked logic circuit - Google Patents

Abstract

An improvement in the basic domino circuit to reduce sensivity to leakage and noise. It basically involves addition of an unclocked small beta p-type pull-up transistor (17) in shunt with the clocked large beta p-type pull-up transistor (13) between the high power terminal and the output node (14) of each stage. This added transistor is operated with its gate so connected that it provides pull-up current to the output node during the evaluation phase when the large beta transistor is turned off.

Description

SPECIFICATION Improvements in or relating to integrated circuits This invention relates to integrated circuits.

There has been increasing interest in integrated circuits using both n-channel and p-channel enhancement mode field-effect transistors because of the improved noise and low power dissipation properties of such circuits. Hereinafter it should be assumed that all ofthetransistors included are ofthe enhancement type unless otherwise indicated. The terms "nchannel", "NMOS", and "n-type" transistor refer to a transistor with an n conductivity type source and drain, while the letter "p" refers to p-type conductivity.

lnafullycomplementaryCMOS circuit in which each p-type transistor is paired with a corresponding n-type transistor, the logic function of each gate is implemented twice, once in the array of p-type transistors and again in the array of n-type tansistors.

The advantage of using the two complete arrays is that exceptforthe brieftimewhen the outputs or inputs are making transitions no currentflows and no power is consumed. However, the problem of this approach is the large amountofarea needed to house thetwo completearraysoftransistors. Moreover, the extra area and the extra transistors result in a large capacitive load which slows the speed ofthe circuit.

Forth is reason, NMOS technology early became the dominanttechnologyfor high speed logic, particularly since an NMOS transistor has a betterfigure of merit than a PMOS transistor because of the higher mobility of electrons. However, power dissipation can become a problem in large arrays basd on NMOStechnology.

To maintain the main benifits of CMOS technology withoutthe area penalty of complete duplication of the two arrays, there has been developed the circuit technique known as pseudo-NMOS. Pseudo-NMOS technology is a design technique which uses circuits identical to those in NMOS technology exceptforthe regular substituition of a p-channel transistorforthe load or pull-up n-channel transistor. However, a problem with this approach is that pull-up current always flows in the pseudo-NMOS circuit even if the logicnetworkis pulling down. This slowsthe pull down.Makingthepull-upcurrentverysmallwould not solve the problem because then the pull-up would be very slow. Asa result, the speed of CMOS technology and that of pseudo-NMOS technology tends to be nearly the same and the trade off in choosing one orthe other technology is between the low power consumption of CMOS technology and the low area of the pseudo-NMOS technology. As conventionally used term such as "pull-up", "pull-down" and "level" referto relativevoltages; e.g. itis common to refer to a voltage increase as a "pull-upto a higher level".The term "dynamic" as used herein refersto a circuit in which the main current path through the drivertransistors is intermittently interrupted by a clock-operated switch, while "static" refers to a circu it that does not require such interruption. "Evaluation" refers to the logic computation phase To achieve circuitswhichcombine both towcapaci- trance and high current capability, various forms of dynamic pseudo-NMOS circuits have been developed.Typically, such a circuit includes a network or cluster of n-type driver transistors interconnected to implement a logic function, a p-type pull-up transistor connected between the high level of the power source and the output node ofthe network, and an n-type pull-down or ground switch transistor connected between the low level ofthe power source, typically ground, and otherorsecond node of the network. In operation, the gate electrodes ofthe pull-up and the pull-down transistors are clocked together for precharging the output node ofthe network to a high level while the current path to the low level is turned off because the ground switch is open. Changing of logic inputs to the network occurs during the precharge phase.At the completion of precharge, the clockturns off the pull-up transistor and turns on the pull-down transistor to close the ground switch and begin the evaluation phase. Depending on the states of the logic inputs to the network, the output will either continue to float high or be pulled down to a lower level.

Theoretically the advantage of a dynamic circuit is that its load capacitance is comparabie to that of a static pseudo-NMOS circuit but the full pull-down current is available with the result that fast speeds can be realised.

However, there are problems in realising these supposed speed advantages in practical circuits because such circuits generally have several logic networks in tandem. In the dynamic approach no network can be activated until its inputs have stabilised, and the time allowed for the networkto stabilise must be chosen so thateven the network with the longest delay can stabilise. Moreover, stabilisation is complicated because in each butthefirst stage the driver coupled to the output node of the preceding stage begins with its input atthe high precharge level of the output node ofthe preceding stage.Accordingly, it is often necessary to include some provision for delay in the evaluation phase of different drivers ofthe circuit, and this results in considerable increase in circuit complexity, particulaly when many stages are involved.

One approach that has been developed to meet this problem has been described as the CMOS domino circuit. In its preferred form, this technology too, as in the dynamic CMOS, utilises clusters of NMOS transis- torsforthe logic networks and uses PMOS transistors as precharge or load elements. As in a dynamic circuit, each output node is precharged to a higher voltage while the path to the low level, typically ground, is open and the precharge is stopped when the path to ground is closed. A significant difference is that the transition from precharge to evaluation is accomplished by means of a single clock edge applied simultaneously to all the drivers in the circuit. To make this practical, it is important to ensure that in each stage but the first the inputs to any drivers coupled to the preceding stage are all low before the start of the evaluation phase. To this end, a static inverter is included as a buffer between the output node of one domino stage and the input circuit node of the drivers in any next domino stage to be supplied by such output. During the precharge,whenthe output node is at the high precharge level, the buffer output is low so that all circuit nodes which connect the output of one domino stage to the input of any next domino stage are low and therefore the transistors they drive are off.

In addition during evaluation, such an input node of a succeeding domino stage can experience only a single type oftransition, namely from low to high. All such input nodes can make at most only such a transition during evaluation and then muststaythere until the next precharge when they again can experience only a single type oftransition, in this case from high to low.

Of course such nodes need not make any transition if they are already at the appropriate level. As a result there cannot be any deviations at any nodes in the circuit. Moreover, all the drivers may be switched from prechargeto evaluate with the same clock edge.

A pure domino CMOS circuit ideally has the low power of a dynamic circuit since there is never ad-c path to ground. Also the full pull-down current is available to drive the output nodes. Atthe same time the load capacitance is much smaller than forthe standard static CMOS because most of the p-type transistors have been eliminated from the load.

Meanwhile, the use of a single clock edge to activate the circuit provides simple operation and full utilisation of the speed of each gate.

One limitation is that each butthe last stage must be buffered with an inverter but this is not a significant problem since such buffering would generally have been needed for maximum speed.

However, in practice Applicant has found that, in a pure domino circuit, chargetendsto leave the output node as a result of leakage or noise and the operation tends to becme less reliable, particularly when many stages are involved.

According to this invention an integrated circuit includes a succession of logic network stages each being for receiving input logic signals for processing and including drivertransistors of one conductivity type, first and second power buses for receiving a steady potential difference, a prechargetransistor of a conductivity type opposite the one type connected between the first power bus and an output node of each stage and having a gate connected for receiving clock signals, a power switch transistor of the one conductivity type connected between the second power bus and a second node of each stage and having a gate connected for receiving the clock signals, and an auxiliaryprechargetransistor of a conductivity type opposite the one type connected betweenthefirst power bus and the output node of each stage and having a gate connected to a terminal which is notsupplied with clocksignals.

Thus a CMOS domino circuit may be modified by the connection between the output node and the high powerterminal of an improved form of precharge networks In particular in its preferred form based on NMOS logic networks, the improved precharge net workincludes both the standard p-type pull-up transistor whose gate is clocked to be off during the evaluation phase and an auxiiiary trickle-charge p-type transistor in shunt with the standard transistor butwhose gate is connected to trickle flow of some cu rrentto the output node during the evaluation phase.

In this arrangement, the clocked p-typetransistor is chosen two have a large beta for quickly precharging the output node when the circuit is not being evaluated, and the unlocked p-type transistor is chosen to have a small beta to have a small effect on the total pull-down current needed and so the power consumed during evaluation Preferablythissmaller trickle transistor is maintained on continuously by connecting its gate to the low level ofthe power supply,typicallyground. Alternatively, the gate ofthe smallertransistorcan betied to the output ofthe following inverterwhereby it is turned offwhen the inverter output is high.

The invention will now be described with reference to the accompanying drawing which is a circuit diagram of an illustrative quasi-static domino CMOS embodying the invention.

With reference now to the drawing, a cluster of two n-type enhancement modetransistors 11 and 12, connected in series to implementthe AND function, forms the first stage network. Apull-up p-type transistor 13 is connected between the high level Vdd bus ofthe power source and the output node 14 of the firststage.To serve asthe powerswitch, an n-type pull-down transistor 15 is connected between the low level Vss bus, typically ground, of the power source (not shown) and the other node 16 ofthe first logic network. An auxiliary p-type transistor 17 is also connected between the Vdd bus and the output node 14to trickle continuous charge to node 14.The main pull-uptransistor13 is chosen to have a beta considerably larger, typically a factor of four, than that ofthe auxiliary pull-up transistor 17 where beta is the ratio of channel width to channel length. The transistors 11 and 12 typically have betas smallerthan those oftransistor 13 and largerthan thatof transistor 17.

The gate electrode of transistor 13 and 15 are connected byway of a bus to a source C of clock pulses while the gate electrode of powerswitch transistor 17 is connected to the low level bus, or ground. Input information INP is applied to the gate electrodes ofthe driver transistors 11 and 12.

The second stage of the domino circuit comprises a logic network made up of a clusteroffive n-type transistors ofwhich four, 21,22,23 and 24, are connected in series to implement an AND function, and thefifth, 25, is connected in shunt across the fourto implementthe OR function with respectto the four.

Additionally, this stage includes its own main and axuiliary pull-up p-typpetransistors 26,27 and its n-type g round switch pull-down transistor 28.

Transistors 26 and 28 are clocked synchronously with transistors 13 and 15. Transistor 27 has its gate electrodetied to ground in the manner of transistor 17.

Input information is supplied to the gates of transis tors 22,23,24and 25.Thegate oftransistor 21 is supplied with the output of the first stage by way of the bufferformed by the static CMOS inverterformed by the p-type transistor 29 and the n-type transistor 30 connectedinthe usual fashion to provide inversion.

In a similarfashion,thethird stage comprises a cluster of three n-type transistors 31-33 ofwhich transistor 31,32 are in seriestoform an AND circuit and transistor 33 is connected in parallel across them to implementthe OR function. P-type transistors 34 and 35 and n-type transistor 36 correspond to transistors 26,27 and 28 and need neo further discussion. Input information is supplied to the gates oftransistors 32 and 33 while the gate of transistor 31 is supplied with the output ofthe second stage by way ofthestandard static CMOS inverterformed by p-type transistor 37 and n-type transistor 38.

Typicallytherewould be additional stagesformed by clusters of n-typetransistors connected to implement desired logic, and the output available at node 39 would be supplied to the gate of one ofthetransistors in the next stage also by way of a standard CMOS inverter.

The operation ofthe circuit is readily understood.

When the clock is low, all the clocked pull-up p-type transistors conduct and the clocked pull-down n-type transistors are turned off. As a resultthe output node 14 of the first stage is charged high, essentially to Vdd less the voltage drop experienced across the network formed bytransistors 13 and 17. The output nodes 39,40 ofthe othertwo stages will similarly be precharged high. The length of the clock pulse should be iong enough to ensure thatthe precharging is complete before the evaluation stage is begun.

At the same time as this precharging is occurring, the input pulses should be applied to the appropriate gates shown by lNP ofthe various driver transistors of the logic networks. During this time, because ofthe role of the inverters formed bytransistors 29,30 and 37,38 the inputs to the gates of drivers 21 and 31 will be low.

Atthis point, for evaluation the clock is switched to high, turning off the main pull-up transistors 13,26 and 34 and turning on the pull-down transistors 15,28 and 36. Then the conduction state ofthe various stages will be determined by the states ofthe input signals applied to the gate electrodes ofthe various drivers 11,12,22,23,24,25,32 and 33. Drivers 21 and 31 will be supplied with the complements of the outputs at nodes 14 and 40.

The presence oftransistors 17,27 and 35 ensures thatthe precharge voltage on nodes 14,40 and 39 will remain essentially at the value of Vdd less the small voltage drop assosiated with transmission through one pull-up network, making the circuit relatively insensitive to noise and leakage effect.

However, it is found that in some instances where the logic network includes a relatively large number of drivers in series, for example,three or more, that charge sharing may become a problem and that this can be alleviated by the inclusion of other clocked auxiliary pull-up, p-type transistors of small beta to provide currentto additional current-shy input nodes ofthe logic networks.

In particular, in the logic network of the second stage which includesfourdrivers in series to imple mentthe ANDfunction, and auxiliary pull-up p-type transistor 43 is connected between the high level terminal Vdd bus and the node 44 between drivers 21 and 22, and its gate is connected to the clockterminal.

Similarly the auxiliary pull-up, p-typetransistor45 is connected between the high level terminal Vdd bus and the node 46 between drivers 22 and 23 and its gate is connected to the clockterminal. The presence of such transistors ensures that the nodes 44 and 46 are pulled up essentially to Vdd when the ciock is low preliminary to the evaluation phase.

It can be appreciated that the clusters of n-type drivers forming each logic network may be interconnected in any manner appropriate to implement the desired logic without affecting the basic operation. In particular the output of any one stage after inverson may be applied simultaneously to morethan one driver of other logic networks. For example, it may be supplied to several parallel succeeding stages or even returned additionally to serve as an input in an earlier stage.

It should be apparent that if desired one can use the complementary domino arrangement in which the drivers ofthe logic networks are p-type enhancement mode transistors and in which the power switch would be a p-type transistor and the precharge networkwould employ n-typetransistorswith appropriate change in the polarities ofthe applied voltages.

Claims (7)

1. An integrated circuit including a succession of logic network stages each being for receiving input logic signals for processing and including driver transistors of one conductivity type, first and second power buses for receiving a steady potential difference, a precharge transistor of a conductivity type opposite the one type connected between the first power bus and an output node of each stage and having a gate connected for receiving clock signals, a power switch transistor ofthe one conductivity type connected between the second power bus and a second node of each stage and having a gate connected for receiving the clock signals, and auxiliary precharge transistor of a conductivitytype opposite the one type connected between the first power bus and the output node of each stage and having a gate connected to a terminal which is not supplied with clock signals.

2. Acircuit as claimed in claim 1 including an inverter connected between the output node of each stage, except the last, and an input node of a driver transistor of a succeeding stage.

3. A circuit as claimed in claim 2 wherein the inverter is a static CMOS inverter.

4. Acircuit as claimed in claim 1,2 or3wherein the transistors of the logic networkand the power switches are type, the precha rge transistors are p-type, the first power bus is the high potential bus, and the second power bus is the low potential bus.

5. Acircuitasclaimed in claim 4wherein the auxiliary precharge transistor gate is connected to the low potential power bus.

6. A circuit as claimed in any preceding claim including a second auxiliary prechargetransistor connected between the first power bus and a node between driver transistors of the stage which is neither the output node nor the second node, and having a gate connected for receiving the clock signals.

7. An integrated circuit substantially as herein described with reference to the accompanying drawing.