JPH09232942A - Semiconductor logic circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a high speed switching of an output signal in the operating state by setting a gate level of an output buffer to a logic threshold level of the output buffer just before the operation. SOLUTION: In the case of operation, a signal CK2 is set to an L level to make FET-MN2 nonconductive, a signal CK1 is set to an H level to make FET-MP1 nonconductive and to make a FET-MN1 conductive. Input signals IN1-TNn go to 'H', an n-channel logic block NLB is conductive, a level of a node Vp is decreased. When the level is lower than a logic threshold level of an INV1, an output is switched. in this case, since the node Vp just before is precharged to a VDD2 a little higher than the logic threshold level of the INV1, the level of the node Vp is lower than the logic threshold level of the INV1 immediately and an output OUT is switched from 'L' into 'H'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor logic circuit.

[0002]

2. Description of the Related Art As an example of a conventional semiconductor logic circuit, there is a domino circuit, which is a kind of dynamic circuit. This circuit configuration is shown in FIG. The operation waveform is shown in FIG. The circuit configuration of this domino circuit and its operation are described in, for example, "Principle of CMOS VLSI Design" (Tomizawa
(Translated by Matsuyama, Maruzen), pp. 141-144.

This circuit has a clock signal CK1 at its gate.
Is input, the source is VDD, the drain is node Vp
And a nMOS transistor MN1 having a gate to which the clock signal CK1 is input, a drain to which the node Vp is connected, and a source to which the n-type logic block NLB is connected via the node Vn. There is. Further, the inverter INV1 which is an output buffer receives the node Vp and outputs a signal to the output OUT.

The n-type logic block NLB includes a plurality of nMOs.
It is composed of an S-transistor, and the drain and source of the nMOS transistor are connected to each other to form a logic. Further, the source of the transistor in the lowermost layer of the n-type logic block NLB is connected to the ground, and the drain of the transistor in the uppermost layer is connected to the node Vn.
Nn is connected.

When the clock CK1 is at L level, the nMOS
The transistor MN1 becomes non-conductive, and the n-type logic block NLB is disconnected from the node Vp. Also, pMO
The S transistor MP1 is conductive and the node Vp is precharged to VDD. At this time, the output OUT is L level. This state is generally called a precharge state.

Since the output of the domino circuit is connected to the input of the domino circuit, the input IN1 is input in the precharge state.
~ INn is input with L level, and n-type logic block
All NLB transistors are non-conducting.

During operation, CK1 switches to H level, pMOS transistor MP1 becomes non-conductive, and nM
The OS transistor MN1 becomes conductive, and the node Vp is connected to the n-type logic block NLB. At this time, inputs IN1 to IN1
INn is still at L level, and the node Vp has the potential VDD.
It is in a floating state while maintaining. At this point, the domino circuit in the preceding stage operates and the output signal thereof switches from the L level to the H level. At this time, the nMOS transistor in the n-type logic block NLB to which the output signal is input becomes conductive, and the logic causes the n-type logic block NL.
B becomes conductive or non-conductive.

When the n-type logic block NLB becomes conductive,
When the potential of the node Vp is lowered by the logic block NLB and falls below the logic threshold potential V _th of the output buffer INV1, the output OUT switches from the L level to the H level. On the contrary, when the n-type logic block NLB is non-conductive, the node Vp remains VDD and is in a floating state, and the output OUT remains L level.

[0009]

In the domino circuit, when the potential of the node Vp starts to drop from VDD during operation and drops below the logical threshold potential V _th of the inverter INV of the output buffer, the output OUT changes from L level to H level. Switch to level. Therefore, if the potential of the node Vp is slightly higher than the logic threshold potential V _th during the precharge, the potential of the node Vp immediately drops below the logic threshold potential V _th during operation. You can That is,
The switching of the signal of the output OUT during operation can be speeded up.

However, when the node Vp is at the potential VDD2, a through current flows through the inverter INV1.
It is not desirable that the potential of the node Vp is always VDD2. Therefore, the node Vp is set to VD immediately before the operation.
A circuit for D2 is required. In addition, temperature, power supply voltage,
It is necessary to prevent VDD2 from falling below the logical threshold potential V _th even when the process or the like varies.

A first object of the present invention is to provide, just before operation,
Another object of the present invention is to provide a circuit form for increasing the speed by setting the gate potential of the output buffer to a potential VDD2 which is slightly higher than the logical threshold potential V _th .

A second object of the present invention is the above-mentioned object 1.
It is to provide a circuit form in which VDD2 of 1 is compensated so as to follow the fluctuation of the logical threshold potential of the output buffer.

[0013]

As means for achieving the above object, typical ones clearly shown by the present invention are shown below.

(1) A semiconductor logic circuit comprising a first logic circuit and a second logic circuit connected to the output of the first logic circuit, wherein a clock signal is input to the first logic circuit, The output of the first logic circuit based on the clock signal,
The control is performed so as to be substantially the logic threshold potential of the second logic circuit.

(2) In the above means (1), the first logic circuit powers the logic block NLB composed of a plurality of transistors and the output node Vp of the first logic circuit by the first clock signal CK1. A first transistor MP1 for precharging to a voltage and a second clock signal C
The second transistor MN1 connecting the node Vp and the logic block NLB by K3 is connected to the node Vp,
The third clock signal CK2 lowers the node Vp to approximately the logic threshold potential VDD2 of the second logic circuit.
The potential VDD2 is generated by connecting the source potential of MN2 to the ground and setting the conductance ratio of MN2 and MP1 to approximately 1.

(3) In the above means (1), the first logic circuit powers the logic block NLB composed of a plurality of transistors and the output node Vp of the first logic circuit by the first clock signal CK1. A first transistor MP1 for precharging to a voltage and a second clock signal C
A second transistor MN1 connecting the node Vp and the logic block NLB by K3, and a third clock signal CK
The third transistor MN2 that lowers the node Vp to the logic threshold potential VDD2 of the second logic circuit by 2
A dummy logic circuit having the same configuration and size ratio as the second logic circuit is connected to the source potential of MN2, and the potential VDD2 is generated using this dummy logic circuit.

In the means (2), the clock signal CK2 is driven to make the third transistor MN2 conductive immediately before the operation, and the node Vp is set to the logic threshold potential VDD2 of the second logic circuit. Lower to. In operation,
Since the potential of the node Vp immediately exceeds the logic threshold potential of the second logic circuit, the output of the second logic circuit switches at high speed.

In the above means (3), VDD2 is generated by connecting the input and output of a dummy logic circuit having the same configuration and size ratio as the second logic circuit. At this time, the potential VDD
2 is the logic threshold voltage of the dummy logic circuit, that is, the second
Becomes the same value as the logic threshold voltage of the logic circuit of
2 can be compensated so as to follow the variation of the logic threshold value of the second logic circuit.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a first embodiment of the present invention. Immediately before the operation, the gate potential of the output buffer is set to the logic threshold potential of the output buffer to reduce the delay time during the operation. It is the reduced domino circuit diagram. Further, FIG. 4 shows an operation waveform diagram of the first embodiment.

This circuit is an nMOS in which the clock signal CK2 is connected to the gate, the ground is connected to the source, and the node Vp is connected to the drain in the conventional domino circuit shown in FIG.
The circuit configuration is such that a transistor MN2 is newly provided. First, when CK1 and CK2 are set to L level together, M
N2 becomes non-conductive, the node Vp is precharged to VDD, the output becomes L level, and the state is the same as the precharged state of the conventional domino circuit.

Next, immediately before CK1 is switched to the H level to bring it into the operating state, CK2 is switched to the H level and MN
Conduct 2 At this time, the node Vp is pulled down to the ground by MN2. However, MP1 is conducting at this time, and the potential of the node Vp is determined by the ratio of the conductances of MP1 and MN2.

Now, if the ratio of the conductances of MP1 and MN2 is set to 1, the potential of the node Vp becomes almost half the potential of VDD. The potential VDD2 is set to a potential slightly higher than the logical threshold potential V _th of the inverter INV1, and the output is kept at L level. Hereafter, this node V
Ha is a state in which p is precharged to a potential VDD2 which is slightly higher than the logical threshold potential V _th of the inverter INV1.
Called lf-VDD precharge state.

During operation, CK2 is switched to the L level to make MN2 non-conductive, and CK1 is switched to the H level for M.
P1 is turned off and MN1 is turned on. Similar to the conventional domino circuit, the input signals IN1 to INn become H level, the n-type logic block NLB becomes conductive, the potential of the node Vp is lowered, and the logic threshold potential V _{th of} INV1.
When it goes down, the output switches. However, immediately before that, the node Vp changes to the logical threshold potential V _{th of the} inverter INV1.
Since it is precharged to a slightly higher potential VDD2, the potential of the node Vp immediately drops below the logical threshold potential V _th of INV1, and the output OUT switches from L level to H level. As described above, the transistor MN2 driven by the clock signal CK2 causes the node V
By setting p to a potential VDD2 slightly higher than the logical threshold potential V _th of INV1, the delay time during operation can be reduced.

FIG. 5 is a circuit diagram showing a second embodiment of the present invention. This circuit corresponds to the clock signal C of the first embodiment.
The circuit configuration is such that K1 is separated into a clock signal CK3 that drives the pMOS transistor MP1 that precharges the node Vp and a clock signal CK1 that drives MN1 that connects the n-type logic block NLB and the node Vp.

In the circuit of the first embodiment, in the Half-VDD precharge state, the potential of the node Vp is VDD2 (inverter IN depending on the conductance ratio of MP1 and MN2).
It is set to a potential slightly higher than the logical threshold potential V _{th of} V1). At this time, a through current flows from VDD through MP1, MN2 to ground.

In the circuit of this embodiment, in the Half-VDD precharge state, by setting the clock CK3 to the H level, MP1 can be controlled to be non-conducting so that the through current does not flow. At this time, the node Vp is the transistor M
Only N2 will gradually pull down to ground.
However, if CK2 is kept at H level, the node Vp is pulled down to the ground. Therefore, when the node Vp reaches VDD2, it is necessary to control CK2 to L level.

Incidentally, Examples 3, 4, 5 described below.
By separating the clock signals at 6 and 16 as in the present embodiment, the same effect that the through current does not flow can be obtained.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention. This circuit has a circuit configuration in which the source is connected to the ground, the nMOS transistor MN3 having the drain and the gate are connected, and the drain is connected to the source of MN2 in the first embodiment. In this circuit, M
The source potential of N2 is always higher than the threshold voltage of MN3. This can prevent the node Vp from dropping below the threshold voltage of MN3 in the Half-VDD precharge state. Further, by providing a plurality of MN3s and stacking them vertically, this effect can be doubled in the number of stacked vertically.

Incidentally, Examples 4, 5, 6, 1 described below
At 6, the same effect can be obtained by adding MN3 as in the present embodiment.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention. This circuit is the same as the first embodiment except that the gate is connected to the ground, the source is VDD, and the drain is the node V.
The circuit configuration is such that a pMOS transistor MP2 connected to p is newly provided. The conductance of MP2 is set to a value sufficiently smaller than the conductance of the logic block NLB and the transistor MN2.

In the first embodiment, when the output outputs the L level during the operation, the node Vp remains in the floating state with the potential VDD2 slightly higher than the logical threshold potential _Vth of INV1. At this time, even if the potential of the node Vp fluctuates due to noise, it does not return to the potential VDD2. This potential is I
When the voltage falls below the logical threshold potential of NV1, H level, that is, incorrect data is output.

In order to prevent this, in this embodiment, MP2
Therefore, the node Vp is raised to VDD to eliminate the floating state. Further, since the conductance of MP2 is set to a value sufficiently smaller than the conductance of the logic block NLB or the transistor MN2, it does not hinder the pulling down of the node Vp to the ground or the potential VDD2. However, after the clock signal CK1 is switched to the H level, the node Vp is set to V by the MP2 in the floating state until the inputs IN1 to INn are switched.
Since it is raised to DD, the effect of speeding up by setting the node Vp to VDD2 just before the operation described in the first embodiment is lost. Therefore, the inputs IN1 to I
It is desirable that the data of Nn be fixed before switching the clock signal CK1.

Incidentally, Examples 6, 7, 8 described below
Similar effects can be obtained by adding MP2 as in the present embodiment at 9, 12, 13, and 16.

FIG. 8 is a circuit diagram showing a fifth embodiment of the present invention. In this circuit, in the first embodiment, the n-type logic block NLB is replaced with a CMOS-type logic block CLB composed of CMOS, and a pMO in which a complementary signal of the clock signal CK1 is connected to the gate between CLB and the node Vp.
It has a circuit configuration in which an S transistor MP2 is added. In this circuit, during operation, the floating state of the node Vp is raised to VDD by the pMOS transistor in CLB. As a result, the same effect as that of the fourth embodiment can be obtained.

If it is not necessary to raise the node Vp to VDD, the pMOS transistor MP2 may be omitted. In this case, the node Vp is pulled up to a potential lower than VDD by the threshold voltage of MN1.

Incidentally, Examples 6, 7, 8 and
Similar effects can be obtained by replacing the n-type logic block NLB with the CMOS-type logic block CLB as in the present embodiment at 9, 12, 13, and 16.

FIG. 9 shows operation waveform diagrams of the fourth and fifth embodiments.

FIG. 10 is a circuit diagram showing a sixth embodiment of the present invention. In this circuit, in the first embodiment, the clock signal CK2 is connected to the gate and the drain is connected to VDD.
The nMOS transistor MN3 is connected to the output OUT, the drain is connected to the source of MN3, and the nMOS transistor MN4 having the node Vp connected to the source is newly provided.

Half-VDD CK in the precharge state
2 is at H level, node Vp is at VDD2 (potentially higher than the logical threshold value _{Vth of} INV1), output OUT is at L level, MN3 is conductive and MN4 is nonconductive. If VDD2 falls below the logical threshold potential _{Vth of} INV1 due to temperature, power supply voltage, process variations, etc., the output will switch to the H level. At this time, MN3 receiving the output OUT is rendered conductive, pulling up the node Vp to the high potential side and pulling down the output to the L level side. Thus, MN3 and M
Feedback from output OUT is applied by N4, VDD2
I try to reduce the fluctuation of. Half-VD
In a state other than the D precharge state, CK2 is at L level, MN3 becomes non-conductive, and this feedback circuit does not operate.

FIG. 11 is a circuit diagram showing a seventh embodiment of the present invention. This circuit is the conventional domino circuit of FIG.
A clock signal CK2 is applied to the gate between P1 and the node Vp.
The pMOS transistor MP3 connected to is inserted. Further, an inverter INV2 having the same circuit configuration and size ratio as INV1 in which the node Vp is connected to the input is provided, the node Vp is connected to the source, and the clock signal CK is connected to the gate.
The circuit configuration is such that the drain of the nMOS transistor MN2 connected to 2 is connected to the source of the node Vp, and the gate is connected to the drain of the pMOS transistor MP2 connected to the complementary signal of CK2 to the output of INV2.

In the circuit other than the Half-VDD precharge state, CK2 is at L level, MP3 is conducting, MP2 and MN2 are non-conducting, and the same operation as the conventional domino circuit is performed. . In the Half-VDD precharge state, CK2 is at H level and the complementary signal of CK2 is at L level.
As a result, MP3 becomes non-conductive and MP1 for precharging is disconnected from the node Vp. Also, M
N2 and MP2 become conductive, and the node Vp is connected to the output of INV2. That is, the input and output of the inverter INV2 are commonly connected to the node Vp, and the node Vp
The potential VDD2 of p becomes the logical threshold potential of INV2.

The circuit configuration and size ratio of INV2 is INV1.
Since it is the same as, the logical threshold potential of INV2 is IN
It has almost the same value as the logical threshold potential of V1. Therefore, the potential VDD2 in the Half-VDD precharge state is
It has almost the same value as the logical threshold potential of INV1. Therefore, it can be compensated so that VDD2 follows the variation of the logical threshold value of INV1.

FIG. 12 is a circuit diagram showing an eighth embodiment of the present invention. This circuit has a configuration in which the input of the inverter INV2 is separated from the node Vp and the output and the input are connected in the seventh embodiment of FIG. This circuit always connects the input and output of the inverter INV2 to generate a logical threshold potential of INV2, and during Half-VDD precharge, MP2 and MN2 are made conductive and the node Vp is I
The logic threshold potential of NV1 is set.

In this circuit, the parasitic capacitance of the node Vp is smaller than that of the seventh embodiment by the gate capacitance of INV2. Therefore, the speed can be increased as compared with the seventh embodiment. However, a through current always flows through the INV2, and the power consumption is higher than that in the seventh embodiment.

FIG. 13 is a circuit diagram showing a ninth embodiment of the present invention. This circuit has a circuit configuration in which a plurality of logic circuits of the eighth embodiment are arranged and INV2 of each is made common. In this circuit, in the eighth embodiment, the number of INV2 through which the through current always flows is made common to one, so that there is an advantage that the power consumption is smaller than that in the eighth embodiment. There is also an advantage that the layout area can be reduced.

FIG. 14 is a circuit diagram showing a tenth embodiment of the present invention, and is a diagram showing a circuit configuration in which a Half-VDD precharge function is applied to a general CMOS gate.
This circuit includes a pMOS transistor MP1 having a gate connected to a clock signal CK2 and an nMOS transistor MN1 having a gate connected to a complementary signal of CK2.
The output of the CMOS logic block CLB is connected to the node Vp via. Further, an inverter INV2 having an input connected to the node Vp is provided, and its output is passed through an nMOS transistor MN2 having a gate connected to the clock signal CK2 and a pMOS transistor MP2 having a gate connected to a complementary signal of CK2. The circuit configuration is such that it is connected to the node Vp.

This circuit is equivalent to a static operation CMOS logic gate constituted by CLB and INV1 when MP1 and MN1 are conductive and MP2 and MN2 are nonconductive when the clock signal CK2 is at L level. C
When K2 becomes H level, MP1 and MN1 become non-conductive, and the logic block CLB is disconnected from the node Vp.
In addition, MP2 and MN2 become conductive, and the input and output of the inverter INV2 are commonly connected to the node Vp. At this time, the node Vp becomes a potential that compensates for the logical threshold potential of the inverter INV1 as in the seventh embodiment. Thus, it normally operates as a CMOS logic gate and enters the Half-VDD precharge state immediately before the switching operation.

FIG. 15 is a circuit diagram showing an eleventh embodiment of the present invention. This circuit is the same as the tenth embodiment except that the inverter INV2 is excluded and the potential VD is applied to the sources of MP2 and MN2.
It has a circuit configuration in which a power source for generating D2 is connected.
In this circuit, the number of transistors in the gate is reduced by replacing the VDD2 generation circuit INV2 with the power supply VDD2 in the tenth embodiment.

FIG. 16 is a circuit diagram showing a twelfth embodiment of the present invention. This circuit has a circuit configuration in which a feedback circuit for preventing the node Vp from falling too much in the sixth embodiment is added to the seventh embodiment. However, the nMOS of the sixth embodiment
The transistor MN3 is replaced with a pMOS transistor MP4 whose gate is connected to a complementary signal of the clock signal CK2. When using nMOS transistor,
The node Vp does not rise above the threshold voltage of the transistor. However, if this is replaced with a pMOS transistor as described above, the node Vp can be changed to VDD.

FIG. 17 is a circuit diagram showing a thirteenth embodiment of the present invention. This circuit corresponds to the INV2 in the twelfth embodiment.
The transistor MP2 for connecting / disconnecting the output of the node Vp and the node Vp, and the transistor MP4 for turning on / off the feedback circuit for preventing the node Vp from falling too much are shown in FIG.
It is shared by 2. The drain of MN3 is connected to VDD and the source is connected to the output of INV2. Therefore, this circuit has an advantage that the number of transistors can be reduced as compared with the twelfth embodiment.

FIG. 18 is a circuit diagram showing a fourteenth embodiment of the present invention, showing a configuration example of a circuit for generating the clock signals CK1 and CK2 of the first embodiment. In this circuit, a certain clock signal CK and CK are the delay stages INVA _{1 to} INV.
Input the signal CKD1 that passed A _2n , and input the clock signal C
NOR gate NOR1 that outputs K2, signal CKD2 that CK passed through delay stage INVB, and CKD2
Enter the INVC ₁ ~INVC _{2m + 1} signals CKD3 having passed through the, is constituted by a NOR gate NOR2 outputs a clock signal CK1.

FIG. 19 shows the operation waveform of this circuit. In this circuit, the clock signal CK1 switches from L to H level when CKD2 switches from H level to L level, and switches from H to L at the timing when CKD3 switches from L level to H level. The pulse width of this CK1 is
It is the sum of the delay times of the delay stages INVC _{1 to} INVC _{2m + 1} . In addition, the clock signal CK2 has CKD1 from H to L.
The L level is switched to the H level at the timing of switching to the level, and the H level is switched to the L at the timing of switching of the CK from the L level to the H level.

Here, in CKD2, CK is the delay stage INV.
Since the signal has passed B, the timing at which CK1 switches from L to H is a timing delayed by the delay time of the delay stage INVB from the timing at which CK2 switches from H to L. Therefore, the timing of turning off the transistor MP1 of the first embodiment by CK1 and the timing of turning off the transistor MN2 of the first embodiment by CK2 can be made substantially the same.

FIG. 20 is a circuit diagram showing a fifteenth embodiment of the present invention, showing another example of the configuration of the circuit for generating the clock signals CK1 and CK2 of the first embodiment. This circuit is
A certain clock signal CK is delayed by the delay stages INVA _{1 to} INVA _2n.
Signal CKD1 that has passed through the delay stage INVB ₁ and INVB ₂ , and a signal CKD2 that has passed through the delay stage INVB1, and a signal CKD2 that has passed through the delay stage INVB1 and CKD2.
Signal CK that has passed through the delay stages INVC _{1 to} INVC _{2m + 1}
It is constituted by a NOR gate NOR2 which inputs D4 and outputs a clock signal CK1.

FIG. 21 shows an operation waveform diagram of this circuit. This circuit is similar to the fourteenth embodiment in that the timing for turning off the transistor MP1 of the first embodiment by CK1 and C
The timing of turning off the transistor MN2 of the first embodiment can be made almost the same by K2. However, in the fourteenth embodiment, this circuit is the clock signal CK input to NOR1.
Is delayed by the delay time of INVB ₁ and INVB ₂ . Therefore, contrary to the fourteenth embodiment, CK
CK2 switches from H to L at a timing delayed by the delay time of the delay stage INVB ₂ after 1 switches from L to H.

FIG. 22 is a circuit diagram showing a 16th embodiment of the present invention. This circuit shows a circuit configuration example in the case where the inverter INV1 of the output buffer is another logic gate in the first embodiment. In this embodiment, two-input N
The case of an AND gate is shown. In the second to thirteenth embodiments of the present invention, similarly, the inverter I of the output buffer is also used.
It is possible to make a circuit configuration in which NV1 is another logic gate.

[0057]

According to the present invention, since the gate potential of the output buffer can be made substantially the logical threshold value of the output buffer immediately before the operation, the switching of the output signal during the operation can be speeded up.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a domino circuit according to a first embodiment of the present invention.

FIG. 2 is a conventional domino circuit diagram.

FIG. 3 is an operation waveform diagram of the conventional example of FIG.

FIG. 4 is an operation waveform diagram of the first embodiment of the present invention.

FIG. 5 is a circuit diagram of the second embodiment of the present invention, in which a through current is prevented from flowing in MP1 of the first embodiment.

FIG. 6 is a circuit diagram of the third embodiment of the present invention, in which a transistor for preventing the potential VDD2 from falling too much is added to the first embodiment.

FIG. 7 is a circuit diagram of a fourth embodiment of the present invention in which a pMOS for floating prevention is added to the first embodiment.

FIG. 8 is a circuit diagram of the fifth embodiment of the present invention, in which floating is prevented by replacing the n-type logic block of the first embodiment with a CMOS-type logic block.

FIG. 9 is an operation waveform diagram of fourth and fifth embodiments of the present invention.

FIG. 10 is a circuit diagram of a sixth embodiment of the present invention, in which a feedback circuit for preventing VDD2 from falling too much is added to the first embodiment.

FIG. 11 is a circuit diagram of the seventh embodiment of the present invention, in which the potential VDD2 compensates the logic threshold value of the output buffer in the first embodiment.

FIG. 12 is a circuit diagram of the eighth embodiment of the present invention in which the VDD2 generation circuit of the seventh embodiment is separated from the node Vp.

FIG. 13 is a circuit diagram of the ninth embodiment of the present invention, in which the VDD2 generation circuit of a plurality of gates is shared in the eighth embodiment.

FIG. 14 is a circuit diagram of a tenth embodiment of the present invention, in which a Half-VDD precharge function is applied to a CMOS logic gate.

FIG. 15 is an eleventh embodiment of the present invention, which is a circuit diagram in the case of replacing the VDD2 generating circuit with a power supply in the tenth embodiment.

FIG. 16 is a circuit diagram of a twelfth embodiment of the present invention, in which a feedback circuit for preventing excessive decrease of VDD2 is added to the seventh embodiment.

FIG. 17 is a circuit diagram of the thirteenth embodiment of the present invention, in which the transistor for controlling on / off of the feedback circuit is removed in the twelfth embodiment.

FIG. 18 is a fourteenth embodiment of the present invention and is a generation circuit diagram of CK1 and CK2 of the first embodiment.

FIG. 19 is an operation waveform diagram of the fourteenth embodiment of the present invention.

FIG. 20 is a fifteenth embodiment of the present invention, which is a generation circuit diagram of CK1 and CK2 of the first embodiment.

FIG. 21 is an operation waveform diagram of the fifteenth embodiment of the present invention.

FIG. 22 is a circuit diagram of a sixteenth embodiment of the present invention in which the output buffer INV1 of the first embodiment is a NAND gate.

[Explanation of symbols]

NLB ... n type logic block, CLB ... CMOS type logic block, INV1, INV2 ... Inverter, NOR1,
NOR2 ... NOR type logic gate, NAND ... NAND type logic gate.

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tsuru Yamazaki 1-280, Higashi Koikeku, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Kenji Kaneko 1-280, Higashi Koikeku, Kokubunji, Tokyo Hitachi, Ltd. Central Research Center

Claims (7)

[Claims] 1. A semiconductor logic circuit comprising a first logic circuit and a second logic circuit connected to the output of the first logic circuit, wherein a clock signal is input to the first logic circuit, A semiconductor logic circuit characterized in that an output of the first logic circuit is controlled based on a clock signal so as to be substantially equal to a logic threshold potential of the second logic circuit. 2. A logic block, wherein the first logic circuit comprises a plurality of transistors, and a first transistor for precharging a node of the first logic circuit to a power supply voltage by a first clock signal. A second transistor that connects the node and the logic block with the second clock signal, and a third transistor that is connected to the node and lowers the node to substantially the logic threshold potential of the second logic circuit with the third clock signal. 2. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is configured by the transistor. 3. The first logic circuit comprises: a logic block including a plurality of transistors; and a first transistor for precharging a node of the first logic circuit to a power supply voltage by a first clock signal. A second transistor that connects the node and the logic block with the second clock signal, and a third transistor that is connected to the node and lowers the node to substantially the logic threshold potential of the second logic circuit with the third clock signal. A transistor, and the source potential of the third transistor is connected to ground,
2. The semiconductor logic circuit according to claim 1, wherein the logic threshold potential is generated by setting a conductance ratio between the third transistor and the first transistor to be approximately 1. 4. The first logic circuit includes a logic block composed of a plurality of transistors, and a first transistor for precharging a node Vp of the first logic circuit to a power supply voltage by a first clock signal. MP1; a second transistor that connects a node and a logic block by a second clock signal; and a third transistor that lowers the node to a logic threshold potential of the second logic circuit by a third clock signal. A dummy logic circuit having the same structure and size ratio as the second logic circuit is connected to the source of the third transistor, and the logic threshold potential is generated using the dummy logic circuit. 1. The semiconductor logic circuit described in 1. 5. A logic block in which the first logic circuit includes a plurality of transistors, and a first transistor connecting a node of the first logic circuit and the logic block by a first clock signal. , The node connected to the node, and is connected to the node by the first clock signal.
2. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is configured by a second transistor that lowers the logic threshold potential of the logic circuit. 6. A logic block in which the first logic circuit includes a plurality of transistors, and a first transistor that connects a node of the first logic circuit to the logic block by a first clock signal. A second transistor connected to the node and configured to pull down the node to substantially the logic threshold potential of the second logic circuit by the first clock signal, the source of the second transistor being connected to the second logic 2. The semiconductor logic circuit according to claim 1, wherein a dummy logic circuit having the same configuration and size ratio as the circuit is connected and the logic threshold potential is generated using the dummy logic circuit. 7. A timing at which the first clock signal and the third clock signal according to claim 2 are generated from the same clock signal, and the first transistor is turned off by the first clock signal. And a semiconductor logic circuit in which the timing of turning off the third transistor by the third clock signal is substantially the same.