GB8312322D0 - Integrated circuits - Google Patents
Integrated circuitsInfo
- Publication number
- GB8312322D0 GB8312322D0 GB838312322A GB8312322A GB8312322D0 GB 8312322 D0 GB8312322 D0 GB 8312322D0 GB 838312322 A GB838312322 A GB 838312322A GB 8312322 A GB8312322 A GB 8312322A GB 8312322 D0 GB8312322 D0 GB 8312322D0
- Authority
- GB
- United Kingdom
- Prior art keywords
- integrated circuits
- circuits
- integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/01—Modifications for accelerating switching
- H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
- H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
- H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Logic Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US37654782A | 1982-05-10 | 1982-05-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
GB8312322D0 true GB8312322D0 (en) | 1983-06-08 |
GB2120034A GB2120034A (en) | 1983-11-23 |
Family
ID=23485448
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB08312322A Withdrawn GB2120034A (en) | 1982-05-10 | 1983-05-05 | Clocked logic circuit |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0107712A4 (en) |
GB (1) | GB2120034A (en) |
WO (1) | WO1983004149A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2596595B1 (en) * | 1986-03-28 | 1988-05-13 | Radiotechnique Compelec | DOMINO TYPE MOS LOGIC HOLDER |
DE4141885C1 (en) * | 1991-12-18 | 1992-12-24 | Siemens Ag, 8000 Muenchen, De | |
DE4321315C1 (en) * | 1993-06-26 | 1995-01-05 | Itt Ind Gmbh Deutsche | Clock generating circuit for clock-controlled logic circuits |
JPH11243326A (en) * | 1997-12-24 | 1999-09-07 | Nec Corp | Static clutch circuit and static logic circuit |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3479523A (en) * | 1966-09-26 | 1969-11-18 | Ibm | Integrated nor logic circuit |
GB1171547A (en) * | 1967-10-09 | 1969-11-19 | Telephone Mfg Co Ltd | Improvements in or relating to Four Phase Logic Systems |
US3866186A (en) * | 1972-05-16 | 1975-02-11 | Tokyo Shibaura Electric Co | Logic circuit arrangement employing insulated gate field effect transistors |
US3911289A (en) * | 1972-08-18 | 1975-10-07 | Matsushita Electric Ind Co Ltd | MOS type semiconductor IC device |
CA979080A (en) * | 1972-08-30 | 1975-12-02 | Tokyo Shibaura Electric Co. | Logic circuit arrangement using insulated gate field effect transistors |
US3911428A (en) * | 1973-10-18 | 1975-10-07 | Ibm | Decode circuit |
US4040015A (en) * | 1974-04-16 | 1977-08-02 | Hitachi, Ltd. | Complementary mos logic circuit |
US3982138A (en) * | 1974-10-09 | 1976-09-21 | Rockwell International Corporation | High speed-low cost, clock controlled CMOS logic implementation |
US3959782A (en) * | 1974-12-04 | 1976-05-25 | Semi, Inc. | MOS circuit recovery time |
US4291247A (en) * | 1977-12-14 | 1981-09-22 | Bell Telephone Laboratories, Incorporated | Multistage logic circuit arrangement |
US4345170A (en) * | 1980-08-18 | 1982-08-17 | Bell Telephone Laboratories, Incorporated | Clocked IGFET logic circuit |
-
1983
- 1983-04-21 WO PCT/US1983/000583 patent/WO1983004149A1/en not_active Application Discontinuation
- 1983-04-21 EP EP19830901782 patent/EP0107712A4/en not_active Withdrawn
- 1983-05-05 GB GB08312322A patent/GB2120034A/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
EP0107712A1 (en) | 1984-05-09 |
EP0107712A4 (en) | 1984-09-14 |
GB2120034A (en) | 1983-11-23 |
WO1983004149A1 (en) | 1983-11-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
WAP | Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1) |