JPH0373612A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To decrease an operating time and a precharge time by constituting a 1st stage logic circuit of a high speed precharge type precharge logic circuit, and constituting 2nd and succeeding stage of logic circuits of a high speed operation type precharge logic circuits in a logical arithmetic section. CONSTITUTION:An operating time Teb of a precharge type precharge logic circuit PLB is set slightly longer than an operating time Tea of a precharge type logic circuit PLA because of a discharge time of a parasitic capacitance C2 by a logic block LB is made late. On the other hand, an internal node n1 of the high speed operation type precharge logic circuit PLA being a basic building block for 2nd-4th stage of logic circuits PL2-PL4 of an arithmetic unit ALU is connected directly to an input terminal of an output inverter circuit. On the contrary the operating time Tea goes faster than the operating time Teb of the PLB. Thus, the precharge time Tp is reduced by a difference of the precharge time between the PLB and PLA. Moreover, the operating time Ts as the entire arithmetic unit is reduced.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention relates to a semiconductor integrated circuit device,
For example, the present invention relates to a technique that is particularly effective for use in high-speed logic integrated circuits and the like having an arithmetic and logic operation unit whose basic configuration is a precharged logic circuit.

[Conventional technology]

There is a precharge type logic circuit that performs dynamic logic operations according to a predetermined timing signal.

Further, there is an arithmetic and logic operation unit in the form of a dome, in which a plurality of precharged logic circuits are connected in series, and there is a high-speed logic integrated circuit that includes such an arithmetic and logic operation unit.

The precharge type logic circuit, as represented by the precharge type logic circuit PLA in FIG. 3, is selectively turned on in accordance with the inverted tie main signal φp and charges the internal node n1 and each node of the logic block LB. P-channel MO3FETs (insulated gate field effect transistors) Ql to Q3 and corresponding input data i1 to i4 are set in a predetermined combination to selectively enter a transmission state and discharge the parasitic capacitance C1 of the internal node n1. The internal node Fnl (D potential is determined by a CMOS inverter circuit consisting of a P channel MOsFET Q5 and an N channel MO3FET QI5, and the output signal 0 is selectively set to a high level. .

As a result, the precharge type logic circuit PLA has the following logical operation function for the input data 11 to 14: o-il.i2+i3.i4.

By the way, the precharge type logic circuit PLA shown in FIG.
In this case, the parasitic capacitance C1 coupled to the internal node n1 therefore requires a relatively long time to precharge, resulting in a problem that the cycle time of the arithmetic and logic unit is limited.

To deal with this, for example, a precharge MO is connected between the internal node n1 and the input terminal of the output inverter circuit, as illustrated in the precharge type logic circuit PLB of FIG.
A method has been proposed in which the parasitic capacitance C is divided by providing an N-channel MO3FET Q16 that is turned on complementary to the 5FETs QI to Q3. In the precharge type logic circuit PLB, the divided parasitic capacitances C1 and C2 are charged via separate precharge MO3FETs QI or Q4, so that the time Tpb required for precharging is as shown in FIG. In addition, the precharge time Tpa of the precharge type logic circuit PLA is reduced to approximately half. However, since the MO5FET QI 6 is provided, the discharging of the parasitic capacitance C2 is slowed down, and the operation time Teb is longer than the operation time Tea of the precharge type logic circuit PLA.

Hereinafter, for convenience, the precharge type logic circuit PLA of FIG.
etc. are called high-speed operation precharge type logic circuits, and the fourth
The precharge type logic circuit PLB shown in the figure is referred to as a high-speed precharge type precharge type logic circuit.

A high-speed operation precharge type logic circuit is described in, for example, Japanese Patent Laid-Open No. 62-98827, and a high-speed precharge type precharge type logic circuit is described in, for example, Japanese Patent Laid-Open No. 63-26027. Are listed.

[The invention aims to solve a! Title]

In conventional high-speed logic integrated circuit devices, etc. whose basic configuration is a precharge type logic circuit, the logic operation section such as an arithmetic logic operation unit can only be one of the above-mentioned high-speed operation type or high-speed precharge type precharge type logic circuit. It is composed of For this reason, for example, the four-stage logic circuit PLI~P
When the logic operation section consisting of L4 is composed only of the high-speed operation precharge type logic circuit PLA, the 6th rJ! As exemplified in J, the operation time T of the logic operation unit as a whole
Although s is relatively short, it is not sufficient, and the precharge time Tp also becomes long. On the other hand, the logic operation section is replaced by a high-speed precharge type precharge type logic circuit PL.
In the case of only B, as illustrated in FIG. 7, the precharge time Tp is shortened, but the operation time Ts of the logic operation section as a whole becomes long.

An object of the present invention is to optimize the configuration of a logic operation unit of a high-speed logic integrated circuit device or the like having a precharge type logic circuit as its basic configuration, and to shorten its operating time and precharge time. Another object of the present invention is to increase the speed of a high-speed logic integrated circuit device, etc. including a logic operation section, and to shorten its cycle time.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in the logic operation section of a high-speed logic integrated circuit device, etc., which has a precharge type logic circuit as its basic configuration, the first stage logic circuit is basically a so-called high-speed precharge type precharge type logic circuit that includes means for dividing parasitic capacitance. The logic circuits in the second and subsequent stages are basically constructed as so-called high-speed operation precharge type logic circuits that do not include means for dividing parasitic capacitance.

[For production]

According to the above means, the configuration of the logic operation section is optimized,
It is possible to speed up the operation time of the logic operation section as a whole and shorten its precharge time.

As a result, the operation of a high-speed logic integrated circuit device or the like including a logic operation section can be further accelerated and its cycle time can be shortened.

〔Example〕

FIG. 1 shows a partial circuit block diagram of an embodiment of an arithmetic and logic unit ALU to which the present invention is applied. Further, the second WJ shows a tie diagram of one embodiment of the arithmetic and logic unit ALU of FIG. 1. Furthermore, FIGS. 3 and 4 show a precharged logic circuit P constituting the arithmetic logic unit ALU of FIG.
Basic circuit diagrams of one embodiment of LA and PLB are shown, and the fJs diagram shows the precharge type logic circuit PLA.
and a timing diagram of one embodiment of the PLB are shown.

Based on these figures, the arithmetic logic unit ALU and precharged logic circuits PLA and P of this embodiment will be constructed.
An overview of the configuration and operation of the LB as well as its characteristics will be described.

The arithmetic and logic unit 7) ALU of this embodiment is included in a high-speed logic integrated circuit device such as a microprocessor, although it is not particularly limited. Although each circuit element and the circuit element constituting each block in FIG. 1 are not particularly limited, along with other circuit elements not shown in the high-speed logic integrated circuit device,
It is formed on a single semiconductor substrate such as single crystal silicon. In addition, in Figure g43 and the 4th WJ, the MOSFET with an arrow added to the channel (back gate) part is a P-channel type, and the N-channel MOS without an arrow
It is shown separately from FET.

In FIG. 1, the arithmetic logic operation unit 7)A of this embodiment is shown.
Although not particularly limited, the LU includes four stages of logic circuits PLI to PL4 that are in the form of a paperback. Among these, the first stage logic circuit PLI receives an inverted timing signal φp from a timing control i11 circuit (not shown), although it is not particularly limited.
1 is supplied, and 8-bit input data 11 to 8 are supplied via a data bus (not shown). On the other hand, the logic circuits PL2 to PL4 of the second to fourth stages receive a timing signal φp2 from the timing control circuit via a corresponding Nant gate circuit, although this is not particularly limited.
is supplied, and the previous stage logic circuit, PLl to P
Output signals 011-01 & o31-o36 of L3 are supplied, respectively. The output signal of the fourth stage logic circuit PL4 is the output signal 01-0 of the arithmetic logic unit ALU.
4, and is sent to a data bus (not shown).

In this embodiment, the first stage logic circuit PLI constituting the arithmetic and logic unit 7) ALU includes one or more high-speed precharge type precharge logic circuits WIrPLB(
The logic circuits PL2 to PL4 of the second stage to @fourth stage are configured based on the precharge type logic circuit of gJl.
Each of them is basically configured with one or more high-speed operation type precharged logic circuits PLA (second precharged logic circuits).

The high-speed precharge type precharge type logic circuit PLB, which is the basic configuration of the first stage logic circuit PLI of the arithmetic and logic operation unit) ALU, is not particularly limited, but as illustrated in FIG. P-channel type (first conductivity type) precharge MO5FET QI (first MO
An inverted tying signal φp is supplied to the gate of this MOSFETQI including the MOSFETQI. Here, the power supply voltage of the circuit is not particularly limited, but is set to be a positive power supply voltage such as +5V. Further, the inverted timing signal φp is formed based on the system clock signal, although it is not particularly limited, and is periodically brought to a low level at predetermined intervals.

Between the internal node nl and the ground potential (second power supply voltage) of the circuit, there are provided logic blocks I and B consisting of four N-channel MO3FETs Q11 to Q14 connected in series and parallel, although not particularly limited thereto. These MOSFETs
The gate of is connected to the input terminal 1f of each precharge type logic circuit.
-14, respectively, and between the power supply voltage of the 0 circuit to which the corresponding predetermined input data 1l-i4 is supplied and each internal node of the logic block LB, there is a terminal P that receives the inverted timing signal φp at its gate. Channel type precharge MO3FETs Q2 and Q3 are provided, respectively.

The internal node nl is further coupled to the input terminal of an output inverter circuit consisting of a P-channel MOSFET Q5 and an N-channel MO3FET QI5 via an N-channel type (second conductivity type) MOSFET QI6 (second MOSFET). .

The gate of the MOS FETQ 16 is supplied with the inverted timing signal φp. MOSFETQI6 is
It has a function of dividing the parasitic capacitance coupled to the internal node nl into the parasitic capacitance C1 on the logic block LB side and the parasitic capacitance ff1C2 on the output inverter circuit side.

Between the power supply voltage of the circuit and the input terminal of the output inverter circuit, there is a P-channel precharge MO3FETQ4 whose gate receives the inverted timing signal φp.
(third MOS FET) is provided. The output terminal of the output inverter circuit is coupled to the output terminal O of this precharged logic circuit PLB.

When the inverted tie main signal φp is set to low level, M
OSFETQI 6 is turned off, and four precharge MO3FETs QI to Q4 are turned on all at once. Therefore, the parasitic capacitances C1 and C2 are connected to one of the circuits via the corresponding precharge MOS FETQl or Q4.
1 source voltage, and the logic block LB
Each node of the corresponding precharge MO3FETQ2
and is charged to the power supply voltage of the circuit via Q3. At this time, the output signal of the output inverter circuit, that is, the output signal O of the precharged logic circuit PLB, is the parasitic capacitance C2
is charged to the circuit power supply voltage, so the input data 1
Regardless of numbers 1 to 14, it is set to a low level like the ground potential of a circuit.

Next, when the inverted timing signal φp is set to high level, the precharge MO3FETs QI to Q4 are turned off, and MOSFET QI6 is turned on instead. Therefore, the condition is that either input data if and 12 or i3 and i4 are set to high level at the same time, and either MOSFET QI 1 and C12 or C13 and C14 constituting logic block LB is turned on at the same time. , the parasitic capacitances C1 and C2 are discharged. As a result, the input potential of the output inverter circuit becomes a low level, and its output signal, that is, the output signal 0 of the precharge type logic circuit PLB, becomes a high level. At this time, if the input data 11 to 14 are not in the above-described predetermined combination, the parasitic capacitances C1 and C2 are not discharged, and the output signal 0 of the precharge type logic circuit PLB remains at a low level. As a result, the precharge type logic circuit PLB inputs the input data t1 to i4.
, it has a logical operation function of o-1l-i2+i3·i4.

By the way, in the precharge type logic circuit PLB, the parasitic capacitance coupled to the internal node nl is M03FETQ1.
6 into two parasitic capacitances 1ic1 and C2,
Charged via the corresponding precharge MO3FET QI or Q4, respectively. Therefore, as illustrated in FIG. 5, the precharge time Tpb of the precharge type logic circuit PLB is approximately half of the operating time T e a of the high-speed operation type precharge type logic circuit PLB. It is shortened to . However, the operation time Tab becomes slightly longer than the operation time Tea of the precharge type logic circuit PLa because the MO5FET QI 6 is added and the discharge time of the parasitic capacitance C2 by the logic block LB is delayed.

On the other hand, the second to fourth stages of the arithmetic and logic operation unit (ALU)
The high-speed operation precharge type logic circuit PLA, which is the basic configuration of the stage logic circuits PL2 to PL4, is composed of MO3FETQ for dividing parasitic capacitance, as illustrated in FIG.
I6 and precharge MO3FET Q4, therefore, its internal node n1 is directly coupled to the input terminal of the output inverter circuit, and there is a relatively large capacitance between internal node n1 and the circuit ground potential. The parasitic capacitance C2I is summed. Therefore, the precharge type logic circuit PLA has the same logic operation #R capability as the precharge type logic circuit PLB in FIG. 4, but the precharge time Tpa is as illustrated in FIG. The operation time Tea is longer than the precharge time Tpb of the precharge logic circuit PLB, and the operation time Tea is faster than the operation time Tab of the precharge logic circuit PLB.

For these reasons, in the arithmetic and logic operation unit ALU of this embodiment, as shown in FIG.
In addition to being shortened by the difference in precharge time of A,
The operation time Ts of the arithmetic and logic unit as a whole is also 1
This is reduced by the difference in the total time of the precharge time and operation time of the precharge type logic circuits PLA and PLB for each stage. As a result, a high-speed logic integrated circuit device including an arithmetic and logic operation unit (ALU) becomes faster and its cycle time becomes shorter.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a high-speed logic integrated circuit, etc. that includes an arithmetic and logic operation unit whose basic configuration is a precharged logic circuit. I can do it. That is, (1) In a logic operation section of a high-speed logic integrated circuit device, etc. whose basic configuration is a precharge type logic circuit, the first stage logic circuit is replaced with a so-called high-speed precharge type precharge type logic including means for dividing parasitic capacitance. Constructed based on the circuit,
By configuring the logic circuits in the second and subsequent stages based on so-called high-speed operation precharge type logic circuits that do not include means for dividing parasitic capacitance, it is possible to optimize the configuration of the logic operation section.

(1) According to the above-mentioned item (1), it is possible to speed up the operation time of the logic operation section as a whole and shorten the precharge time.

(3) According to the above (1) and (2), the operation of a high-speed logic integrated circuit device etc. including a logic operation unit is further accelerated,
The effect is that the cycle time can be shortened.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the number of stages of logic circuits constituting the arithmetic and logic unit (ALU) is arbitrary, and the number of bits of input/output data is not limited. Also, in FIGS. 3 and 4, The logic block LB of the precharged logic circuits PLA and PLB can take any form depending on its logic operation function. In FIG. 4, various embodiments may be considered for the method of dividing the parasitic capacitance coupled to the internal node n1.
Various embodiments may be adopted, such as the circuit block configuration of the arithmetic and logic operation unit ALU shown in FIG. 1, and the specific configuration of the precharge type logic circuits PLA and PLB shown in FIGS. 3 and 4.

In the above explanation, the invention made by the present inventor was mainly explained in the case where it was applied to a high-speed logic integrated circuit device including an arithmetic and logic operation unit, which is the background field of application, but the invention is not limited to this. for example,
The present invention can also be applied to other logic operation units of high-speed logic integrated circuit devices and various digital integrated circuits including similar logic operation units. The present invention can be widely applied to domino-type logic operation units and semiconductor integrated circuit devices including such logic operation units.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, in a logic operation section of a high-speed logic integrated circuit device or the like whose basic configuration is a precharge type logic circuit, the first stage logic circuit is replaced with a so-called high-speed precharge type precharge type logic circuit that includes means for dividing parasitic capacitance. By configuring the logic circuits from the second stage onwards as a so-called high-speed operation precharge type logic circuit that does not include means for dividing parasitic capacitance, the operating time of the logic operation section as a whole can be reduced. The precharge time can be shortened while increasing the speed. As a result, it is possible to speed up the operation of a high-speed logic integrated circuit device, etc. including a logic operation section, and shorten its cycle time.

[Brief explanation of drawings]

FIG. 1 is a partial circuit block diagram showing one embodiment of the arithmetic and logic operation unit to which the present invention is applied. FIG. 2 is a timing diagram showing one embodiment of the arithmetic and logic operation unit of FIG. 3 is a basic circuit diagram showing an embodiment of a high-speed operation type precharged logic circuit included in the arithmetic and logic unit shown in FIG. 1; FIG. 5 is a basic circuit diagram showing an example of a high-speed precharge type precharge type logic circuit, and FIG. 5 is a timing diagram showing an example of the precharge type logic circuit of FIGS. 3 and 4. 7 is a timing diagram showing an example of a conventional arithmetic logic operation unit configured with a high-speed precharge type logic circuit. FIG. FIG. 3 is a timing diagram showing an example of a logic operation unit. ALU...Arithmetic logic unit, PLI to PL4.
...Precharge type logic circuit, PLA...High speed operation type precharge type logic circuit, PLB...High speed precharge type precharge type logic circuit, LB...Logic block, Q1 to Q5... P-channel MOSFET, Q
l 1-Ql 6...N channel MO3FET%C
, C1-C2...parasitic capacitance. Figure 3

Claims (1)

[Claims] 1. The first stage logic circuit is configured based on a first precharge type logic circuit that performs a relatively high-speed precharge operation and a relatively low-speed logic operation, and the second stage and subsequent stages A semiconductor integrated circuit, characterized in that the logic circuit comprises a logic operation unit configured based on a second precharge type logic circuit that performs a relatively high-speed logic operation and a relatively low-speed precharge operation. circuit device. 2. The second precharge type logic circuit has a first conductivity type first logic circuit which is provided between the first power supply voltage and a predetermined internal node and is selectively turned on according to a predetermined timing signal. a logic block provided between the MOSFET and the internal node and a second power supply voltage and selectively placed in a transmission state when input data is in a predetermined combination;
an output inverter circuit whose input terminal is coupled to the internal node, the first precharged logic circuit having an input terminal coupled to the internal node in addition to the first MOSFET and the logic block. First MOSFET
a second MOS of a second conductivity type that is turned on in a complementary manner to
an output inverter circuit coupled to the internal node via a FET; and a third inverter circuit of a first conductivity type provided between a first power supply voltage and an input terminal of the output inverter circuit and receiving the timing signal at its gate. A semiconductor integrated circuit device according to claim 1, characterized in that the semiconductor integrated circuit device includes a MOSFET. 3. The semiconductor integrated circuit device is a high-speed logic integrated circuit device, and the logic operation section is an arithmetic and logic operation unit of the high-speed logic integrated circuit device, or 2. The semiconductor integrated circuit device according to item 2.