TWM645518U - Domino circuit with nmos tree - Google Patents

Abstract

This invention proposes a novel architecture of a domino-type circuit with an NMOS tree, which is composed of a control circuit (3) and a plurality of domino-type basic gates with an NMOS tree, wherein each domino-type basic gate with an NMOS tree The gate system includes an NMOS tree (1), a first PMOS transistor (MP1), a first NMOS transistor (MN1), a holding circuit (2) and a clock (clk). The holding circuit (2) updates It includes an inverter (INV) and a second PMOS transistor (MP2), and the control circuit (3) includes a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4). The domino circuit with the NMOS tree is in the evaluation phase (when the clock is at a logic high level), because the base of the first PMOS transistor (MP1) in the off state is connected to a higher potential. The first power supply voltage (Vdd) is the high second power supply voltage (Vdd2). According to the body effect of the transistor (Body effect), the absolute value of the critical voltage of the first PMOS transistor (MP1) increases, so the current The subcritical leakage current through the first PMOS transistor (MP1) is reduced; furthermore, because the logic high of the clock (clk) received by the gate of the first PMOS transistor (MP1) is The potential of the second power supply voltage (Vdd2) can therefore further reduce the sub-critical leakage current. As a result, the domino circuit with an NMOS tree proposed in this invention can effectively reduce power consumption. In addition, this invention provides a domino circuit with an NMOS tree without charge sharing by precharging all internal nodes of the NMOS tree to a logic high potential.

Description

Domino circuit with NMOS tree

This creation is related to a domino circuit with an NMOS (N-channel Metal Oxide Semiconductor, N-channel metal oxide semiconductor) tree, especially one that uses a control circuit and a plurality of NMOS trees. The domino-type basic gate is composed of complementary metal oxide semiconductor (CMOS) logic circuits with charge-sharing-free and low power consumption.

Dynamic circuits are a very important type of circuit in CMOS logic circuits. Compared with static circuits, dynamic circuits generally have the advantages of less area, higher operating speed, or less power. Therefore, It is commonly used in many high-performance circuits, such as high-speed CPU (Central Processing Unit) and DSP (Digital Signal Processor) chips.

The domino-type basic gate with an NMOS tree is a CMOS dynamic circuit. The conventional domino-type basic gate with an NMOS tree is as shown in Figure 1. It consists of an NMOS tree (1), a holding circuit (2), and a PMOS It is composed of a transistor (MP1), an NMOS transistor (MN1) and a clock (clk). The holding circuit (2) includes a PMOS transistor (MP2) and an inverter (INV). The PMOS transistor (INV) The source of the crystal (MP2) is connected to the power supply voltage (Vdd), the drain is connected to a first internal node (N1), and the gate is connected to the output terminal (OUT) of the inverter (INV); the PMOS transistor The source of (MP1) is connected to the supply voltage (Vdd), and the gate is used to To receive the clock (clk), the drain is connected to the first internal node (N1); the source of the NMOS transistor (MN1) is connected to the reference ground, and the gate is used to receive the clock (clk), The drain is connected to a second internal node (N2); the NMOS tree (1) is connected between the first internal node (N1) and the second internal node (N2), and accepts a plurality of logic input signals (IN1, IN2...INn), in order to perform a logical operation on the logical input signals (IN1, IN2...INn), and the result of the logical operation is sent to an output terminal (OUT) through the inverter (INV), In order to provide output and/or as a logical input signal of the domino-type basic gate of the next level with NMOS tree.

The domino-type basic gate with NMOS tree shown in Figure 1 has two working phases. The first working phase is called the pre-discharge phase. As the name implies, it is the domino-type basic gate with NMOS tree. The output terminal (OUT) is pre-discharged to a logic low level (Logic low). At this time, the clock (clk) is a logic low level (Logic low), the PMOS transistor (MP1) is turned on and the NMOS transistor (MN1) is turned off, so the output terminal (OUT) will be discharged to a logic low level through the inverter (INV); the second working phase is called the evaluation phase (Evaluation phase), and at this time the clock (clk) is Logic high, the PMOS transistor (MP1) is turned off and the NMOS transistor (MN1) is turned on, because at this time the NMOS transistor (MN1) and the NMOS tree (1) are connected in series, and the The NMOS transistor (MN1) is turned on again, so the logic value of the output terminal (OUT) will be determined by the logic input signals (IN1, IN2...INn), and the Bollinger function that should be completed originally is completed.

The domino-type basic gate with the NMOS tree shown in Figure 1 does not take into account the leakage current due to the PMOS transistor (MP1) being turned off and operating in the subthreshold region during the evaluation phase. , so there is still room for improvement; furthermore, the domino-type basic gate with the NMOS tree shown in Figure 1 does not precharge all the internal nodes of the NMOS tree (1) to a logic high potential, so it is difficult to solve the charge sharing problem. Still a little inadequate, There is also room for improvement.

In view of this, the main purpose of this invention is to propose a novel architecture of a domino circuit with an NMOS tree, which can have lower power consumption than the previous domino basic gate with an NMOS tree.

The secondary purpose of this creation is to propose a novel architecture of a domino circuit with an NMOS tree, which can provide an NMOS tree with no charge sharing by precharging all internal nodes of the NMOS tree to a logic high level. Domino circuit.

This invention proposes a novel architecture of a domino-type circuit with an NMOS tree, which is composed of a control circuit (3) and a plurality of domino-type basic gates with an NMOS tree, wherein each domino-type basic gate with an NMOS tree The gate system includes an NMOS tree (1), a first PMOS transistor (MP1), a first NMOS transistor (MN1), a holding circuit (2) and a clock (clk). The holding circuit (2) updates It includes an inverter (INV) and a second PMOS transistor (MP2), and the control circuit (3) includes a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4). The domino circuit with the NMOS tree is in the evaluation phase (when the clock is at a logic high level), because the base of the first PMOS transistor (MP1) in the off state is connected to a higher potential. The first power supply voltage (Vdd) is the high second power supply voltage (Vdd2). According to the body effect of the transistor (Body effect), the absolute value of the critical voltage of the first PMOS transistor (MP1) increases, so the current The subcritical leakage current through the first PMOS transistor (MP1) is reduced; furthermore, because the logic high of the clock (clk) received by the gate of the first PMOS transistor (MP1) is The potential of the second power supply voltage (Vdd2) can therefore further reduce the sub-critical leakage current. As a result, the method proposed in this invention The NMOS tree domino circuit can effectively reduce power consumption. In addition, this invention provides a domino circuit with an NMOS tree without charge sharing by precharging all internal nodes of the NMOS tree to a logic high potential.

1: NMOS tree

2: Hold circuit

3:Control circuit

Vdd: first power supply voltage

Vdd2: second power supply voltage

INV: inverter

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

MN1: The first NMOS transistor

N1: first internal node

N2: The second internal node

clk: clock

/clk: inverted clock

IN1…INn: logic input signal

Ni1...Nim: internal node of NMOS tree

Figure 1 shows a conventional domino-type basic gate with an NMOS tree;

Figure 2 shows a domino circuit with an NMOS tree according to a preferred embodiment of the present invention.

Based on the above purpose, this invention proposes a domino circuit with an NMOS tree, as shown in Figure 2. For the convenience of explanation, the circuit shown in Figure 2 only uses a control circuit (3) and an NMOS tree. The tree domino type basic gate is explained as an example.

As shown in Figure 2, the domino-type circuit with an NMOS tree is composed of a control circuit (3) and a domino-type basic gate with an NMOS tree, wherein the domino-type basic gate system with the NMOS tree includes There is an NMOS tree (1), a first PMOS transistor (MP1), a first NMOS transistor (MN1), a holding circuit (2) and a clock (clk), where the logic of the clock (clk) The high potential (Logic high) is the potential of a second power supply voltage (Vdd2), and its logic low potential (Logic low) is the potential of the reference ground; the source of the first PMOS transistor (MP1) is connected to the first power supply voltage (Vdd), the gate is used to receive the clock (clk), and the drain is connected to a first internal node (N1); the source of the first NMOS transistor (MN1) is connected to the reference ground, and the gate The pole is used to receive the clock (clk), and the drain pole is connected to a second internal node (N2); the NMOS tree (1) is connected between the first internal node (N1) and the second internal node. between points (N2), and accepts a plurality of logical input signals (IN1, IN2...INn) in order to perform a logical operation on these logical input signals (IN1, IN2...INn), and the result of the logical operation is inverted The phase detector (INV) is then sent to an output terminal (OUT) for output or as a logical input signal of the next stage domino-type basic gate with an NMOS tree.

Please refer to Figure 2 again. The holding circuit (2) further includes an inverter (INV) and a second PMOS transistor (MP2). The inverter (INV) is connected to the first internal node (N1 ) and the output terminal (OUT), and the drain of the second PMOS transistor (MP2) is connected to the first internal node (N1), the gate is connected to the output terminal (OUT), and the source is connected to a first voltage source (Vdd). The control circuit (3) includes a third PMOS transistor (MP3) and a fourth PMOS transistor (MP4). The source of the third PMOS transistor (MP3) is connected to a first power supply voltage (Vdd). The gate is used to receive the clock (clk), the drain is connected to the base of the first PMOS transistor (MP1), and the source of the fourth PMOS transistor (MP4) is connected to a second power supply voltage (Vdd2), the gate is used to receive the inverted clock pulse (/clk), and the drain is connected to the base of the first PMOS transistor (MP1), where the potential of the second power supply voltage (Vdd2) is high at the potential of the first power supply voltage (Vdd).

The domino circuit with NMOS tree shown in Figure 2 has two working phases. The first working phase is the pre-discharge phase. At this time, the clock (clk) is the logic low potential of the reference ground. (Logic low), the first NMOS transistor (MN1) is turned off and the first PMOS transistor (MP1) is turned on, so the output terminal (OUT) will be discharged to a logic low level through the inverter (INV) ; The second working phase is the evaluation phase (Evaluation phase). At this time, the clock (clk) is the logic high of the second power supply voltage (Vdd2), and the first NMOS transistor (MN1) is turned on and the first PMOS transistor (MP1) is turned off, so the logic value of the output terminal (OUT) will be determined by the logic input signal (IN1, IN2...INn), and complete the Boolean function that should be completed originally.

In addition, when evaluating the phase, since the clock (clk) is the logic high level of the second power supply voltage (Vdd2), and the inverting clock (/clk) is the logic low level of the reference ground, the control circuit The third PMOS transistor (MP3) in (3) is turned off, and the fourth PMOS transistor (MP4) in the control circuit (3) is turned on, so the substrate of the first PMOS transistor (MP1) is connected to the second power supply voltage (Vdd2); and in the pre-discharge phase, because the clock (clk) is the logic low potential of the reference ground at this time, and the inverted clock (/clk) is the second The power supply voltage (Vdd2) is at a logic high level, so the third PMOS transistor (MP3) in the control circuit (3) is turned on, and the fourth PMOS transistor (MP4) in the control circuit (3) is turned on. is turned off, so the base of the first PMOS transistor (MP1) is connected to the first supply voltage (Vdd).

Next, we will describe how this invention reduces power consumption. First, compare the conventional domino-type basic gate with an NMOS tree shown in Figure 1 and the preferred embodiment of this invention shown in Figure 2. From the above analysis, it can be seen that in advance During the discharge phase (when the clock (clk) is at a logic low level), the preferred embodiment of the present invention has the same working principle as the conventional domino-type basic gate with an NMOS tree shown in Figure 1; When the value phase is reached (the clock (clk) is at a logic high potential at this time), the substrate of the first PMOS transistor (MP1) in the preferred embodiment of the present invention is connected to a potential higher than the first power supply voltage (Vdd). The second power supply voltage (Vdd2) is high, and the base of the conventional PMOS transistor (MP1) with the domino-type basic gate of the NMOS tree shown in Figure 1 is connected to the first power supply voltage (Vdd), according to Due to the body effect of the transistor, the absolute value of the critical voltage of the first PMOS transistor (MP1) in the preferred embodiment of the present invention is larger than that of the conventional domino-type basic gate with an NMOS tree shown in Figure 1. The absolute value of the critical voltage of the PMOS transistor (MP1) is large, so the voltage flowing through the first PMOS transistor (MP1) of the preferred embodiment of the present invention The sub-critical leakage current will be less than the sub-critical leakage current flowing through the conventional PMOS transistor (MP1) with the domino-type basic gate of the NMOS tree shown in Figure 1. As a result, the preferred embodiment of the present invention can reduce the sub-critical leakage current. critical leakage current.

Furthermore, because the logic high potential of the clock (clk) received by the gate of the first PMOS transistor (MP1) in the preferred embodiment of the present invention is the potential of the second power supply voltage (Vdd2), and the first The logic high potential of the clock (clk) received by the gate of the PMOS transistor (MP1) of the conventional domino-type basic gate of the NMOS tree shown in the figure is the potential of the first power supply voltage (Vdd), that is In the preferred embodiment of this invention, the gate-source voltage of the first PMOS transistor (MP1) is the voltage of the second power supply voltage (Vdd2) minus the first power supply voltage (Vdd), and its value is a positive number. The gate source voltage of the conventional PMOS transistor (MP1) with a domino-type basic gate of an NMOS tree shown in Figure 1 is 0 volts. According to US Patent No. 6865119 No. 3(A) and 3( Figure B) shows that for PMOS transistors, the sub-critical leakage current when the gate-source voltage is +0.1 volts is about 1% of the sub-critical leakage current when the gate-source voltage is 0 volts, so this invention is better Embodiments may further reduce sub-critical leakage current.

Next, the relationship between the second power supply voltage (Vdd2) and the first power supply voltage (Vdd) is discussed. Since the potential of the second power supply voltage (Vdd2) is higher than the potential of the first power supply voltage (Vdd), but in order to To avoid generating Gate Induced Drain Leakage (GIDL) current, the potential of the second power supply voltage (Vdd2) should be no more than, for example, 1 volt, 0.8 volt or more than the potential of the first power supply voltage (Vdd). 0.6 volt limit.

Finally, discuss how this creation can be designed as a multi-drain MOS transistor (MD-MOS transistor) by precharging all internal nodes of the NMOS tree (1) to a logic high potential. , and precharges all internal nodes (Ni1, Ni2...Nim) of the NMOS tree (1) to a logic high potential through another drain electrode, thereby effectively providing Domino circuit with NMOS tree without charge sharing.

Although the present invention specifically discloses and describes selected preferred embodiments, those familiar with the art will understand that any possible changes in form or details may be made without departing from the spirit and scope of the invention. Therefore, all changes within the relevant technical scope are included in the patentable scope of this creation.

【Creative effect】

This invention proposes a domino circuit with an NMOS tree, which has the following effects: (1) Effectively reduce power consumption: because the base of the first PMOS transistor (MP1) in the off state is connected to a potential higher than the first power supply voltage (Vdd) is the high second power supply voltage (Vdd2), and the logic high potential (Logic high) of the clock pulse (clk) received by the gate of the first PMOS transistor (MP1) is the second power supply voltage (Vdd2) potential, so it can effectively reduce power consumption; (2) No charge sharing problem: the first PMOS transistor (MP1) can be designed as a multi-drain MOS transistor (MD-MOS transistor), and through another drain The pole precharges all internal nodes (Ni1, Ni2...Nim) of the NMOS tree (1) to a logic high potential, thereby effectively providing a domino circuit with an NMOS tree without charge sharing.

1: NMOS tree

2: Hold circuit

3:Control circuit

Vdd: first power supply voltage

Vdd2: second power supply voltage

INV: inverter

MP1: The first PMOS transistor

MP2: The second PMOS transistor

MP3: The third PMOS transistor

MP4: The fourth PMOS transistor

MN1: The first NMOS transistor

N1: first internal node

N2: The second internal node

clk: clock

/clk: inverted clock

IN1…INn: logic input signal

Ni1...Nim: internal node of NMOS tree

Claims (5)

A domino-type circuit with an NMOS tree, which includes: a control circuit (3) and a plurality of domino-type basic gates with an NMOS tree; each domino-type basic gate with an NMOS tree further includes: a first PMOS transistor (MP1), its source is connected to a first power supply voltage (Vdd), the gate is used to receive a clock pulse (clk), and the drain is connected to a first internal node (N1); a first NMOS transistor (MN1), its source is connected to the reference ground, the gate is used to receive the clock (clk), and the drain is connected to a second internal node (N2); an NMOS tree (1), which is connected to the between the first internal node (N1) and the second internal node (N2), and accepts a plurality of logical input signals (IN1, IN2, ^... INn) in order to process the logical input signals (IN1, IN2, ^... INn) performs a logical operation; a holding circuit (2) for effectively keeping the signal at the output terminal (OUT) of the domino circuit with NMOS tree from charge redistribution, coupling noise, and/or leakage current, etc. influence; and the clock (clk) has a logic high potential of the second power supply voltage (Vdd2) and a logic low potential of the reference ground; wherein, the holding circuit (2) further includes: an inverter (INV ), the inverter (INV) is connected between the first internal node (N1) and the output terminal (OUT) of the domino circuit with an NMOS tree; and a second PMOS transistor (MP2), Its drain is connected to the first internal node (N1), its gate is connected to the output end (OUT) of the domino circuit with NMOS tree, and its source is connected to a first power supply voltage (Vdd); and The control circuit (3) further includes: a third PMOS transistor (MP3), the source of the third PMOS transistor (MP3) is connected to the first power supply voltage (Vdd), and the gate is used to receive the clock (clk), and the drain is connected to a substrate of the first PMOS transistor (MP1); and a fourth PMOS transistor (MP4), the source of the fourth PMOS transistor (MP4) is connected to The second power supply voltage (Vdd2), the gate is used to receive an inverted clock pulse (/clk), and the drain is connected to the substrate of the first PMOS transistor (MP1). For example, in the domino circuit with NMOS tree described in item 1 of the patent application, the potential of the second power supply voltage (Vdd2) is higher than the potential of the first power supply voltage (Vdd). For example, in the domino circuit with an NMOS tree described in item 1 of the patent application, the clock (clk) is the logic low potential of the reference ground during a pre-discharge phase. The domino circuit with an NMOS tree as described in item 1 of the patent application, wherein the clock (clk) is the logic high of the second power supply voltage (Vdd2) during an evaluation phase (Evaluation phase). Potential. For example, in the domino circuit with an NMOS tree described in item 1 of the patent application, the first PMOS transistor (MP1) is designed as a multi-drain MOS transistor (MD-MOS transistor), in which the multi-drain middle One of the drains is connected to the first internal node (N1), and the other drain precharges all the internal nodes (Ni1, Ni2,...Nim) of these NMOS trees to a logic high potential, thereby effectively providing a wireless Charge-sharing-free domino circuit with NMOS tree.

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