JPS63153617A - Logic integrated circuit - Google Patents

Abstract

PURPOSE:To shorten a time required for the pre-charge of a bus, by providing a half pre-charge circuit which performs the pre-charge of the bus up to an intermediate potential between the high and the low sides of a power source voltage. CONSTITUTION:The half pre-charge circuit 3 is constituted with an enhance type N-channel MOSFETQp turned ON/OFF by a pre-charge signal (phip). The pre-charging MOSFETQp is set in an ON-state when the control signal (phip) goes to a high level, and a signal line li is boosted up to an intermediate level (Vcc-Vthn) between the power source voltage Vcc and a ground level. In such way, it is possible to shorten the time to arrive at a pre-charge level compared with a pre-charge system which pre-charges the bus up to a Vcc level, and to boost the bus up to the pre-charge level sufficiently even when the pulse width of the pre-charge signal (phip) is narrowed, and to realize the acceleration of the transfer of data by the bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Fields] This invention relates to semiconductor integrated circuit technology and a technology that is particularly effective when applied to a bus precharging method in an LSI. The present invention relates to a technique effective for use in a bus precharging method of a controller LSI consisting of a controller LSI.

[Prior art] Conventional 1 For example, CRT controller H manufactured by Hitachi, Ltd.
The internal bus of an MO3 integrated LSI such as the D63484 is a so-called dynamic bus that precharges in synchronization with an externally supplied clock and draws out the charge on each signal line according to the data transferred to the bus. It consists of a dynamic bidirectional bus.

[Problems to be solved by the invention] LSI having a dynamic internal bus as described above
In order to increase the speed of an LSI by increasing the clock frequency, the time for precharging must also be shortened. However, if the precharge time is short, it becomes difficult to completely charge up each signal line forming the bus to the power supply voltage Vcc. This causes a problem in the receiving circuit, which is designed on the assumption that the bus will be completely charged up to the Vcc level.

Furthermore, with the development of CMO8 technology, there is a tendency for LSIs to become larger and larger, and as the LSI becomes larger, the length of the bus becomes longer and the number of circuit elements connected to the bus also increases.

Therefore, the stray capacitance of the bus and the elements connected to the bus (M
OSFET) gate capacitance increases the parasitic capacitance of the bus, increasing the load on the bus and making high-speed precharging difficult.

In addition, in a conventional dynamic bus that is completely precharged to the power supply voltage vcc, data 110"
Since the (low level) is determined by drawing out the charge, the timing at which the data 1101+ is determined always lags behind the data "1" (high level).

However, the data on the bus can be treated as valid only after the slower data "0" is determined. Therefore, there was a limit to how fast the bus could be increased using the conventional precharging method.

The object of this invention is to provide an LS with a dynamic type bus.
The object of the present invention is to shorten the time required to precharge a bus, and to reduce the time difference between high and low levels of signals on the bus, thereby increasing the speed of the bus.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

That is, a half precharge circuit is provided that precharges the bus to a potential intermediate between the power supply voltage on the high side and the power supply voltage on the low side of the circuit.

[Function] According to the above-described means, the potential difference of the bus that is boosted by precharging and the potential difference that is dropped by discharge is smaller than that in a complete precharging method.
As a result, it is possible to shorten the time required to precharge the bus, reduce the time difference between when the high level and low level of the signals on the bus are determined, and achieve the above objectives of increasing the speed of the bus. .

[Embodiment] FIG. 1 shows an embodiment in which the present invention is applied to the configuration of a bus peripheral circuit in a CMOS-LSI.

In FIG. 1, the symbol Qi indicates an LSI
This shows one of the signal lines that make up the data bus in the
Connected to each signal line 12i are an output side circuit 1 that carries data 110 II or II I 11 thereon, and an input side circuit 2 that receives and receives the data. One output side circuit 1 and one input side circuit 2 are connected to the signal line Qi in the drawing, but in an actual LSI, multiple output side circuits and input side circuits are connected to one signal line. be done.

On the output side circuit, there is a CMOS inverter INV consisting of a P-channel MOSFET Q and an N-channel MOSFET Qz that are turned on and off in a complementary manner according to the data output on the bus, and an output control signal. It is composed of MO5FETQs as a transfer gate which is turned on and off by φ1 and short-circuits the output node n8 of the CMOS inverter INV and the signal line Qi. When MOSFETQ is turned on, the data at that time (l Orr.

11111, the signal line Qi is raised or lowered to a high level or a low level. This gate is a P-channel MO5FE in parallel with an N-channel MO5FET.
The high level may be raised to the Cc level by constructing a transmission in which T is connected.

The input side circuit 2 consists of a clocked inverter operated by the input control signal φ2, and is designed to capture and hold data on the signal line Qi while the input control signal φ2 is at a high level. .

A half precharge circuit 3 is provided to charge up the signal line Qi to a predetermined potential between the power supply voltage Vcc and the ground level before the output side circuit 1 transfers data onto the signal line Qi. It is provided.

In this embodiment, it is connected to each signal line Qi.

A half precharge circuit is configured by an enhancement type N-channel MOSFET Qp that is turned on and off by a precharge signal φp. This precharge required MO5FETQP is controlled by the control signal φp
It is turned on when the signal line 12i is set to a high level such as Vcc, but the drain side voltage Vcc is directly connected to the signal line 12i.
The signal line 121 can only be charged up to a potential lower by the threshold voltage Vthn of the MOSFET QP without transmitting Vcc to the signal line ui.
is maintained between the power supply voltage Vcc and the ground level (VCC-Vthn
) level.

The threshold voltage of the above MOSFET QP is obtained when Qp is obtained by the same process as the N output side circuits constituting other circuits such as the above output side circuit 1 and input side circuit 2.
0.2-1. An appropriate value can be obtained within the range of Ov. In addition, the MOSFE that constitutes the precharge equalization circuit
If it is formed in a separate process from T, for example 2
．． A precharge MOSFET Qp having an arbitrary threshold voltage Vthn such as 5V can be formed.

Furthermore, by connecting a plurality (n) of N-channel MO5FETs in series between the power supply voltage Vcc and the signal line Qi, precharging can be performed to a level lower than Vcc by Vthnxn.

FIG. 2 shows the timing of a bus configured as described above.

According to the half precharge circuit of this embodiment.

When the precharge MO5FERQp is turned on by the signal φp, each signal line 12i of the bus is first set to (Vcc-
Vthn) level. Then, when the MO5FET03 is turned on by the change of the control signal φ to the high level, the signal line Qi remains at the high level or is changed to a low level such as Ov depending on the input data to the inverter INV1. After the level of the signal line Qi is determined, the control signal φ2 changes from low level to high level, so that the input side circuit 2 is operated and data on the signal line Qi is taken in.

In the above case, the inverter INV constituting the output circuit 1
Since l has the ability to drive the bus, the precharge MO5FET QP completely (V c c-
Even if it is not precharged to V th n),
This can be further boosted.

As mentioned above, if the bus is precharged to a potential between Vcc and Ov, it will take longer to reach the precharge level compared to the precharge method that completely precharges the bus due to the Vcc level. Time becomes shorter. Therefore, even if the pulse width of the precharge signal φp is narrowed, the voltage on the bus can be sufficiently increased to the precharge level, and data transfer by the bus can be speeded up.

In addition, if the half precharge method as described above is adopted, the signal line level changes all at once from the <VcC level to ○V as shown by the broken line A in Figure 2 when the data changes from high to low. In comparison, the time from precharge level to low level is determined is shorter. In other words.

The difference between the time when the high level is determined and the time when the low level is determined becomes smaller. As a result, the timing at which data on the signal line is taken into the input side circuit 2 by the control signal φ2 can be made faster, which also increases the speed at which signals are transmitted via the bus. Furthermore, since the amplitude of the signals on the bus is small, power consumption is also reduced.

Moreover, generally in CMO3 circuits, P-channel MOS
When the gate widths of the FET and the N-channel MO5FET are made the same, the gm ratio (gmp/gmn) becomes smaller than 1. By this, P.

In a C0M5 inverter where N is the same size, the logic threshold is smaller than Vcc/2. Therefore, when a signal whose high level is Vcc is input to such a CMOS inverter, the margins on the high side and the low side of the inverter become unbalanced. Therefore, in order to make the margins equal, the P-channel MOSFET must be replaced with the N-channel MOSFET.
It becomes necessary to form it so that it is larger than T. As a result, the area occupied by the input side circuit also increases.On the other hand, according to the above embodiment, when P and N are made the same size, the logic threshold VLT of the CMOS inverter is as shown in FIG. Thus, the potential is approximately midway between the high level (Vcc-Vthn) and the low level (○V) of the bus signal line. Therefore, the margins on the high side and the low side of the input side circuit 2 are equal, which has the advantage that design is easy and the input side circuit can be made compact.

Furthermore, in the above embodiment, the N-channel MO5 with high gm
Since the bus is precharged with FETQP, P channel MO5FE of the same size with lower gm
Precharging can be performed faster than when precharging is performed with T.

Therefore, when trying to make the precharge speed the same, the solicharge circuit can be configured more compactly than when using a P-channel MOSFET.

In the above embodiment, the half precharge circuit is composed of an N-channel MOSFET, but it is not limited to this, and for example, a CMO as shown in FIG.
Consists of 5 circuits, signal φP.

Each transistor Q11 by φp? qtz may be rendered conductive at the same time, and each signal line ui of the bus may be precharged to an intermediate potential determined by the on-resistance ratio at that time.

As explained above, the above embodiment is provided with a half precharge circuit that precharges the bus to a potential midway between the power supply voltage on the high side and the power supply voltage on the low side of the circuit. By reducing the potential difference between 1 and 2 and the potential difference lowered by discharge compared to a complete precharge method, the time required to precharge the bus is shortened, and the time difference between when the high level and low level of the signal on the bus are determined is reduced. This has the effect of making the bus smaller and increasing the speed of the bus.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the output side circuit is composed of a CMOS inverter INV□ having bus drive capability and a data transfer MOSFETQ, but this is replaced with a discharge N-channel MOSFET connected to the signal line Qi. It is also possible.

This invention is based on a control LSI such as a microcomputer or a CRT controller, which has a bus inside it.
It can be used in general MO3 type logic LSI.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in a CMOS-L SI that has an internal bus, it is possible to shorten the time required to precharge the bus and reduce the time difference between when the high level and low level of the signal on the bus are determined, thereby increasing the speed of the bus. You will be able to aim for it.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing one embodiment of the peripheral circuit of the 0MO5-LSI bus to which the present invention is applied, Fig. 2 is its timing chart, and Fig. 3 is a circuit diagram showing another embodiment of the precharge circuit. It is. 1... Output side circuit, 2... Input side circuit, 3...
・Reset means (half precharge circuit), Qi・
...Bus signal line, Qp...N channel/l/MO5FET for precharging, Nv1...CMOS
inverter. Figure 1 Figure 2 Figure 2

Claims (1)

[Scope of Claims] 1. In a logic integrated circuit that has an internal bus and is composed of complementary MOSFETs, each signal line that makes up the bus is connected immediately before data is output from the output side circuit onto the bus. 1. A logic integrated circuit comprising reset means for charging the circuit to a potential intermediate between a high side power supply voltage and a low side power supply voltage of the circuit. 2. The reset means as set forth in claim 1 is characterized in that the reset means is constituted by an N-channel MOSFET connected between each signal line and a high-side power supply voltage terminal of the circuit. Logic integrated circuit. 3. Claims characterized in that the final stage of the output side circuit is constituted by a complementary MOS inverter and a transfer gate connected between the output node of this inverter and the signal line. Logic integrated circuit according to item 1 or 2.