JPH0683503A - Method and device for precharging bus line - Google Patents

Abstract

PURPOSE:To drive a bus line with low power consumption at a digital signal processor provided with the bus line in a precharge system. CONSTITUTION:When an instruction decoder 5 decodes an instruction for using a bus line 5, a precharge permit signal 6 is outputted for permitting the precharge of the bus line 1 and only when the precharge of the bus line 1 is permitted by a precharge permit signal 6, a P channel MOS field effect transistor 9 connects a power source 4 and the bus line 1 and precharges the bus line 1. Thus, unnecessary power consumption is prevented by precharging the electric charge of a discharged component although the bus line is not used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a precharge method and a precharge method for a precharge type bus line.

[0002]

2. Description of the Related Art In recent years, a digital signal processor (hereinafter abbreviated as DSP) has been attracting attention as a processor for incorporating a device into a mobile phone or the like in accordance with the trend of introducing a digital system into the field of mobile communication. In a DSP for a digital mobile phone driven by a battery, it is necessary to perform enormous amount of calculation such as voice coding processing with low power consumption in order to prolong a continuous call time.

In the DSP, a bus line is provided in order to supply the data to be calculated from a plurality of data memories and registers to the arithmetic unit. It is necessary to connect a large number of registers to this bus line, and when the bus has a long distance, this bus line may be realized by a precharge type bus.

An example of a conventional bus line precharging method and precharging device for precharging a precharge type bus line will be described below with reference to the circuit diagram of FIG. 3 and the timing chart of FIG.

In FIG. 3, 401 is a bus line of negative logic. Reference numeral 402 is a first inverter circuit, which is connected to the bus line 401. 403
Is a second inverter circuit, which is connected to the first inverter circuit 402 and outputs a signal to the bus line 401 and has a small drive capacity. 404 is a power source. Reference numeral 415 is a first clock signal, which becomes L level at the timing of precharging the bus line 401. Reference numeral 406 denotes a P-channel MOS field effect transistor (hereinafter abbreviated as P-channel MOSFET), the power source 404 is connected to the source terminal, the first clock signal 405 is input to the gate terminal, and the first clock signal 405 is L. When it is at the level, it turns on and supplies power to the bus line 401 connected to the drain terminal to supply the bus line 4
Precharge 01. Reference numeral 407 is a register that stores data to be calculated. A second clock signal 408 indicates the timing of outputting the value of the register 407 to the bus line 401. Reference numeral 409 is a register output permission signal. A logical product circuit 410 includes a register 407.
Output signal, the second clock signal 408, and the register output enable signal 409 are input. 411 is N channel M
OS field effect transistor (hereinafter N channel MOSFE
(Abbreviated as T), the source terminal is grounded, the gate terminal is connected to the output terminal of the AND circuit 410, the drain terminal is connected to the bus line 401, and when the output signal of the AND circuit 410 is 1, it turns on. Ground the bus line 401 to L
To level. 412 is an arithmetic circuit, and the bus line 4
The logical value of 01 is calculated.

A method of outputting the logical value of the register 407 to the bus line 401 after precharging the bus line 401 in the above-mentioned configuration will be described below.

As shown in FIG. 4, the first clock signal 405 becomes L level once in one machine cycle at the timing of φ1. At this time, the P-channel MOSFET 406
Since the gate terminal of is at L level, P channel MOS
The FET 406 is turned on, the power source 404 connected to the source terminal is connected to the bus line 401 of the drain terminal, and the bus line 401 is precharged to the H level. Next, at the timing of φ2, the first clock signal 4
05 becomes H level, so P-channel MOSFET4
06 is turned off, and the bus line 401 and the power supply 404 are disconnected. At this time, the operation of the first inverter circuit 402 and the second inverter circuit 403 causes the bus line 401
Is kept at H level. Next, when the second clock signal 408 becomes H level within the same timing of φ2, if the register output enable signal 409 is H level as in the machine cycle # 1 shown in FIG. 4, the output of the register 407 becomes H level ( If the logical value is '1'), the output of the AND circuit 410 becomes the H level, so the N-channel MOSFET 4
11 is turned on, the bus line 410 is connected to the ground line and becomes L level, and the logical value “1” is output to the negative logic bus line 401. Register 407 at this time
If the output of L is L level (logical value is “0”), the output of AND circuit 410 becomes L level, so N channel M
The OSFET 411 remains off, and the bus line 41
The 0 level is a state in which the precharged H level (logical value “0”) is held as it is, which means that the logical value “0” is output from the register 407.

As described above, in the above-described conventional bus line precharge method and precharge device, the P-channel MOSFET 406 is turned on at the timing of φ1, the bus line 401 is connected to the power supply 404, and the register 407 at the timing of φ2. Depending on the logical value, N channel MO
By turning on the SFET 411 and grounding the bus line 401, the logical value of the register 407 can be output after the bus line 401 is precharged.

[0009]

However, in the above-described conventional bus line precharge method and precharge device, the bus line 401 is not used when the arithmetic circuit 412 is not used at the time of executing a program control instruction or the like.
Not used. In such a case, as shown in machine cycle # 2 in FIG.
Even when 9 is at the L level, the bus line 401 is always precharged once per machine cycle. The bus line 401 has a very large load capacity because a large number of registers are usually connected and the distance is long. Even when the N-channel MOSFET 411 is not turned on at the timing of φ2 and the bus line 401 is not grounded, a certain amount of electric charge is discharged. Therefore, even if the bus line 401 is not used, the first clock signal 405 becomes H level. By repeating the L level, the P-channel MOSFET 40
6 repeatedly turns on and off to precharge the charges for the discharge. Therefore, there is a problem that unnecessary power is consumed.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an excellent bus line precharge method and precharge device which can drive a bus line with low power consumption. Is.

[0011]

SUMMARY OF THE INVENTION To achieve the above object, the present invention provides a method of precharging a bus line of a precharge type only when the instruction decoder decodes an instruction to use the bus line. The line is precharged, and when the instruction decoder decodes the instruction not to use the bus line, the bus line is not precharged.

In order to achieve the above object, the present invention provides a bus line precharge device with a precharge bus line and an instruction decoder which outputs a permission signal when an instruction using the bus line is decoded. And a precharge circuit that is connected to the enable signal, the clock signal, and a power supply and charges the bus line at a timing indicated by the clock signal when precharge is allowed by the enable signal.

In order to achieve the above object, the present invention further provides a bus line, a first inverter circuit having the bus line as an input, and an output signal of the first inverter circuit as an input. A second inverter circuit for outputting to the memory, an instruction decoder for outputting a permission signal when an instruction using the bus line is decoded, a NAND circuit for inputting the permission signal and a clock signal, and a power source for the source terminal. A P-channel MOS field effect transistor having a gate terminal connected to the output terminal of the NAND circuit and a drain terminal connected to the bus line.

[0014]

Therefore, according to the present invention, when the instruction decoder decodes an instruction using the bus line, it outputs a permit signal for permitting precharging of the bus line, and the precharge circuit outputs the permit signal to the bus line. Since the bus line is precharged only when the precharge is allowed, the electric charge for discharge is not precharged even though the bus line is not used.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a bus line precharge device in one embodiment of the present invention, and FIG. 2 is an operation timing diagram.

In FIG. 1, 1 is a bus line, which is of negative logic. 2 is the first inverter circuit,
It is connected to the bus line 1. Reference numeral 3 is a second inverter circuit, which is connected to the first inverter circuit 2 and outputs a signal to the bus line 1 and has a small drive capability. 4 is a power supply. 5 is an instruction decoder, 6
Is a precharge enable signal, and when the instruction decoder 5 decodes an instruction using the bus line 1, its logical value is "1".
Otherwise, the precharge permission signal 6 having a logical value of "0" is output. Reference numeral 7 is a first clock signal, which becomes L at the timing of precharging the bus line 1. A NAND circuit 8 receives the precharge permission signal 6 and the first clock signal 7 as inputs.
Reference numeral 9 denotes a P-channel MOS field effect transistor (hereinafter abbreviated as P-channel MOSFET), the source terminal of which is connected to the power supply 4, the gate terminal of which is connected to the output terminal of the NAND circuit 8 and the output signal of the NAND circuit 8 is at L level. When it is turned on, power is supplied to the bus line 1 connected to the drain terminal to precharge it. 10 is a ground wire. Reference numeral 11 is a register, which stores data to be calculated. Reference numeral 12 denotes a second clock signal, which indicates the timing of outputting the value of the register 11 to the bus line 1. Reference numeral 13 is a register output enable signal. A logical product circuit 14 receives the output of the register 11, the second clock signal 12, and the register output permission signal 13. 15 is an N-channel MOS field effect transistor (hereinafter referred to as N-channel MOS
It is abbreviated as FET), the source terminal is grounded, the gate terminal is connected to the output terminal of the AND circuit 14, the drain terminal is connected to the bus line 1, and when the output signal of the AND circuit 14 is 1, it turns on. The bus line 1 is grounded to the L level. Reference numeral 16 denotes an arithmetic circuit, which calculates the logical value of the bus line 1.

A method of outputting the register value to the bus line after precharging the bus line in the above configuration will be described below.

As shown in FIG. 2, the first clock signal 7 has an H level at a timing of φ1 once in one machine cycle.
Become a level. The instruction decoder 5 sets the logical value of the precharge permission signal 6 to "1" only when the instruction using the bus line 1 is decoded. In the timing chart of FIG. 2, the machine cycle # 1 is a case where the bus line 1 is used, and the machine cycle # 2 is a case where the bus line 1 is not used. In the machine cycle # 1, the precharge enable signal 6 output from the instruction decoder 5 is at H level, so when the first clock signal 7 goes to H level at the timing of φ1, the gate terminal of the P-channel MOSFET 9 becomes L level. Therefore, the P-channel MOSFET 9 is turned on, the power source 4 connected to the source terminal is connected to the bus line 1 connected to the drain terminal, and the bus line 1 is precharged to H level. Next, at the timing of φ2, the first
Clock signal 7 of H level, P channel M
The OSFET 9 is turned off and the bus line 1 and the power supply 4 are disconnected. At this time, the bus line is kept at the H level by the action of the first inverter circuit 2 and the second inverter circuit 3. Further, when the second clock signal 12 goes to H level within the same timing of φ2, the register output enable signal 13 is at H level, so if the output of the register 11 is at H level (logical value is “1”), Since the output of the AND circuit 14 becomes H level, the N channel MOSFET 15
Is turned on, the bus line 1 is connected to the ground line and becomes L level, and the logical value “1” is output to the bus line 1. At this time, if the output level of the register 11 is L level (logical value is “0”), the output of the AND circuit 14 becomes L level, so the N-channel MOSFET 15 remains off and the level of the bus line 1 is kept. Since the precharged H level (logical value is “0”) is maintained as it is, the logical value “0” is output from the register 11.

In the timing chart of FIG. 2, machine cycle # 2 is when the instruction decoder 5 decodes an instruction that does not use the bus line 1. At this time, since the precharge permission signal 6 output from the instruction decoder 5 is at L level, when the first clock signal 7 becomes H level at the timing of φ1, the gate terminal of the P channel MOSFET 9 becomes H level and P Since the channel MOSFET 9 is turned off, the power source 4 connected to the source terminal is not connected to the bus line 1 connected to the drain terminal, and the bus line 1
Is not precharged.

As described above, according to the above embodiment, when the instruction decoder 5 decodes an instruction using the bus line 1,
The precharge permission signal 6 that permits precharging the bus line 1 is output, and P is set only when the precharge permission signal 6 permits precharging of the bus line 1.
Since the channel MOSFET 9 connects the power supply 4 and the bus line 1 for precharging, there is an effect that unnecessary power consumption for precharging the charges for discharge can be avoided even if the bus line is not used.

[0022]

As is apparent from the above embodiment, the present invention outputs a permission signal for permitting precharging of the bus line when the instruction decoder decodes the instruction using the bus line, and the precharge circuit. Will precharge the bus line only when the pre-charge of the bus line is permitted by the above enable signal, so avoiding unnecessary consumption of power by pre-charging the electric charge for discharge even if the bus line is not used. It has the effect of being able to.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a bus line precharge device according to an embodiment of the present invention.

FIG. 2 is a timing chart showing operation timings as well.

FIG. 3 is a schematic block diagram of a conventional bus line precharge device.

FIG. 4 is a timing chart showing operation timings of the same.

[Explanation of symbols]

1 Bus Line 2 First Inverter Circuit 3 Second Inverter Circuit 4 Power Supply 5 Instruction Decoder 6 Precharge Enable Signal 7 First Clock Signal 8 NAND Circuit 9 P-Channel MOS Field Effect Transistor (P-Channel MOSFET) 10 Ground Line 11 Register 12 Second clock signal 13 Register output enable signal 14 AND circuit 15 N-channel MOS field effect transistor (N-channel MOSFET) 16 Arithmetic circuit

Claims (3)

[Claims] 1. A precharge method of precharging a bus line, wherein the bus line is precharged only when an instruction decoder decodes an instruction using the bus line, and the instruction decoder A method of precharging a bus line, wherein the bus line is not precharged when an instruction not using the line is decoded. 2. A precharge type bus line, an instruction decoder for outputting a permission signal when an instruction using the bus line is decoded, a precharge method connected to the permission signal, a clock signal and a power supply and precharged by the permission signal. A precharge circuit for charging the bus line at a timing indicated by the clock signal when the bus line precharge device is permitted. 3. A bus line, a first inverter circuit that receives the bus line as an input, and a second inverter circuit that receives an output signal of the first inverter circuit and outputs the output signal to the bus line.
Inverter circuit, an instruction decoder that outputs a permission signal when an instruction that uses the bus line is decoded, a NAND circuit that receives the permission signal and a clock signal as input signals, a source terminal connected to a power supply, and a gate terminal The NA
A bus line precharge device comprising: a P-channel MOS field effect transistor connected to an output terminal of an ND circuit and a drain terminal connected to the bus line.