JP4197044B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit including a clock generation circuit, and more particularly to a semiconductor integrated circuit equipped with a PLL (Phase Locked Loop) circuit.

  A computer system such as a microprocessor or a microcontroller is provided with a PLL circuit that functions as a multiplied clock generation circuit in order to realize an external frequency multiplication function in a part of the central processing unit in order to perform high-speed operation. In recent microprocessors, it is required to maintain the clock phase between the external bus and the semiconductor integrated circuit with high accuracy.

  Conventionally, there is a method in which the time until the PLL circuit is stabilized after power-on is counted by a timer, the clock supply from the PLL circuit to the central processing unit is stopped until a certain time, and the multiplication clock supply is started when the timer overflows. is there.

  Now, in the phase comparator in the PLL circuit, it is desirable that the relationship between the phase difference between the two input signals and the output voltage is linear. However, in reality, a minute phase difference cannot be detected, and a phase difference dead zone may exist, or a discontinuity may exist due to too high sensitivity.

  It has already been found that the delay time in the reset circuit has a great influence on the input / output characteristics of the phase comparator. In other words, in order to improve the input / output characteristics of the phase comparator, it is necessary to optimize the delay time in the reset circuit. However, in the phase comparator according to the first prior art, since the reset circuit is composed of one 4-input NAND circuit, the delay time is shorter than the appropriate value, and the input / output characteristics having a dead zone are exhibited ( Patent Document 1).

Various improvements have already been made to optimize the delay time of the reset circuit. According to the second prior art, the output of the reset signal is delayed by narrowing the channel width of the transistors constituting the 4-input NAND circuit (see Patent Document 2). According to the third prior art, a plurality of capacitors are used as means for delaying the output of the reset signal (see Patent Document 3).
US Pat. No. 3,610,954 JP 63-119318 A US Pat. No. 4,378,509

  As described above, in the phase comparator according to the first prior art, since the reset circuit is configured by one 4-input NAND circuit, the delay time is shorter than the appropriate value, and the input / output characteristics having the dead zone are shown. End up. In the case of the second prior art, the yield is inevitably deteriorated due to variations in channel width and the like in recent years when the gate width of the transistor has become less than μm. In the case of the third prior art, the capacitor increases the chip area.

  The charge pump circuit also has a factor of deteriorating input / output characteristics. When a current type charge pump circuit is used, the output voltage of the phase comparator may change even though there is no phase difference between the two signals. That is, although the in-phase clock is input, the phase difference is erroneously detected, and a highly accurate PLL circuit cannot be realized.

  The clock driver is designed to supply a clock synchronized with zero skew to each functional block. However, skew variation occurs depending on each chip due to temperature dependence and process variation.

  In each functional block, a circuit that uses a two-phase clock in synchronization with a clock, such as a dynamic circuit or a memory, is designed so that it can operate stably with a delay in advance so as not to cause racing. Due to process variations, the margin of the two-phase clock is reduced and malfunction occurs.

  In addition, there is a function block that has a function to stop the subsequent operation when processing becomes unnecessary in the middle of a series of operations due to low power consumption. It does not stop and causes malfunction.

  In addition, even if an adjustment circuit for solving these problems is provided, it is a waste of time if the operation of the adjustment circuit is started after the PLL circuit is stabilized.

  An object of the present invention is to enable effective use of the time before the clock generation circuit supplies a system clock signal, particularly the oscillation stabilization wait time of the PLL circuit.

  To achieve the above object, the present invention provides a semiconductor integrated circuit including a clock generation circuit that generates a system clock signal from a reference clock signal, using the reference clock signal before the clock generation circuit supplies the system clock signal. Thus, the specific circuit portion in the semiconductor integrated circuit is adjusted. In particular, in a semiconductor integrated circuit including a PLL circuit, a specific circuit portion is adjusted using a reference clock signal before the PLL circuit oscillates stably.

  Specifically, the reference clock signal is supplied to both the reference clock input unit and the feedback clock input unit of the phase comparator in a state in which the feedback loop of the PLL circuit is cut off, and the phase difference detection dead band in the phase comparator is reduced. The delay of the reset signal in the phase comparator is adjusted so as to decrease.

  In the case of a bandgap reference circuit for supplying a reference voltage to a current-type charge pump circuit in a PLL circuit, a reference clock input unit of a phase comparator in the PLL circuit with a feedback loop of the PLL circuit cut off A reference clock signal is supplied to one of the feedback clock input units and the phase compensation amount of the band gap reference circuit is adjusted so that the band gap reference circuit does not oscillate.

  In the case of the current type charge pump circuit in the PLL circuit, the reference clock is supplied to one of the reference clock input unit and the feedback clock input unit of the phase comparator in the PLL circuit with the feedback loop of the PLL circuit cut off. A signal is supplied to adjust the current drive capability of the current type charge pump circuit.

  In the case of a clock distribution circuit for distributing a system clock signal to a plurality of functional blocks, the skew between a plurality of clock drivers in the clock distribution circuit is adjusted so as to reduce the output clock skew of the clock distribution circuit. .

  In the case of a data holding circuit that operates in synchronization with a system clock signal, such as a memory circuit having a word line and a sense amplifier, or a dynamic circuit having two or more stages connected serially, Perform racing adjustment in internal operation.

  In the case of a functional circuit having a power consumption reduction function, such as a cache circuit, the phase fine adjustment period after the completion of frequency pull-in of the PLL circuit is entered based on the reference clock signal and the feedback clock signal of the PLL circuit. When detected, it is adjusted which part in the functional circuit is stopped according to the frequency of the oscillation clock signal of the PLL circuit.

  According to the present invention, in a semiconductor integrated circuit including a clock generation circuit that generates a system clock signal from a reference clock signal, the semiconductor integrated circuit uses the reference clock signal before the clock generation circuit supplies the system clock signal. Since the specific circuit portion is adjusted, the performance of the semiconductor integrated circuit can be improved while effectively using the preparation period of the clock generation circuit.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a semiconductor integrated circuit according to the present invention will be described in detail with reference to the accompanying drawings.

<Embodiment 1>
FIG. 1 is an example of a semiconductor integrated circuit according to the present invention, and is a block diagram showing a configuration example of a semiconductor integrated circuit incorporating a PLL circuit. In FIG. 1, reference numeral 50 denotes a PLL circuit, which includes a phase comparator 51, a loop filter 52, a voltage controlled oscillator 53, and a programmable frequency divider 54. The phase comparator 51 has Fp and Fr input ports, and is a circuit that compares the phases of signals input to the two ports. A reference clock 100 is input to Fp. The output 51a of the phase comparator 51 is connected to the loop filter 52. The output 52a of the loop filter 52 is connected to the voltage controlled oscillator 53, and the voltage controlled oscillator 53 converts the input voltage into a frequency. The clock signal output from the voltage controlled oscillator 53 is connected to the programmable frequency divider 54. The switch circuit 55 is controlled by the feedback control signal 3. When the feedback control signal 3 is “H”, the Fr of the phase comparator 51 is connected to the programmable frequency divider 54, and the feedback control signal 3 is “L”. At this time, Fr of the phase comparator 51 is connected to the reference clock signal Fp. In this example of the switch circuit 55, 6 and 7 are N-type MOS (Metal Oxide Silicon) transistors, 5 and 8 are P-type MOS transistors, and 5 and 6, and 7 and 8 constitute a transfer gate. Yes. 4 is an inverter. Further, the output 52a of the loop filter 52 is input to the reset control voltage generation circuit 1, and the reset control voltage generation circuit 1 uses a PLL on (ON) signal 56 that enables the operation of the PLL circuit 50 as a reset signal. Synchronous operation is performed using the clock 100, the ripple of the loop filter output 52a is detected, and when the ripple occurs, a voltage lower than the initial voltage is generated and output as the reset control voltage 2, and the phase comparator 51 is input. When no ripple is detected, the reset control voltage 2 generates a voltage higher than the initial voltage.

  FIG. 2 is an example of the phase comparator 51 of the PLL circuit 50, 30 is a digital phase comparator, and 40 is a charge pump circuit. The digital phase comparator 30 includes a reset circuit 31, a first flip-flop 32, a second flip-flop 33, a first three-input NAND circuit 34, a second three-input NAND circuit 35, a first inverter 36, 1 two-input NAND circuit 37, second inverter 38, and second two-input NAND circuit 39. The reference clock signal Fp is input to the first NAND circuit 37 via the first inverter 36, while the reference clock signal Fr is input to the second NAND circuit 39 via the second inverter 38. The output signal of the first NAND circuit 37 is input to the first flip-flop 32 and the first three-input NAND circuit 34, and the output signal of the second NAND circuit 39 is the second flip-flop 33 and the second three-input NAND circuit 34. Input to the input NAND circuit 35. The output signal of the first flip-flop 32 is input to the first three-input NAND circuit 34, and the output signal of the second flip-flop 33 is input to the second three-input NAND circuit 35. The reset circuit 31 includes a four-input NAND circuit 31a that receives the output signals of the first flip-flop 32 and the second flip-flop 33 and the output signals of the first NAND circuit 37 and the second NAND circuit 39 as inputs. The output signal is connected to the source of the transfer gate 31b, the drain is input as a reset signal to the first flip-flop 32 and the second flip-flop 33, and the first three-input NAND circuit 34 and the second This is input to the 3-input NAND circuit 35. The gate of the N-type MOS transistor of the transfer gate 31b is connected to the reset control voltage 2 in FIG. The gate of the P-type MOS transistor of the transfer gate 31b is grounded. If the potential of the reset control voltage 2 becomes higher, the output of the transfer gate 31b changes more quickly, and if the potential of the reset control voltage 2 becomes lower, the output of the transfer gate 31b changes more slowly.

  The first three-input NAND circuit 34 outputs the first phase difference detection signal Pu that is normally “H” and is “L” while the phase of the reference clock signal Fp is ahead of the reference clock signal Fr. Is done. The second three-input NAND circuit 35 outputs a second phase difference detection signal Pd that is normally “H” and is “L” while the phase of the reference clock signal Fp is delayed from the reference clock signal Fr. Is done. The charge pump circuit 40 includes a P-type MOS transistor 41, an N-type MOS transistor 42, and an inverter 43. The source of the P-type MOS transistor 41 is connected to the power supply, and the drain is connected to the drain of the N-type MOS transistor 42. The source of the N-type MOS transistor 42 is grounded. The first phase difference detection signal Pu output from the first three-input NAND circuit 34 is input to the gate of the P-type MOS transistor 41, while the second three-input NAND is input to the gate of the N-type MOS transistor 42. The second phase difference detection signal Pd output from the circuit 35 is inverted by the inverter 43 and input. The drain of the P-type MOS transistor 41 (the drain of the N-type MOS transistor 42) is connected to the output terminal 51a.

  When the first phase difference detection signal Pu is “L”, the P-type MOS transistor 41 becomes conductive, so that the drain potential of the P-type MOS transistor 41 (potential of the output 51a) rises. Further, when the second phase difference detection signal Pd is “L”, the output signal of the inverter 43 becomes “H” and the N-type MOS transistor 42 becomes conductive, so that the potential of the drain of the N-type MOS transistor 42 (output 51a). The potential) decreases. That is, the potential of the output 51a rises when the phase of the reference clock signal Fp is ahead of the reference clock signal Fr, and falls when it is behind.

  An example of the reset control voltage generation circuit 1 is shown in FIG. The reset control voltage generation circuit 1 includes a ripple detection circuit 210 that detects a ripple of the loop filter output 52a, an addition counter 230 that is added when a ripple is detected by the ripple detection circuit 210, and a ripple detection circuit. When the ripple is not detected in 210, the addition counter 240 to be added and the state in which the ripple is not detected within the three clock cycles of the reference clock 100 are the first and third, and only the second ripple is detected. When the feedback control signal 3 is set to “H” and the ripple removal completion circuit 220 for turning off the clocks of the ripple detection circuit 210 and the addition counters 230 and 240 and the addition counter 230 are added, the reset control voltage 2 is reduced, and if the addition counter 240 is added, the reset control voltage 2 is It consists gel reset control voltage output circuit 250..

  The ripple detection circuit 210 includes P-type MOS transistors 211, 212, and 213, an N-type MOS transistor 214, and a latch circuit 219 that holds data while the clock 218 is “L”. It operates as a dynamic circuit with the clock 229 generated by the above. The potential of the voltage 216 is generated by the P-type MOS transistors 211 and 212 at a desired voltage value. When a voltage higher than the potential of the voltage 216 by the threshold value of the N-type MOS transistor 214 is generated from the loop filter 52, the output signal 215 of the ripple detection circuit 210 changes from “H” to “L”. When no ripple is detected, the output signal 215 remains “H”.

  The addition counters 230 and 240 include EXOR circuits (exclusive OR circuits: circuits that output “H” when inputs do not match) 232, 236, 242, and 245, AND circuits 233, 237, 241, and 244, And half flip-flops 234, 235, 243, and 246 with reset. Reference numeral 259 in FIG. 3 represents a 1-bit addition register composed of the lower HAs 232 and 233 and the flip-flop 234 with reset, and receives the output 215 of the ripple detection circuit 210 via the inverter 231. The clock of the flip-flops 234, 235, 243, and 246 is inputted with the clock 218 generated from the ripple removal completion circuit 220, and the reset is inputted with the PLLON signal 56.

  The ripple removal completion circuit 220 includes flip-flops 221 and 222 with reset, EXOR circuits 223 and 227, a 3-input AND circuit 224, an inverter 226, an AND circuit 225, and a buffer 228. The input is the output signal 215 of the ripple detection circuit 210, and the data input of the flip-flop 222 is the Q output of 221. The outputs of the flip-flops 221 and 222 are input to the EXOR circuit 223, and the output of the flip-flop 221 and the output signal 215 of the ripple detection circuit 210 are input to the EXOR circuit 227. The outputs of the EXOR circuits 223 and 227 and the output signal 215 of the ripple detection circuit 210 are input to the 3-input AND circuit 224, and the output of the 3-input AND circuit 224 is input to the inverter 226 and connected to the feedback control signal 3 The The output of the inverter 226 and the reference clock 100 are input to the AND circuit 225, and the output of the AND circuit 225 is used for the clock 229 and connected to the buffer 228. The output of buffer 228 is used for clock 218. The clock of the flip-flops 221 and 222 uses the clock 218, and the reset uses the PLLON signal 56.

  The reset control voltage output circuit 250 includes a parallel connection of P-type MOS transistors 256, 255, and 254 and a parallel connection of N-type MOS transistors 251, 252, and 253. The gate lengths of the P-type MOS transistors 256, 255, 254 and the N-type MOS transistors 251, 252, 253 are 4 times, 2 times, 1 time, and the 256 gates are connected to the output 238 of the flip-flop 234. The gate of 255 is connected to the output 239 of the flip-flop 235, the gate of 251 is connected to the output signal 249 obtained by inverting the output of the flip-flop 243 by the inverter 247, and the gate of 252 is connected to the flip-flop 246. Is output to an output signal 257 that is inverted by an inverter 248.

  FIG. 4 is a timing chart of each signal in FIG. 1, FIG. 2, and FIG. In FIG. 4, the horizontal axis represents time, and the vertical axis represents the feedback control signal 3, the two input ports Fp and Fr of the phase comparator 51, the output 52 a of the loop filter 52, the ripple detection circuit output 215, and the clock (clockb) 218. 2-bit in-register state 221, 222, internal state of flip-flops 234, 235 constituting addition counter 230, internal state of flip-flops 243, 246 constituting addition counter 240, expressed in binary notation, reset The control voltage is 2.

  The operation of FIGS. 1, 2, and 3 constituting the first embodiment will be described with reference to FIG. In the PLL circuit 50, before the power is turned on, the PLLON signal 56 is "L", and the values in the flip-flops 221, 222, 234, 235, 243, and 246 in the reset control voltage generation circuit 1 are "L". After the power is turned on, when the PLLON signal 56 becomes “H” and the feedback control signal 3 is “L” at first, the feedback loop is cut, and the Fr of the phase comparator 51 has the same phase and the same period as Fp. A reference clock 100 is input. Originally, when an in-phase clock is input to the phase comparator 51, it is ideal that no ripple occurs in the loop filter output 52a. However, in this example, a case is considered in which the reset delay time of the phase comparator 51 is earlier than the desired time due to process variations and the like. In the first period of the reference clock 100, a ripple occurs in the loop filter output 52a. Then, the output signal 215 of the ripple detection circuit 210 becomes “L”, “H” is input to the lower order HA of the addition counter 230, and the internal state of the flip-flops 234 and 235 becomes 01. As a result, the gate of the P-type MOS transistor 256 of the reset control voltage output circuit 250 becomes “H”, and the P-type MOS transistor 256 is cut off. Since the P-type MOS transistors 256, 255, and 254 are connected in parallel, the on-resistance is increased and the potential of the reset control voltage 2 is decreased. This is transmitted to the gate electrode of the transfer gate 31b of FIG. 2, and the delay increases. As a result, in the second period of the reference clock 100, the reset output of the digital phase comparator 30 has a large delay. In the second period, the output of the loop filter 52 is still rippled, and the reset control voltage output circuit 250 further lowers the potential of the reset control voltage 2. Further, the reset output of the digital phase comparator 30 has a large delay, and the ripple is eliminated in the output of the loop filter 52 in the third period. At the time when the ripple disappears, “H” is input to the addition register 240 of the reset control voltage generation circuit 1. Then, the reset control voltage generation circuit 1 increases the potential of the reset control voltage 2. In the fourth period, the reset output of the digital phase comparator 30 has a delay smaller than that in the third period, and ripples are generated again. The reset output of the digital phase comparator 30 has a large delay, and the ripple is eliminated in the output of the loop filter 52 in the fifth period. When the ripple disappears, the output of the AND circuit 224 of the ripple removal completion circuit 220 of the reset control voltage generation circuit 1, that is, the feedback control signal 3 becomes “H”. The internal clock 229 stops and holds the potential of the reset control voltage 2. In the sixth period, the PLL circuit 50 connects the feedback loop by the switch circuit 55 and operates until the normal PLL oscillation stable state. This makes it possible to realize highly accurate phase comparison with respect to the initial variation and temperature fluctuation of the device of the digital phase comparator 30.

  In FIG. 2, Pu and Pd may be output at the same time due to variations in switching voltages of the 3-input NAND circuits 34 and 35. However, a buffer is provided between the transfer gate 31b and the 3-input NAND circuits 34 and 35. It is also possible to relax by making the output waveform steep. Preferably, the delay time between the 3-input NAND circuit 34 and the P-type MOS transistor 41 and the delay time between the 3-input NAND circuit 35 and the N-type MOS transistor 42 are adjusted by adjusting the transistor size or adding a buffer. It is better to make it uniform. In the transfer gate 31b in FIG. 2, not only the gate voltage of the N-type MOS transistor but also the gate voltage of the P-type MOS transistor may be controlled.

  The digital phase comparator 30 shown in FIG. 2 is an example, and any type of phase comparator configured by a sequential logic having a reset function can make the reset delay variable by the same method.

<Embodiment 2>
FIG. 5 shows an example of a semiconductor integrated circuit according to the present invention. In the semiconductor integrated circuit of FIG. 5, the output of the charge pump circuit of the PLL circuit 500 is further connected to the ripple detection circuit 900 to the PLL circuit 500 and the reference voltage circuit 600, and ripples are detected from the output of the ripple detection circuit 900. Are connected to a 2-bit addition counter 910. When the control input e is “H”, the output bus of the addition counter 910 is connected to the capacitors 920 and 921 to the En 626, respectively. It is connected to the control signal of the switch circuit 930 to be cut off. These capacitors 920 and 921 are set to 1/4, 1/2 of the value C of the capacitor 630 in the reference voltage circuit 600. The ripple detection circuit 900 is the circuit 210 described in the first embodiment, and the addition counter 910 is the same.

  FIG. 6 is an example of a PLL circuit 500 according to the present invention. In FIG. 6, reference numeral 500 denotes a PLL circuit, which includes a phase comparator 51, a loop filter 52, a voltage controlled oscillator 53, and a programmable frequency divider 54. The output of the phase comparator 51 is connected to the loop filter 52, the output 52a of the loop filter 52 is connected to the voltage controlled oscillator 53, and the voltage controlled oscillator 53 converts the input voltage into a frequency. The clock signal output from the voltage controlled oscillator 53 is connected to the programmable frequency divider 54. The switch circuit 55 is controlled by the feedback control signal 3. When the feedback control signal 3 is “H”, the Fr of the phase comparator 51 is connected to the programmable frequency divider 54, and when the feedback control signal 3 is “L”. Fr of the phase comparator 51 is connected to the switching circuit 510. In response to the input switching control signal 540, the switching circuit 510 inputs the reference clock 100 to Fr of the phase comparator 51 only when the input switching control signal 540 is “H”, and when the input switching control signal 540 is “L”, Fix Fr to ground. In this example of the switching circuit 510, 515 and 518 are N-type MOS transistors, 516 and 517 are P-type MOS transistors, and 515 and 516, and 517 and 518 constitute a transfer gate. Reference numeral 514 denotes an inverter. On the other hand, the reference clock Fp of the phase comparator 51 is connected to the switching circuit 501. In response to the input switching control signal 540, the switching circuit 501 inputs the reference clock 100 to the Fp of the phase comparator 51 only when the input switching control signal 540 is “L”, and when the input switching control signal 540 is “H”, Fix Fp to ground. In this example of the switching circuit 501, 505 and 508 are N-type MOS transistors, 506 and 507 are P-type MOS transistors, and 505 and 506, and 507 and 508 constitute a transfer gate. Reference numeral 504 denotes an inverter. In FIG. 6, the phase comparator 51 is separated into a digital phase comparator 30 and a current type charge pump circuit 520. The current-type charge pump circuit 520 includes P-type MOS transistors 521 and 523, N-type MOS transistors 524 and 522, and an inverter 525. The P-type MOS transistor 521 has a source connected to a power supply and a gate connected to the reference voltage circuit 600. The drain is connected to the source of the P-type MOS transistor 523. The gate of the P-type MOS transistor 523 is connected to Pu of the digital phase comparator 30. The N-type MOS transistor 522 has a source connected to the ground, a gate connected to the output terminal En626 of the reference voltage circuit 600, and a drain connected to the source of the N-type MOS transistor 524. The gate of the N-type MOS transistor 524 is connected to Pd of the digital phase comparator 30 via the inverter 525. The drains of the P-type MOS transistor 523 and the N-type MOS transistor 524 are connected to each other, and are connected to the charge pump output (current monitor) 526 and the loop filter 52. The current-type charge pump circuit 520 obtains a desired voltage for En626 and Ep651 from the reference voltage circuit 600, thereby charging the loop filter 52 with current when Pu is “L” and when Pd is “L”. , Has the function of discharging current.

  FIG. 7 shows the reference voltage circuit 600 used in FIG. The reference voltage circuit 600 includes a band gap generation circuit 610, an operational amplifier 620, a P-type MOS transistor 650, an N-type MOS transistor 640, and a capacitor 630. The band gap generation circuit 610 includes a P-type MOS transistor 619, resistance elements 612, 613, and 614, and diodes 615 and 616, and the resistance elements 612 and 613 have the same value of resistance, and have a value of R ohm here. Resistance element 614 has a value of r ohms. The diode 616 includes n diodes connected in parallel, and each diode is equivalent to the diode 615.

The operational amplifier 620 includes P-type MOS transistors 625, 624, and 623 and N-type MOS transistors 621 and 622. The reference voltage circuit 600 is a negative feedback circuit. The operational amplifier 620 compares the voltages at the nodes 617 and 618 and adjusts the current flowing through the P-type MOS transistor 619 so as to have the same potential. That is, if the voltage of 617 is V2, the current of 613 is I2, the voltage of 618 is V1, and the current of 612 is I1,
V1 = V2 (1)
I1 · R = I2 · R (2)
I1 = I2 (3)
I1 = Is · (exp (V1 / (n · Vt)) − 1) (4)
Holds. here,
Vt = kT / q (5)
I2 = 12 · Is · (exp (Vd / (n · Vt)) − 1) (6)
Where q is the charge amount of electrons, k is the Boltzmann constant, and T is the absolute temperature. If the voltage at the contact point between the resistor 614 and the diode 616 is Vd,
V1 = r · I2 + Vd (7)
n · Vt · log (I1 / Is + 1) = R · I1 + n · Vt · log (I1 / (12 · Is) +1) (8)
It is. Therefore,
From I1 / Is >> 1, n · Vt · (log (I1 / Is) −log (I1 / (12 · Is))) = R · I1 (9)
(N · Vt · log12) / R = I1 (10)
Holds. That is, I1 is proportional to kT / q and inversely proportional to the temperature characteristic of R. The capacitor 630 is provided for phase compensation of the negative feedback of the reference voltage circuit 600.

  FIG. 8 shows a configuration example of the switch circuit 930 in FIG.

  FIG. 9 is a timing chart for explaining the operation of FIGS. 6 and 7, where the horizontal axis is time, and the vertical axis is feedback control signal 3, input switching signal 540, and Fp and Fr of digital phase comparator 30. , The voltage value of each charge pump output 526 and the current value of the charge pump output 526. Before the PLL circuit 500 operates, the feedback control signal 3 is set to “L”, and the feedback loop is interrupted. By setting the input switching control signal 540 to “L”, the reference clock 100 is input to Fp of the digital phase comparator 30 and Fr is fixed to “L”. Up to three clock cycles, the output voltage of the current-type charge pump circuit 520 rises and always supplies current. By monitoring this current or voltage, it is possible to detect whether the phase comparator 51 and the reference voltage circuit 600 are operating normally.

  Specifically, when the capacity 630 of the reference voltage circuit 600 is manufactured to be small rather than an appropriate capacity, the feedback system loop of the reference voltage circuit 600 has no phase margin, and the reference voltage circuit 600 oscillates. , En626 and Ep651 always have amplitudes. At this time, the current type charge pump circuit 520 supplies a current corresponding to the voltage amplitude. In this case, when the voltage of the charge pump output 526 is monitored, ripples are generated. The ripple voltage is detected by the ripple detection circuit 900, counted by the addition counter 910, and the reference voltage circuit 600 operates stably by increasing the capacitance so that no ripple is generated. In the above example, it is assumed that the capacitor 630 is not an appropriate value. However, when the reference voltage circuit 600 oscillates, any circuit can be realized from oscillation to stable operation.

<Embodiment 3>
FIG. 10 shows an example of a semiconductor integrated circuit according to the present invention. The PLL circuit 800 of FIG. 10 is almost the same as that of FIG. 6, but only the current type charge pump circuit 801 is different. The current type charge pump circuit 801 in FIG. 10 is substantially the same as the current type charge pump circuit 520 in FIG. 6, but the drains of the P type MOS transistors 806 and 805 are connected to the connection point 804 of the P type MOS transistors 807 and 802. Has been. Each of the P-type MOS transistors 806 and 805 has a gate length twice or four times that of the P-type MOS transistor 807, and each gate has a bit signal 808 and 809 of the 2-bit register circuit output bus 840, respectively. When it is “H”, it is connected to Ep651, and when it is “L”, it is connected to a switch circuit 820 that is connected to a power source. The drains of the N-type MOS transistors 813 and 814 are connected to a connection point 810 between the N-type MOS transistors 803 and 812. Each of the N-type MOS transistors 813 and 814 has a gate length twice or four times that of the N-type MOS transistor 812, and each gate has a bit signal 815 or 816 of the 2-bit register circuit output bus 850, respectively. When it is “H”, it is connected to En626, and when it is “L”, it is connected to a switch circuit 830 that is connected to the ground. Each bit of the register circuit output buses 840 and 850 is generated from the charge pump output 811 by the voltage differentiation circuit 860, operational amplifiers 861 and 863, and addition counters 862 and 864. Vref1 is an upper limit voltage, and Vref2 is a lower limit voltage. However, each bit of the register circuit output buses 840 and 850 may be generated from the charge pump output 811 by a tester provided outside the semiconductor integrated circuit.

  11 shows a configuration example of the switch circuit 820 in FIG. 10, and FIG. 12 shows a configuration example of the switch circuit 830 in FIG.

  FIG. 13 is a timing chart for explaining the operation of FIG. The horizontal axis represents time, and the vertical axis represents feedback control signal 3, input switching signal 540, digital phase comparator 30 Fp and Fr, charge pump output 811 voltage values, and charge pump output 811 current values. is there. In FIG. 13, a case is considered where the characteristics of the P-type MOS transistor 807, which is the current source of the current-type charge pump circuit, deteriorates. Before the PLL circuit operates, the feedback control signal 3 is set to “L” to shut off the feedback loop. By setting the input switching control signal 540 to “L”, the reference clock 100 is input to Fp of the digital phase comparator 30 and Fr is fixed to “L”. Up to three clock cycles, the voltage 811 of the current-type charge pump circuit 801 rises and always supplies current. However, in the first cycle, the current value of the current-type charge pump circuit 801 is smaller than the appropriate current value. Therefore, by shifting the register output 840 and setting 00 to 01, the current value of the current type charge pump circuit 801 becomes an appropriate value in the second period. In the fourth period, the input switching control signal 540 is set to “H”, so that the reference clock 100 is input to Fr of the digital phase comparator 30 and Fp is fixed to “L”. The voltage 811 of the current type charge pump circuit 801 decreases, and the current is always discharged. Since the current value is already appropriate in the fourth period, the register output 850 maintains 00 as it is. In this way, by monitoring the charge pump current and adjusting the current source of the charge pump circuit by the addition counters 862 and 864, an appropriate current value can be obtained, and subtle current variations such as process variations can be reduced. It is possible. In this example, only the P-type MOS transistor has been described. However, the same method may be used for the deterioration of the N-type MOS transistor, that is, the discharge.

<Embodiment 4>
FIG. 14 shows an example of a semiconductor integrated circuit according to the present invention. Reference numeral 400 denotes a semiconductor integrated circuit according to the present invention. Reference numeral 480 denotes a clock distribution circuit, which is connected to a switch circuit 420 that switches between the reference clock 100 input to the PLL circuit 50 by the bypass control signal 473 and the clock multiplied by the PLL circuit 50. The clock distribution circuit 480 distributes the clock to the functional blocks A, B, and C through the clock lines 430, 431, and 432. The drivers 485a and 485b of the clock lines 431 and 432 have a function of increasing / decreasing the strength of the drivers by the output buses 441, 442, 443, and 444 of the control register circuit 490, and the clock lines 430, 431, and 432 of the clock lines 431 and 432, respectively. Is connected to a phase comparator 410 that detects a rising edge, and one phase comparator 460 detects the phase difference between the clock lines 430 and 431 and sends an up signal 461 and a down signal to one control register circuit 440. A signal 462 is provided. The other phase comparator 470 detects the phase difference between the clock lines 431 and 432 and supplies an up signal 471 and a down signal 472 to the other control register circuit 450. Reference numeral 463 denotes a comparison completion signal given from one control register circuit 440 to the other control register circuit 450.

  FIG. 15 shows an example of the phase comparator 410, which includes input ports Fp and Fr, inverters 411 and 412, 2-input NAND circuits 413, 414, 415 and 416, and output ports Up and Dn. A reference clock is input from Fp and input to the inverter 411 and the NAND circuit 413. The NAND circuit 413 also receives the output of the inverter 411. The comparison target clock is input from Fr and input to the inverter 412 and the NAND circuit 414. The NAND circuit 414 also receives the output of the inverter 412. The 2-input NAND circuits 415 and 416 are R-S latch circuits. When the falling edges of the outputs of the NAND circuits 413 and 414 are detected and the rising edge of Fr is delayed from the rising edge of Fp, The Up output becomes “H” corresponding to the phase difference delay. When the rising edge of Fr is advanced from the rising edge of Fp, the Dn output becomes “L” by the phase difference delay.

  FIG. 16 shows an example of the switch circuit 420. The control signal port e, the two input ports i1 and i2, the output port o, the inverter 424, the P-type MOS transistors 425 and 428, and the N-type MOS transistor 426 are shown. When the e input port is “H”, i2 is output to o, and when it is “L”, i1 is output to o.

  FIG. 17 is an example of the control register circuit 490. The control register circuit 490 includes a comparison completion detection circuit 300, addition registers 493, 494, input ports R, CK, Up, Dn, and output ports Eo, Uo, Do. The reset signal 492 of the input port R is connected to the comparison completion detection circuit 300 and the input port R of the addition registers 493 and 494, the input port CK is input to the comparison completion detection circuit 300, and the input port Up is a dynamic circuit. Through 499, the signal is input to in of the addition register 493 and the input port Din of the comparison completion detection circuit 300. The input port Dn is connected to the in register of the addition register 494 and the input port Din2 of the comparison completion detection circuit 300 via the inverter 487 and the dynamic circuit 488. In the dynamic circuit 488, 485 is an N-type MOS transistor and 486 is a P-type MOS transistor. The output port Eo is connected to out1 of the comparison completion detection circuit 300, the output port Uo is connected to the output ports O1 and O2 of the addition register 493, and the output port Do is connected to the output ports O1 and O2 of the addition register 494. Has been. The addition registers 493 and 494 are configured by serially connecting a 1-bit addition register 496 including an HA and a flip-flop with reset, and the 1-bit addition register 496 includes input ports in, CK, and R. And output ports O2 and O1. A clock 491 is input to CK, and a reset signal 492 is input to R. The output port O1 is an output of the flip-flop, and O2 is a carry signal.

  The comparison completion detection circuit 300 is a circuit similar to the ripple removal completion circuit 220 shown in the first embodiment, and an example is shown in FIG. 18 includes flip-flops 303, 304, 305, 306 with reset, EXOR circuits 312, 313, 4-input AND circuit 311, AND circuits 314, 318, OR circuit 315, inverter 317, and the like. When the state of the Up signal and the Dn signal, which are the input signals of the control register circuit 490, does not change within two cycles of the reference clock, or when the Up signal and the Dn signal change alternately within three cycles, the comparison completion signal ( Eo) is output from out1, clocks (clocka, clockb) 489 and 491 used inside the control register circuit 490 are stopped, and the contents of the respective addition registers 493 and 494 are held.

  FIG. 19 is a timing chart for explaining FIGS. 14, 15, and 17. The horizontal axis represents time, the vertical axis represents the voltage value of each signal, the bypass control signal 473, the reference clock 100, and the function. Supply clock signal line 430 to block A, supply clock signal line 431 to function block B, supply clock signal line 432 to function block C, output ports Up and Dn of phase comparator 460, output port of phase comparator 470 Up and Dn are signal lines of the output bus of the control register circuit 440 and the output bus of the control register circuit 450. In this example, the rising edge of the supply clock signal line 431 to the function block B is later than the rising edge of the supply clock signal line 430 of the function block A, and the rising edge of the supply clock signal line 432 to the function block C is further increased. The example is later than the rising edge of the supply clock signal line 431 of the functional block B. Initially, when the PLL circuit starts stable operation, the PLLON signal 56 changes from “L” to “H”, and the reset signals of the control register circuits 440 and 450 are released. The bypass control signal 473 is “L”, and the PLL circuit 50 internally performs feedback loop control to start preparation for stable operation.

  The reference clock 100 is supplied to the clock distribution circuit 480, and the phase comparator 460 detects the phase difference between the clocks of the clock signal lines 430 and 431. In the first period, since the rising edge of the clock 431 is later than 430, the Up output of the phase comparator 460 becomes “H”. As a result, the first bit Uo [0] of the addition register 493 of the control register circuit 440 becomes “H”, and the driver 485a of the clock line 431 is strengthened. In the second period, the phase difference between the clock lines 430 and 431 disappears, the Up output of the phase comparator 460 remains at “L”, the Dn output remains at “H”, and the clock is similarly output in the third period. There is no phase difference between the lines 430 and 431, and clock distribution with no phase difference is possible. Then, the control register circuit 440 outputs a comparison completion signal 463, and the reset of the control register circuit 450 is released. Next, the phase comparator 470 starts to compare the phase difference between the clock lines 432 and 431. In the fourth period, the Up output of the phase comparator 470 becomes “H”. As a result, the first bit Uo [0] of the addition register 493 of the control register circuit 450 becomes “H”, and the driver 485b of the clock line 432 is strengthened. In the fifth period, the Dn output of the phase comparator 470 becomes “L”, the first bit Do [0] of the addition register 494 of the control register circuit 450 becomes “H” (not shown), and the driver of the clock line 432 Reduce the ability of 485b. In the sixth period, the Up output of the phase comparator 470 becomes “H” again. Since the phase difference between the clock lines 432 and 431 cannot be reduced any more, the control register circuit 450 outputs the comparison completion signal 463, the bypass control signal 473 becomes “H” in the seventh period, and the output signal of the PLL circuit 50 Is supplied from the clock distribution circuit 480 to each functional block.

  As described above, by adjusting the strength of the clock drivers 485a and 485b of the clock distribution circuit 480 in advance before the PLL circuit 50 operates stably, the clock skew to each functional block can be reduced, and the semiconductor integrated circuit The clock phase of the circuit 400 can be adjusted with high accuracy.

<Embodiment 5>
FIG. 20 shows an example of a semiconductor integrated circuit according to the present invention. A PLL circuit 50 operating with the reference clock 100; a clock supply circuit 60 connected to the output of the PLL circuit 50; a switch circuit 420 for switching the reference clock 100 and the output of the clock supply circuit 60 with a bypass control signal 703; An SRAM (Static Random Access Memory) circuit 700 synchronized with the output of the circuit 420 is provided. The SRAM circuit 700 has an address 741 at an input port, an SRAM data output 763 and an bypass control signal 703 at an output port. The SRAM circuit 700 also includes an address driving circuit 740 that drives an address signal line 742 in accordance with an address 741, a memory access circuit 710 including a memory cell array 730 and a row decoder array 720, and a bit line pair 711 of the memory cell array 730. The precharge array for precharging, the sense amplifier array 760 for amplifying the voltage of the bit line pair 711, the comparator 770 for comparing the output 761 of the sense amplifier array 760 with the reference voltage, and the state of the output 771 of the comparator 770 for the reference clock Incremental / decremental register 750 that stores data synchronously at 100, and a sense amplifier activation signal generation circuit 780 that controls the delay time of activation signal 781 of sense amplifier array 760 in the output state of addition / subtraction register 750. Yes. The output of the switch circuit 420 is supplied to the memory access circuit 710 via the buffer 701 and the buffer output signal line 702, and is also supplied to the sense amplifier array 760 via the sense amplifier activation signal generation circuit 780. Reference numerals 782, 783, 784, and 785 denote delay circuits (inverters) in the sense amplifier activation signal generation circuit 780, respectively. The output 762 of the sense amplifier array 760 becomes the SRAM data output 763 through the output circuit array.

  FIG. 21 shows an example of the memory access circuit 710. The memory access circuit 710 includes a dummy memory cell array having N columns of dummy memory cells 731 and a row decoder that always activates the dummy word line 723 in synchronization with the clock when the bypass control signal 703 is inactivated. 721 (FIG. 22), a memory cell array 730 composed of N columns and M rows of memory cells 732, and when the bypass control signal 703 is activated, each word line in the state of address 741 in synchronization with the clock. There are M row decoders 722 (FIG. 23) that activate 724. 22 and 23, 725 is an AND circuit, 726 is a decoding circuit, and 727 is an inverter.

  The dummy memory cell 731 is a circuit as shown in FIG. 24 and has a function of transmitting bit information “0” in the memory cell to the bit line pair (BL, BLB) 712 when the word line (WD) 723 is activated. have.

  The normal memory cell 732 is a circuit as shown in FIG. 25, and has a function of transmitting bit information in the memory cell to the bit line pair (BL, BLB) 712 when the word line (WD) 724 is activated. ing.

  FIG. 26 shows a sense amplifier circuit 764 constituting one bit of the sense amplifier array 760. The sense amplifier circuit 764 of FIG. 26 has N-type MOS transistors 746, 747, 779, P-type MOS transistors 765, 766, 777, 778, and a sense amplifier output line 749.

  FIG. 27 shows an example of the comparator 770. From the sense amplifier array 760, the output o of the sense amplifier circuit 764 connected to the first, N / 2, and N columns of the dummy memory cell array and the ground signal ( (Expected value) is compared by the EXOR circuits 772, 773, 774, the outputs of the EXOR circuits 772, 773, 774 are input to the 3-input AND circuit 775, and the comparator output signal 771 is output from the latch 219 that operates in synchronization with the clock 758. obtain.

  FIG. 28 is an example of the addition / subtraction register 750. The addition / subtraction register 750 includes an inverter 741, a phase comparison completion circuit 200, a 2-bit addition / subtraction register circuit 743, input ports R, CK, Up, and output ports Eo, Uo. The reset signal 759 of the input port R is connected to the phase comparison completion circuit 200 and the input port R of the addition / subtraction register circuit 743, and the input port CK is input to the phase comparison completion circuit 200 and receives the comparator output signal 771. The port Up is input to in of the addition / subtraction register circuit 743 and Din of the phase comparison completion circuit 200. The output clock (clockb) 758 of the phase comparison completion circuit 200 is connected to the clock input port of the addition / subtraction register circuit 743. The 1-bit logic circuit 753 includes AND circuits 756 and 754 and an inverter 742. Reference numeral 752 denotes a 1-bit addition / subtraction register circuit, which includes a 1-bit logic circuit 753 and a flip-flop 757 with reset. Reference numeral 743 denotes an add / subtract register circuit having a 2-bit configuration. 752 is serially connected, and the output bus Uo751 is composed of an inversion of lower bits and upper bits.

  FIG. 29 is a timing chart for explaining FIG. The horizontal axis is time, and the vertical axis is the voltage value of each signal. The respective signals are the bypass control signal 703, the reference clock 100, the dummy word line 723, the bit line pair 711, the comparator output 771, A sense amplifier activation signal 781 and an output bus 751 of the addition / subtraction register 750 are provided. When the signal for starting the operation of the PLL circuit 50, that is, the PLLON signal 56 becomes "H", the reset of the flip-flop 757 in the addition / subtraction register 750 is released. Initially, since the bypass control signal 703 is “L”, the reference clock 100 is directly connected to the SRAM circuit 700. Then, the dummy word line 723 rises, the internal bit information “0” of the dummy memory cell 731 is transmitted to the bit line pair 712 of the dummy memory cell 731, and a difference occurs in the voltage of the bit line pair 711. The activation signal 781 is activated. The comparison is performed by the comparator 770. In this example, since the comparison results are different in the first period, they are added, and the output bus 751 of the addition / subtraction register 750 outputs 01. As a result, the driver delay of the sense amplifier activation signal 781 is added, and normal operation is enabled in the second period.

  The normal operation is performed even in the third period, the bypass control signal 703 becomes “H” from the phase comparison completion circuit 200, the internal contents of the addition / subtraction register 750 are held, and the clock from the clock supply circuit 60 is transferred to the SRAM circuit 700. To be supplied.

  As described above, the racing error between the sense amplifier activation signal 781 and the word line can be removed before the PLL circuit 50 operates stably, and a highly accurate SRAM circuit 700 and semiconductor integrated circuit can be realized.

<Embodiment 6>
FIG. 30 shows an example of a semiconductor integrated circuit according to the present invention. A data holding circuit 70 in FIG. 30 includes a circuit 81 in which two stages of dynamic circuits 92 and 93 are serially connected, a switch circuit 420 that switches between the reference clock 100 and the output of the clock supply circuit 60 by a bypass control signal 90. It has. The first-stage dynamic circuit 92 includes N-type MOS transistors 71, 72, 73 and 74 and a P-type MOS transistor 75, and receives a clock 85 from the switch circuit 420. When the bypass control signal 90 is inactivated, in the first-stage dynamic circuit 92, the N-type MOS transistor 74 is turned on / off in synchronization with the clock 85, and the N-type MOS transistors 71, 72, 73 are turned on. Always off. When the bypass control signal 90 is activated, the gates of the N-type MOS transistors 71, 72, 73 are connected to normal data lines 87, 88, 89, respectively. The second-stage dynamic circuit 93 connected to the output node 94 of the first-stage dynamic circuit 92 includes N-type MOS transistors 77 and 78, a P-type MOS transistor 76, and an inverter 79, and includes a delay adjustment circuit 84. Is given a clock 91. The output 82 of the dynamic circuit 93 at the second stage is compared with the expected value by the comparator 80, and the comparator output 83 held in the latch 219 operating in synchronization with the clock 758 is supplied to the control register (addition / subtraction register) 750. Is done. The driver 91 in the delay adjustment circuit 84 can be increased in strength with respect to the clock 91 supplied to the second stage dynamic circuit 93 by the output bus 86 of the control register 750.

  FIG. 31 is a timing chart for explaining FIG. The horizontal axis represents time, and the vertical axis represents the voltage value of each signal. The bypass control signal 90, the reference clock 100, the clock signal 85 of the first dynamic circuit, the clock signal 91 of the second dynamic circuit, and the dynamic circuit output signal 82, an output signal 83 of the comparator, and an output 86 of the addition / subtraction register 750. When the PLLON signal 56 becomes “H”, the addition / subtraction register 750 is released from reset. Since the bypass control signal 90 is “L”, the clock 85 of the first-stage dynamic circuit is directly connected to the reference clock 100. Further, since the bypass control signal 90 is “L”, the N-type MOS transistor 74 is turned on / off, and the N-type MOS transistors 71, 72, 73 are turned off. In the first cycle clock, the dynamic circuit output 82 outputs “H”. Originally, it should be “L”. The comparison circuit 80 outputs “H”, and the register output 86 changes from 01 to 10. This increases the delay of the clock 91 of the second dynamic circuit. In the second period, the dynamic circuit output 82 becomes “L”, and normal operation is possible. In the third period, another mistake is made and a hit is made in the fourth period. Then, the addition / subtraction register 750 sets the bypass control signal 90 to “H” to hold the register internal information, and the dynamic circuit 81 is directly connected to the output of the clock supply circuit 60.

  As described above, the delay of the clock 91 is adjusted so that the second stage dynamic circuit 93 is activated after the potential of the output node 94 of the first stage dynamic circuit 92 is determined. Thereby, the racing error of the two-phase clock of the dynamic circuit 81 connected in serial can be removed until the PLL circuit becomes stable, and a highly accurate semiconductor integrated circuit can be realized.

  In the fourth to sixth embodiments, when another type of clock generation circuit is adopted instead of the PLL circuit 50, the reference clock 100 is used before the clock generation circuit supplies a system clock signal. Thus, the adjustment of the corresponding part in each embodiment is executed.

<Embodiment 7>
FIG. 32 shows an example of a semiconductor integrated circuit according to the present invention. Reference numeral 1000 denotes a semiconductor integrated circuit. Reference numeral 1010 denotes a cache circuit that synchronizes with a clock when the block reset signal is canceled, and includes a tag unit 1020 and a data unit 1040. The tag unit 1020 includes an SRAM circuit 1025 and a comparison circuit 1030. The lower address is used to read the upper address from the SRAM circuit 1025 storing the upper address in the tag, and the upper circuit address from the external block is read by the comparison circuit 1030. Compare. The data unit 1040 has a function of accessing the internal memory with a lower address, receiving a hit signal 1031 from the tag unit 1020, and outputting or writing data when the hit signal 1031 indicates a hit. The data portion 1040 includes a sense amplifier and an output circuit. The data portion 1040 operates by receiving the hit signal 1031 from the activation signal 1043 and the output activation signal 1044 of the sense amplifier, or always operates in synchronization with the clock. Is provided with a circuit 1041 for controlling the signal by a register signal 1052. In addition, the semiconductor integrated circuit 1000 includes a functional block C that is synchronized with the clock 61 when the block reset signal is canceled. The output data from the data portion 1040 of the internal cache is fetched with the clock 61 and the expected value is obtained. A comparison circuit 1060 for comparison is provided. The comparison circuit 1060 also has a function of holding the internal contents of one clock cycle. The control register 1050 synchronizes with the clock 62, releases the reset of the internal register with the phase fine adjustment period transmission signal 1071, the internal register is an incremental counter, and the output signal 1061 of the comparison circuit 1060 is “L”. At this time, it operates in synchronization with the clock and stops when it becomes “H”. Then, a stop signal (Eo) 1051 is output.

  Further, the semiconductor integrated circuit 1000 has a phase fine adjustment period transmission circuit 1070 having a function of transmitting a state in which the phase fine adjustment period is reached when the PLL circuit 50 enters the phase fine adjustment period from the pull-in period. . FIG. 33 shows an example of the phase fine adjustment period transmission circuit 1070, which includes a quadrature divider 1072 synchronized with a reference clock, a 4-bit addition register / OR circuit 1073, and a flip-flop 1074. When either one of the upper 2 bits is “H”, this circuit outputs “H” to 1071, thereby transmitting that the phase fine adjustment period has been reached. Each bit addition register 259 constituting the addition register circuit 1073 has the internal configuration shown in FIG.

  The phase fine adjustment period transmission signal 1071 cancels the reset of the control register 1050 in the data portion 1040. The cache circuit 1010 accesses the dummy memory cell only when the block reset signal is “L” and the phase fine adjustment period transmission signal 1071 is “H”, and the comparison circuit 1030 hits every cycle. In the data portion 1040, the dummy memory cell is accessed and read out every cycle. The dummy memory cell is a circuit having a function as shown in FIG.

  FIG. 34 shows a configuration example of the switch circuit 1042 in FIG.

  FIG. 35 is a timing chart for explaining FIG. The horizontal axis is time, and the vertical axis is the voltage of each signal line. Each signal line includes a block reset signal, a phase fine adjustment period transmission signal 1071, a PLL feedback signal Fr, a tag hit signal 1031, a cache data portion dummy word line 723, a sense amplifier activation signal 1043, and an output activation signal 1044. This is a circuit output signal 1061. Until the PLL circuit 50 rises and oscillation is stabilized, the block reset signal is “L”, and even if data access to each functional block is performed, it is invalid. When the PLL circuit 50 enters the phase fine adjustment period, the phase fine adjustment period transmission signal 1071 becomes “H” and is supplied to the cache circuit 1010.

  The comparison circuit 1060 always synchronizes with the clock 61 and outputs a clock delayed by the memory access of the tag unit 1020.

  The dummy word line 723 of the data portion 1040 always operates only during the phase fine adjustment period. As for the register output 1052 in the first period, the sense amplifier activation signal 1043 is operated by the tag hit signal 1031, and only the clock 62 operates in synchronization with the output activation signal 1044. In this example, the comparison circuit 1060 misses, and the sense amplifier activation signal 1043 generated by the tag hit signal 1031 detects that it is impossible to output normal data. In the second period, the output of the control register 1050 is changed from 01 to 10.

  The sense amplifier activation signal 1043 is synchronized with the clock 61, and the output activation signal 1044 operates in response to the tag hit signal 1031. However, the comparison circuit 1060 hits in the third period, and this time, it is detected that normal data can be output by the output activation signal 1044 generated by the tag hit signal 1031. The control register 1050 holds the contents.

  As described above, when the oscillation clock frequency of the PLL circuit 50 is determined as to which operation of the sense amplifier or the output circuit in the data unit 1040 is to be stopped when the tag unit 1020 indicates a cache miss during normal operation. Thus, it is determined according to the frequency. Specifically, the operation of the sense amplifier is stopped when the clock frequency is low, and the operation of the output circuit is stopped while allowing the operation of the sense amplifier when the clock frequency is high. As a result, in order to reduce power consumption according to the clock frequency, device conditions, and temperature dependence, when invalid data is stopped in the middle of one cycle of the clock, it can be stopped by an optimal logic unit. That is, a semiconductor integrated circuit capable of efficiently reducing power consumption can be realized.

  In each of the above embodiments, the reference clock 100 may be supplied from the internal oscillation circuit of the semiconductor integrated circuit or may be supplied from the outside of the semiconductor integrated circuit.

1 is a block diagram of a semiconductor integrated circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the phase comparator in FIG. FIG. 2 is a circuit diagram showing a configuration of a reset control voltage circuit in FIG. 1. 3 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. 1. FIG. 5 is a block diagram of a semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 6 is a circuit diagram showing a configuration of a PLL circuit in FIG. 5. FIG. 6 is a circuit diagram showing a configuration of a reference voltage circuit in FIG. 5. FIG. 6 is a circuit diagram showing a configuration of a switch circuit in FIG. 5. 6 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. FIG. 6 is a block diagram of a semiconductor integrated circuit according to a third embodiment of the present invention. It is a circuit diagram which shows the structure of the switch circuit in FIG. It is a circuit diagram which shows the structure of the other switch circuit in FIG. 11 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. It is a block diagram of the semiconductor integrated circuit which concerns on the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the phase comparator in FIG. It is a circuit diagram which shows the structure of the switch circuit in FIG. FIG. 15 is a block diagram showing a configuration of a register control circuit in FIG. 14. It is a circuit diagram which shows the structure of the ripple detection completion circuit in FIG. 15 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. It is a block diagram of the semiconductor integrated circuit which concerns on the 5th Embodiment of this invention. FIG. 21 is a block diagram showing a configuration of a memory access circuit in FIG. 20. FIG. 22 is a circuit diagram showing a configuration of a dummy row decoder in FIG. 21. FIG. 22 is a circuit diagram showing a configuration of a normal row decoder in FIG. 21. FIG. 22 is a circuit diagram showing a configuration of a dummy memory cell in FIG. 21. FIG. 22 is a circuit diagram showing a configuration of a normal memory cell in FIG. 21. FIG. 21 is a circuit diagram showing a unit configuration of the sense amplifier array in FIG. 20. It is a circuit diagram which shows the structure of the comparator in FIG. It is a block diagram which shows the structure of the addition / subtraction register | resistor in FIG. 21 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. It is a block diagram of the semiconductor integrated circuit which concerns on the 6th Embodiment of this invention. 31 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. 30. It is a block diagram of the semiconductor integrated circuit which concerns on the 7th Embodiment of this invention. FIG. 33 is a circuit diagram showing a configuration of a phase fine adjustment period detection circuit in FIG. 32. FIG. 33 is a circuit diagram showing a configuration of a switch circuit in FIG. 32. 33 is a timing chart for explaining the operation of the semiconductor integrated circuit of FIG. 32.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reset control voltage generation circuit 30 Digital phase comparator 31 Reset circuit 31a 4 input NAND circuit 31b Transfer gate 40,520,801 Charge pump circuit 50,500,800 PLL circuit 51 Phase comparator 55,501,510 Switch circuit 70 Data Holding circuit 81 Dynamic circuit 480 Clock distribution circuit 600 Reference voltage circuit (bandgap reference circuit)
700 SRAM circuit (memory circuit)
760 Sense amplifier array 1010 Cache circuit (functional circuit)
1020 Tag unit 1040 Data unit 1070 Phase fine adjustment period detection circuit

Claims (14)

A semiconductor integrated circuit including therein a clock generation circuit that generates a system clock signal from a reference clock signal and a specific circuit portion that operates based on the system clock signal generated by the clock generation circuit,
The clock generation circuit includes:
A phase comparator having a first input unit to which the reference clock signal is input and a second input unit;
A feedback signal output via the phase comparator, and a switch circuit to which the reference clock signal and the control signal are input,
The switch circuit outputs either the feedback signal or the reference clock signal to the phase comparator according to the control by the control signal, and the phase comparator is provided at the second input unit of the phase comparator. One of the feedback signal and the reference clock signal output from the signal is input, and the phase comparator generates an output signal based on the signals input from the first input unit and the second input unit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 1,
The clock generation circuit includes:
A loop filter to which a signal output via the phase comparator is input;
A voltage-controlled oscillator to which a signal output through the loop filter is input;
The semiconductor integrated circuit according to claim 1, wherein the feedback signal is a signal output via the voltage controlled oscillator. The semiconductor integrated circuit according to claim 1,
The switch circuit outputs the reference clock signal to the phase comparator before the system clock signal is stably oscillated. The semiconductor integrated circuit according to claim 1,
The semiconductor integrated circuit, wherein the reference clock signal is output from the switch circuit to the phase comparator before the clock generation circuit outputs the system clock signal to adjust the specific circuit portion. The semiconductor integrated circuit according to claim 3 .
The semiconductor integrated circuit characterized by having a function of adjusting the delay before Symbol reset signal in said phase comparator as the detection dead zone of the phase difference becomes smaller in the phase comparator. The semiconductor integrated circuit according to claim 5, wherein
2. The semiconductor integrated circuit according to claim 1, wherein the phase comparator includes a transfer gate for transmitting the reset signal, and a gate voltage of the transfer gate is adjusted according to a reset control voltage. The semiconductor integrated circuit according to claim 3 .
The clock generation circuit includes a current type charge pump circuit to which a signal output from the phase comparator is input ,
The semiconductor integrated circuit characterized by having a function of pre-SL current charge pump circuit bandgap reference circuits for supplying a reference voltage to the adjusted amount of phase compensation of the bandgap reference circuit so as not to cause oscillation . The semiconductor integrated circuit according to claim 3 .
The clock generation circuit includes a current type charge pump circuit to which a signal output from the phase comparator is input ,
The semiconductor integrated circuit characterized by having a function of adjusting the current driving capability of the previous SL current type charge pump circuit. The semiconductor integrated circuit according to claim 3 .
Characterized in that it has a function of adjusting the skew between several clock drivers before Symbol within the clock distribution circuit so as to reduce the output clock skew of the clock distribution circuitry for distributing the system clock signal to a plurality of functional blocks A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 3 or 4,
The specific circuit portion is a data holding circuit that operates in synchronization with the system clock signal,
A semiconductor integrated circuit having a function of performing racing adjustment in an internal operation of the data holding circuit. The semiconductor integrated circuit according to claim 10.
The data holding circuit is a memory circuit having a word line and a sense amplifier, and has a function of adjusting the activation timing of the sense amplifier with respect to the activation of the word line so that a read error does not occur in the memory circuit. A semiconductor integrated circuit comprising: The semiconductor integrated circuit according to claim 10.
The data holding circuit includes a first dynamic circuit and a second dynamic circuit connected serially to each other, and a delay circuit for delaying an input clock signal of the first dynamic circuit and supplying it to the second dynamic circuit Have
The reference clock signal is bypassed to the first dynamic circuit and the delay circuit to optimize the activation timing of the second dynamic circuit with respect to an output change of the first dynamic circuit. A semiconductor integrated circuit having a function of adjusting a delay amount. The semiconductor integrated circuit according to claim 3 or 4,
The specific circuit portion is a functional circuit that operates in synchronization with the system clock signal,
In order to reduce power consumption of the functional circuit, it has a function of adjusting which part in the functional circuit is stopped according to the frequency of the system clock signal of the clock generation circuit. A semiconductor integrated circuit. The semiconductor integrated circuit according to claim 13.
The functional circuit is a cache circuit having a tag part and a data part,
A semiconductor integrated circuit having a function of adjusting which operation of a sense amplifier or an output circuit in the data portion is stopped when the tag portion indicates a cache miss.

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