JPS5779738A - Delay equalizing circuit - Google Patents
Delay equalizing circuitInfo
- Publication number
- JPS5779738A JPS5779738A JP55155683A JP15568380A JPS5779738A JP S5779738 A JPS5779738 A JP S5779738A JP 55155683 A JP55155683 A JP 55155683A JP 15568380 A JP15568380 A JP 15568380A JP S5779738 A JPS5779738 A JP S5779738A
- Authority
- JP
- Japan
- Prior art keywords
- delay
- input data
- address
- data
- write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Filters And Equalizers (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
PURPOSE:To reduce the capacity of delay memory and to minimize the delayed amount of data, by discriminating input data with most delay out of several input data, detecting the difference of delay among this input data and each input data and performing readout control of each data written in the delay memory accroding to the difference of delay, in a delay equalizing circuit used for parallel transmission data. CONSTITUTION:In response to the clock from a terminal 1 by a write-in address counter 4, an address to write in input data from terminals 2a...2c to delay memories 5a...5c is produce. Write-in address storage circuits 10a-10c store the write-in address in response to the output of frame synchronizing circuits 3a-3c. The address corresponds to the delay in the input data. When a discrimination circuit 11 detects the frame synchronizing pulse of input data with most delay out of input data, an address corresponding to the delay of input data is loaded to readout address counters 9a-9c and the data are read out from each delay memory according to each readout address counter.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55155683A JPS5779738A (en) | 1980-11-05 | 1980-11-05 | Delay equalizing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55155683A JPS5779738A (en) | 1980-11-05 | 1980-11-05 | Delay equalizing circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5779738A true JPS5779738A (en) | 1982-05-19 |
JPS6124852B2 JPS6124852B2 (en) | 1986-06-12 |
Family
ID=15611276
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55155683A Granted JPS5779738A (en) | 1980-11-05 | 1980-11-05 | Delay equalizing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5779738A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01260941A (en) * | 1988-04-11 | 1989-10-18 | Nec Corp | Multiplexer |
JPH02192240A (en) * | 1988-10-17 | 1990-07-30 | Fujitsu Ltd | Transmission delay correcting system |
JPH0448839A (en) * | 1990-06-16 | 1992-02-18 | Fujitsu Ltd | Reception data synchronization circuit |
JPH05292077A (en) * | 1992-04-10 | 1993-11-05 | Nec Corp | Delay time difference eliminating device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03124351U (en) * | 1990-03-29 | 1991-12-17 |
-
1980
- 1980-11-05 JP JP55155683A patent/JPS5779738A/en active Granted
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01260941A (en) * | 1988-04-11 | 1989-10-18 | Nec Corp | Multiplexer |
JPH02192240A (en) * | 1988-10-17 | 1990-07-30 | Fujitsu Ltd | Transmission delay correcting system |
JPH0448839A (en) * | 1990-06-16 | 1992-02-18 | Fujitsu Ltd | Reception data synchronization circuit |
JPH05292077A (en) * | 1992-04-10 | 1993-11-05 | Nec Corp | Delay time difference eliminating device |
Also Published As
Publication number | Publication date |
---|---|
JPS6124852B2 (en) | 1986-06-12 |
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