JPS59139425A - Data transfer control system - Google Patents
Data transfer control systemInfo
- Publication number
- JPS59139425A JPS59139425A JP58009537A JP953783A JPS59139425A JP S59139425 A JPS59139425 A JP S59139425A JP 58009537 A JP58009537 A JP 58009537A JP 953783 A JP953783 A JP 953783A JP S59139425 A JPS59139425 A JP S59139425A
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- peripheral devices
- central processing
- data
- data transfer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
Description
【発明の詳細な説明】
囚 発明の技術分野
本発明は、中央処理装置(CPU)の制御t−受けて複
数の周辺装置相互間のデータの授受上制御する補助制御
装置を備えるコンピュータシステムに関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a computer system including an auxiliary control device that controls the exchange of data between a plurality of peripheral devices under the control of a central processing unit (CPU).
(B) 技術の背景
例えば外部記憶装置として磁気ディスクル装置を備える
コンピュータシステムにおいては、データ記憶媒体の保
存あるいは移動の便を図るため、一般に磁気テープをも
備え、磁気ディスク装置と磁気テープ装置との間で頻繁
にデータの授受すなわち転送をおこなっている。(B) Background of the Technology For example, in a computer system equipped with a magnetic disk drive as an external storage device, in order to facilitate the storage or movement of data storage media, it is generally equipped with a magnetic tape, and the magnetic disk drive and magnetic tape drive are combined. Data is frequently exchanged or transferred between the two.
したがって、このようなコンピュータシステムにおいて
は、CPU(D負荷を軽減させるため、OPUと複数の
外部記憶装置との間に、例えばバックアップファイルコ
ントローラ (BUFO)と称せられるような、補助制
御装置を設け、磁気ディスク装置と磁気テープ装置との
間のデータの転送の制御を前記B F’UOにおこなわ
せるようにしている。Therefore, in such a computer system, in order to reduce the load on the CPU (D), an auxiliary control device, such as a backup file controller (BUFO), is provided between the OPU and the plurality of external storage devices. The B F'UO is configured to control data transfer between the magnetic disk device and the magnetic tape device.
(q 従来技術と問題点
前記BUFoを設けたコンピータシステムにおいても、
CPUと周辺装置との間でデータの転送がおこなわれる
のでろるが、従来、BUFOに対するバイパス回が設け
られてぃなかった。またBUFOのデータ転送用バッフ
ァには通常、0M−08のLSI1用いており、したが
って1バイト毎のデータの歓送に長時間ヲ要し、したが
って、オーバーランに陥るという問題が生じていた。(q Conventional technology and problems Even in the computer system equipped with the above-mentioned BUFo,
This is true because data is transferred between the CPU and peripheral devices, but conventionally, there has been no bypass circuit for the BUFO. Further, the BUFO data transfer buffer normally uses an 0M-08 LSI1, and therefore it takes a long time to send data byte by byte, resulting in an overrun problem.
0 発明の目的
不兄明の目的は、CPUと周辺装置との間に8TI記B
UF’Oのような補助制御装Ti?設けたコンピュータ
システムにおいて、公費に応じて、OPUと周辺装置と
の間のデータの転送速度を増大できるようにすることに
める。0 Purpose of the Invention The purpose of the invention is to create a connection between the CPU and peripheral devices in Section 8TI B.
Auxiliary control device Ti like UF'O? In the provided computer system, the data transfer speed between the OPU and peripheral devices can be increased at public expense.
(H+’) 発明の構成
本発明になるデータ転送制御方式は、中央処理装置と複
数の周辺装置と前記中央処理装置の制御をうけて前記複
数の周辺装置相互間のデータの授受の制御をおこなう補
助制御装置とを備えるコンビエータシステムにおいて、
前記中央処理装置と前記複数の周辺装置の少なくともい
ずれかとの間に前記補助制御装置全バイパスするバイパ
ス路を設け、授受するデータの内容に応じて前記補助制
御襞tを経由することなく前記中央処理装置と前記複数
の周辺装置のいずれかとの間のデータおよび信号の授受
?おこなうようにしたものでるる。(H+') Structure of the Invention The data transfer control method according to the present invention controls data transfer between a central processing unit, a plurality of peripheral devices, and the plurality of peripheral devices under the control of the central processing unit. In a combiator system comprising an auxiliary control device,
A bypass path that completely bypasses the auxiliary control device is provided between the central processing unit and at least one of the plurality of peripheral devices, and depending on the content of data to be exchanged, the central processing unit can bypass the auxiliary control device t. Transfer of data and signals between the device and any of the plurality of peripheral devices? This is what I tried to do.
■ 発明の実施例
以下、本発明の要旨全図示実施例によって具体的に説明
する。① Embodiments of the Invention The gist of the present invention will be specifically explained below with reference to fully illustrative embodiments.
M1図は本発明の一実施例のシステム構成図を示し、・
lは中央処理装置(OF(J) 、2は0PUIとHi
己BUFOとの間に設けられるドライバレシーバ、8は
0PUIの制御?うけて俊Sピ複数の周辺装置すなわち
磁気ディスク装置と#i気テーグ装置との間のデータの
授受すなわち転送の制御t&こなう補助制御装置(BU
FO)、4にBUPOBと後記磁気テーグ装瀘との間に
設けられるドライバレシーバ、5に磁気テープ装置、6
はBUFOBと後記磁気ディスク装置との間に設けられ
るドライバレシーバ、8は0PUlと磁気ディスク装置
7との間に設けられBUFO8=2バイパスするバイパ
ス路、81はバイパス路8に設けられるグー)、81は
BUFO8に設けられる制御回路、82はBUFO8に
設けられ磁気テープ装置5用のバッファ、88はバッフ
ァ82と後記バッファの間に設けられるゲート、84は
BUF’08に設けられ磁気ディスク装置7用のバッフ
ァである。Diagram M1 shows a system configuration diagram of an embodiment of the present invention,
l is the central processing unit (OF (J), 2 is 0PUI and Hi
Driver receiver installed between own BUFO, 8 is 0PUI control? In response, an auxiliary control unit (BU) is used to control and receive data, that is, transfer, between multiple peripheral devices, that is, magnetic disk devices, and the #i key device.
FO), 4 is a driver receiver provided between BUPOB and the magnetic tape device described later, 5 is a magnetic tape device, 6
is a driver receiver provided between BUFOB and the magnetic disk device described later, 8 is a bypass path provided between 0PUl and the magnetic disk device 7 to bypass BUFO8=2, and 81 is a bypass path provided in bypass path 8), 81 is a control circuit provided in BUFO 8, 82 is a buffer provided in BUFO 8 for the magnetic tape device 5, 88 is a gate provided between the buffer 82 and the buffer described below, and 84 is a control circuit provided in BUF'08 for the magnetic disk device 7. It is a buffer.
第2図に、0PUIと磁気ディスク装yt7との間のデ
ータ転送におけるタイムチャート全示し、ドの送出、(
b)ハパラメータの送出、(C)はデータの転送、(d
)はコマンド終了報告の受付け、(e)はビジー信号、
(f)はパンメータリクエスト、(鱒にアテンション、
(h)はデータの転送、(i)はコマンド終了報告のた
めの割込要求である。FIG. 2 shows the complete time chart for data transfer between 0PUI and magnetic disk drive yt7, the sending of
b) Send parameters, (C) transfer data, (d)
) is for receiving command completion report, (e) is for busy signal,
(f) is a pan meter request, (attention to trout,
(h) is an interrupt request for data transfer, and (i) is an interrupt request for command completion report.
アテンション信号(ロ))がオンになるとゲート8Bが
閉じられるとともにグー)81が囲がれ、また、アテン
ション信号(g)がオフになるとゲート8Bが開かれる
とともにゲート81が閉じられる。アテンション信号(
g)の監視ならびにゲート88およびグー)81の制御
はBUFO8に内蔵されているマイクロ10セツサ(図
示省略)によってなされる0
このようにして、データの転送(c)・(b) iバイ
パス路8を介しておこなわれる。When the attention signal (b) is turned on, the gate 8B is closed and the gate 81 is surrounded, and when the attention signal (g) is turned off, the gate 8B is opened and the gate 81 is closed. attention signal (
Monitoring of g) and control of gate 88 and g) 81 are performed by a micro 10 setter (not shown) built into BUFO 8. In this way, data transfer (c) and (b) i bypass path 8 This is done through
な2、本実施例によれは、OP U l vAllがら
7Fs出されるコマンド(a)およびパンメータ(b)
’tバッファ82に格納することができる。同僚に磁気
ディスク装fi?から送出されるコマンド終?@i告(
ト)をバッファ84に格納することができ@。したがっ
て、これら全エラー解析用として利用することができる
C
0 発明の効果
以上説明しfcように、不発明によれば、補助制御装置
のデータ転送用バッファが低速でめっても、CPUと周
辺装置との間のデータの転送を補助制御装置全経由する
ことなく直接におこなうことができるので転送速度全増
大することができる。2. According to this embodiment, the command (a) and pan meter (b) issued for 7Fs from OP U l vAll
't buffer 82. Does your co-worker have a magnetic disk drive? The end of the command sent from ? @i notification (
) can be stored in the buffer 84. According to the invention, even if the data transfer buffer of the auxiliary control device is slow and rare, the CPU and peripheral Since data can be transferred directly to and from the device without going through all the auxiliary control devices, the transfer speed can be increased.
第1図は本発明一実施例のシステム構成図、また第2図
はデータ転送におけるタイムチャートを示し、第1図に
おいてUl;C0PtT、81qBUFO。
5は磁気チー1装置、7は磁気ディスク装置、8はバイ
パス路である。FIG. 1 is a system configuration diagram of an embodiment of the present invention, and FIG. 2 is a time chart for data transfer. In FIG. 1, Ul; C0PtT, 81qBUFO. 5 is a magnetic chip 1 device, 7 is a magnetic disk device, and 8 is a bypass path.
Claims (1)
御をうけて前記複数の周辺装置相互間のデータ授受の制
御をおこなう補助?[i4御装置と金備えるフンex−
タシステムにおいて、前記中央処理装置と前記複数の周
辺装置の少なくともいずれかとの間に前記補助制御装置
全バイパスするバイパス路を設け、授受するデータの内
容に応じて前記補助制御装置を経由することなく前記中
央処理装置と前り己複歓の周辺装置のいずれかとの間の
データの授受tおこなうこと全特徴とするデータ転送制
御方式。A central processing unit, a plurality of peripheral devices, and an assistant that controls data transfer between the plurality of peripheral devices under the control of the central processing unit? [i4 control equipment and money ex-
In the data system, a bypass path for completely bypassing the auxiliary control device is provided between the central processing unit and at least one of the plurality of peripheral devices, and depending on the content of the data to be exchanged, the bypass path is provided to completely bypass the auxiliary control device. A data transfer control method characterized by the fact that data is exchanged between a central processing unit and any of its peripheral devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58009537A JPS59139425A (en) | 1983-01-24 | 1983-01-24 | Data transfer control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58009537A JPS59139425A (en) | 1983-01-24 | 1983-01-24 | Data transfer control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59139425A true JPS59139425A (en) | 1984-08-10 |
Family
ID=11723012
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58009537A Pending JPS59139425A (en) | 1983-01-24 | 1983-01-24 | Data transfer control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59139425A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04279954A (en) * | 1991-03-07 | 1992-10-06 | Fujitsu Ltd | Data transfer system for device controller |
US6987773B1 (en) | 1999-05-11 | 2006-01-17 | Sharp Kabushiki Kaisha | Apparatus and method for transferring data |
WO2007096983A1 (en) * | 2006-02-24 | 2007-08-30 | Fujitsu Limited | Data input/output controller |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5236438A (en) * | 1975-09-17 | 1977-03-19 | Sanyo Electric Co Ltd | Channel device |
JPS539450A (en) * | 1976-07-14 | 1978-01-27 | Nec Corp | Primary digital overall areas passing circuit |
-
1983
- 1983-01-24 JP JP58009537A patent/JPS59139425A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5236438A (en) * | 1975-09-17 | 1977-03-19 | Sanyo Electric Co Ltd | Channel device |
JPS539450A (en) * | 1976-07-14 | 1978-01-27 | Nec Corp | Primary digital overall areas passing circuit |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04279954A (en) * | 1991-03-07 | 1992-10-06 | Fujitsu Ltd | Data transfer system for device controller |
US6987773B1 (en) | 1999-05-11 | 2006-01-17 | Sharp Kabushiki Kaisha | Apparatus and method for transferring data |
WO2007096983A1 (en) * | 2006-02-24 | 2007-08-30 | Fujitsu Limited | Data input/output controller |
JPWO2007096983A1 (en) * | 2006-02-24 | 2009-07-09 | 富士通株式会社 | Data I / O controller |
JP4724743B2 (en) * | 2006-02-24 | 2011-07-13 | 富士通株式会社 | Data transfer apparatus and data transfer apparatus control method |
US8073999B2 (en) | 2006-02-24 | 2011-12-06 | Fujitsu Limited | Data input-output control apparatus |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS57117027A (en) | Signal sending and receiving circuit | |
JPS59139425A (en) | Data transfer control system | |
JPS55135955A (en) | Magnetic disk control device of double recording system | |
JPS5534756A (en) | Double recording system of magnetic disc device | |
JPS6027014A (en) | Magnetic disk controller | |
JPH069036B2 (en) | I / O controller | |
JPS6161432B2 (en) | ||
JPS6235148B2 (en) | ||
KR940009830B1 (en) | Control logic device | |
JPS6139126A (en) | Magnetic tape recording device | |
JPS59174648U (en) | auxiliary storage | |
JPS55154649A (en) | Disc cash write-in system | |
JPS58121200A (en) | Data buffer diagnosing system | |
JPH0573484A (en) | Information processing system | |
JPS63211169A (en) | Magnetic tape control mechanism | |
JPS58179536U (en) | I/O channel control device | |
JPS63300346A (en) | Dma control system | |
JPH05189351A (en) | Bus converter | |
JPS58183539U (en) | Power outage processing circuit | |
JPS59123032A (en) | Input and output control system | |
JPH03171245A (en) | Dma control system | |
JPS5953929A (en) | Data transfer device | |
JPS62131358A (en) | Data transfer equipment | |
JPS57101959A (en) | Main storage device | |
JPS60100853U (en) | I/O event recorder |