JPH04283848A - Data transfer control system - Google Patents

Abstract

PURPOSE:To shorten the data transfer time of a data transfer device. CONSTITUTION:The device 12 is equipped with an interface 13 which operates with interface standards whose transferred data amount is specifies with a 1st transferred data block, a counting means 16 which counts the amount of transferred data, and a data transfer means 17 which stops a data transfer process when the data transfer is carried out by the data amount specified by the counting means 16, and performs the data transfer with a device 11 which is connected through the interface 13. This device is provided with a detecting means 14 which detects the 1st transferred data block and a setting means 15 which sets the amount of transfer data indicated by the 1st transferred data block in the counting means 16 according to the detection result of the detecting means 14, and the data transfer is started when the setting means 15 sets the amount of transfer data in the counting means 16.

Description

[Detailed description of the invention]

0001

[Industrial field of application] The present invention is advantageous in that the amount of data transferred is
The present invention relates to a device that transfers data according to an interface standard specified in data to be transferred, and particularly relates to a data transfer control method that eliminates processor intervention and reduces data transfer time.

In recent years, with advances in semiconductor technology, the processing speed of central processing units in computer systems has improved, so improving the command processing speed of peripheral devices connected to this central processing unit has become an important issue. It has become.

[0003] Therefore, it is necessary to improve the data transfer speed of peripheral devices and reduce internal processing time.

0004

2. Description of the Related Art Among the peripheral devices mentioned above, there is a control device that performs data transfer according to an interface standard in which the amount of data to be transferred is specified in the data to be transferred, for example,
There is a disk controller.

Conventional disk control devices are controlled by a processor, and when transferring data, the processor reads the data input through the interface circuit up to the data block storing the amount of data to be transferred. Either recognizes the amount of data to be transferred and transfers the specified amount of data based on instructions from the program, or starts the data transfer circuit after the processor sets the amount of data to be transferred in the transfer counter etc. of the data transfer circuit. , data transfer was performed by hardware.

FIG. 9 is a block diagram illustrating an example of the prior art, FIG. 10 is a diagram illustrating an interface standard, and FIGS. 11, 12, and 13 are time charts illustrating the operation of FIG.

FIG. 9 shows that the amount of data to be transferred is specified in the first data block of the data to be transferred, and after the processor 8 sets the amount of data to be transferred in the transfer counter 10 of the data transfer control circuit 9, the data transfer control A case is shown in which the circuit 9 is activated to perform data transfer by hardware.

[0008] The interface between the host device 1 and the disk control device 2 is, for example, IPI-3 (Intelli
gent Peripheral Interface
-3), and this interface standard is based on the American ANS
I (American National Stand)
rd Institute).

That is, the command sent by the host device 1 is as follows:
As shown in Figure 10, first the Packet Length
(transfer data amount) is specified, then Command
Reference Number is specified, then O
peration Code is specified, then Com
mon Modifier and Opecode Mo
difier is specified, then Slave Addre
ss is specified, then Facility Addre
ss is specified, and finally Parameters are specified.

When the disk control device 2 is selected and coupled by the host device 1, the processor 8 of the disk control device 2 synchronizes with the clocks shown in FIGS. In order to assert (make valid) the sink-in signal requesting data transmission, the data transfer control circuit 9 is instructed to send the sink-in signal to the host device 1 via the driver/receiver 4 as shown in sink-in in FIG. send it out.

Upon receiving the sink-in signal from the disk control device 2, the host device 1 sends the command "1" shown on the bus in FIG. 11 along with the sink-out signal that instructs the data acquisition timing, as shown in sink-out in FIG. do.

Command “1” is a Packe shown in FIG.
t Length (transfer data amount), is sent to the latch circuit 5 via the driver/receiver 4, is latched as shown in command "1" of the latch circuit in FIG. 11, and is sent to the processor 8. be done.

The processor 8 outputs the sink-out signal as shown in FIG.
When the processor detects a sink-out signal, as shown in Detection by the Processor, it sends an instruction to stop the sink-in signal to the data transfer control circuit 9, as shown in Negate SIN.

As shown in FIGS. 11 and 12, processor command "1" analysis and command transfer preparation, when the amount of data to be transferred is recognized from the contents of command "1", as shown in FIG.
After setting the transfer data amount N in the number of bytes in the transfer counter 10 as shown in the counter 2, the data transfer control circuit 9 is instructed to transfer data as shown in the processor command transfer start instruction in FIGS. 12 and 13.

At the same time, the processor 8 requests the host device 1 to send the next data, and the host device 1 sends a command transfer start signal as shown in FIGS. 12 and 13.

The data transfer control circuit 9, which has received the command transfer start signal via the latch circuit 5, is instructed to transfer data by the processor 8, and therefore sends a sink-in signal to the host device 1, as shown in sink-in in FIG. death,
As shown in the sink-out and bus in FIG. 13, the host device 1 sequentially latches commands "2" to "L" sent together with the sink-out signal in the latch circuit 5 as shown in the latch circuit in FIG. The latched data is sequentially stored word by word in the buffer memory 6.

As shown in the counter in FIG. 13, the set value N of the transfer counter 10 is subtracted 2 bytes at a time because the amount of data to be transferred is 1 word, and when the set value N of the transfer counter 10 becomes 0, the data transfer control circuit 9 stops the data transfer operation, and as shown in FIG. 12, processor command transfer start instruction, processor 8 stops sending command transfer instructions.

If the received command is a write command, the drive control circuit 7 writes the data transferred from the host device 1 to the drive 3 after transferring the command based on the contents of the received command.

Note that the above command "L" is Parameters shown in FIG.

[0020]

[Problems to be Solved by the Invention] Recently, chips capable of high-speed processing have been supplied to the processor 8 of the disk control device 2, but when performing the same work, the processing time in the hardware is longer than the processing time in the program. The processing time of the configured circuit is still faster.

However, conventionally, as described above, the processor 8 receives the command "1" of the processor shown in FIGS. 11 and 12.
As shown in the analysis and preparation for command transfer, when the amount of data to be transferred is recognized from the contents of command "1", the transfer counter 10 is
After setting the amount of data to be transferred, the data transfer control circuit 9 is instructed to start data transfer.

[0022]Therefore, the conventional disk control device 2 has a problem in that the command processing time requires a large amount of time for the intervention of the processor 8, which increases the data transfer processing time. In view of these problems, it is an object of the present invention to provide a command processing circuit that does not require intervention by the processor 8, thereby shortening the data transfer processing time of the disk control device.

[0023]

Means for Solving the Problems FIG. 1 is a block diagram illustrating the principle of the present invention. The data transfer device 12 is shown in FIG.
As shown in (A), an interface 13 that operates according to an interface standard in which the amount of data to be transferred is specified by the first data block to be transferred, a counting means 16 that counts the amount of transferred data, and this counting means 16 The apparatus is equipped with a data transfer means 17 that stops the data transfer process when the data transfer of a specified amount of data is completed, and performs data transfer with the device 11 connected via the interface 13.

[0024] Then, a detection means 14 detects the first data block transferred from the device 11, and based on the detection result of this detection means 14, the amount of transferred data indicated by the first transferred data block is counted. A setting means 15 is provided to set the amount of data to be transferred to the counting means 16, and when the setting means 15 sets the amount of data to be transferred to the counting means 16, data transfer is started.

[0025] Then, when the data transfer of the amount of data specified by the counting means 16 is completed, the data transfer process is stopped. Further, as shown in FIG. 1B, the data transfer device 18 has an interface 19 that operates according to an interface standard in which the amount of data to be transferred is specified in the middle of the data to be transferred, and a counter that counts the amount of data to be transferred. and a data transfer means 17 that stops the data transfer process when the data transfer of the amount of data specified by the counting means 16 is completed, and is connected to the device 11 connected via the interface 19. Transfer data between.

and detection means 20 for detecting a data block specifying the amount of data transferred from the device 11;
Based on the detection result of the detection means 20, the amount of transfer data indicated by the detected data block is calculated by the counting means 20.
6 is provided, and when this setting means 21 sets the amount of data to be transferred in the counting means 16, data transfer is started.

[0027] Then, when the data transfer of the amount of data specified by the counting means 16 is completed, the data transfer process is stopped.

[0028]

[Operation] By configuring as described above, the counting means 16
Since processor intervention is not required when setting the amount of data to be transferred, command processing time is shortened.

Therefore, the data transfer processing time of the data transfer device 12 or 18 can be shortened.

[0030]

Embodiment FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention, and FIGS. 3 and 4 are time charts explaining the operation of FIG. 2.

In FIG. 2, the same reference numerals as in FIG. 9 indicate the same functions. The interface between the host device 1 and the data transfer device 12 is IPI-3. When the data transfer device 12 is selected and coupled by the host device 1, a signal notifying command transfer is transferred from the host device 1 to the driver/receiver 4 of the data transfer device 12, as shown in the command transfer start signal in FIG.

The processor 8 of the data transfer device 12 operates in synchronization with a clock as shown in FIGS. 3 and 4.
As shown in the processor command transfer start instruction in FIG. 3, the data transfer control circuit 25 is instructed to start data transfer.

When the data transfer control circuit 25 receives a command transfer start signal from the host device 1 via the driver/receiver 4, the data transfer control circuit 25 receives a sink-in signal as shown in FIG. is sent to the host device 1 via the driver/receiver 4.

Upon receiving the sink-in signal from the data transfer device 12, the host device 1 sends the command "1" shown on the bus in FIG. 3 along with the sink-out signal that instructs the data acquisition timing, as shown in sink-out in FIG. do.

Command “1” is the Packe shown in FIG.
t Length (transfer data amount), is sent to the latch circuit 22 via the driver/receiver 4, and is latched as shown in the command "1" of the latch circuit 22 in FIG. The data is sent to the buffer memory 6.

The data transfer control circuit 25 includes the latch circuit 2
The multiplexer 24 is switched so that the output of 2 is sent to the transfer counter 10, and the multiplexer 24 sends the command ``1'' sent by the latch circuit 22 to the transfer counter 1 as shown in the command ``1'' of the multiplexer in FIG.
Send to 0.

Furthermore, since the data transfer control circuit 25 enables the flip-flop 26 at the same time as sending out the sync-in signal, the flip-flop 26 is set when notified of reception of the sync-out signal from the driver/receiver 4. As shown in Figure 3 flip-flop, logic ”
1'' to the data transfer control circuit 25.

The data transfer control circuit 25 controls the transfer counter 10 as shown in the load signal in FIG.
Sends a signal to enable loading.

Therefore, the content of the command "1" sent by the multiplexer 24, that is, the transfer data amount N, is calculated by the transfer counter 10 as shown in the transfer data amount N of the counter in FIG.
is set to

After setting the amount of data to be transferred in the transfer counter 10, the data transfer control circuit 25 causes the host device 1 to send out a sink-in signal as shown in sink-in in FIG. As shown in counter 4, the buffer memory 6 is controlled to cause the drive control circuit 7 to transfer data until the set value of the transfer counter 10 becomes 0.

At this time, as shown in FIGS. 3 and 4, processor 8 waits for command transfer to end, the processor 8 does not participate in the above operation after issuing the command transfer start instruction. When transferring the response information to the host device 1, the processor 8 stores the response information read from the drive 3 by the drive control circuit 7 in the buffer memory 6 via the data transfer control circuit 25, and causes the latch circuit 23 to latch it.

The data transfer control circuit 25 switches the multiplexer 24 so that the output of the latch circuit 23 is sent to the transfer counter 10, so that the transfer data amount N specified for the first data block is equal to the transfer counter 10. 1
Sent to 0.

Since the data transfer control circuit 25 simultaneously enables the flip-flop 27, the flip-flop 27 is set by the sink-in signal and the logic
“1” is sent to the data transfer control circuit 25.

The data transfer control circuit 25 sends out a signal that enables the loading of the transfer counter 10 at the timing of sending out the logic "1" sent out by the flip-flop 27. Set the data amount N.

Then, the data read from the buffer memory 6 is transferred to the host device 1 via the latch circuit 23 and driver/receiver 4 until the set value of the transfer counter 10 becomes 0.
Transfer to.

The data transfer control circuit 25 is connected to the processor 8
When setting the transfer data amount to the transfer counter 10, the multiplexer 24 is switched to send the output of the processor 8 to the transfer counter 10.

FIG. 5 is a block diagram of a circuit showing another embodiment of the present invention, and FIGS. 6 to 8 are time charts explaining the operation of FIG. 5. FIG. 5 shows a case where the amount of data to be transferred is specified in the middle of the data to be transferred; for example, a case will be explained where it is specified in the fourth data block.

When the processor 8 is selected and coupled to the host device 1, it instructs the data transfer control circuit 28 to start data transfer, as shown in FIG. 6, processor command transfer start instruction.

When instructed to read data, the data transfer control circuit 28 controls the multiplexer 24 to send the output of the latch circuit 23 to the transfer counter 10, and enables the counter 30.

Further, the counter 30 is set to "4" in order to index the data block whose transfer data amount is specified by the instruction from the processor 8. As shown in the command transfer start signal of FIG. 6, when data transfer is instructed from the host device 1, the data transfer control circuit 28
A request signal as shown in REQ■ is sent to the counter 30, and data is read out from the buffer memory 6 in synchronization with this REQ■, so that the data in the latch circuit in FIG.
As shown in data "1" to data "3", this data is latched by the latch circuit 23 one byte at a time.

The data latched by the latch circuit 23 is
As shown in data "1" to data "3" of the multiplexer in FIG.
It is transferred to the host device 1 via the driver/receiver 4 along with the request signal as shown in EQ■.

At this time, the host device 1 sends an ACK signal notifying data reception as shown in ACK in FIG. The counter 30 receives data from the data transfer control circuit 28.
Every time REQ■ is input, the countdown is performed, as shown in (4), (3), (2), and (1) of the counter 30 in FIG.
Subtract the set value sequentially.

When the set value of the counter 30 becomes 0, as shown at (0) in FIG. 7, a signal instructing the setting of the transfer counter 10 is sent out, as shown at EQU (2) in FIG. Therefore, the data transfer control circuit 28 controls the transfer counter 10
As shown in FIG. 7 LOAD, a signal is sent out to set the data to be sent out by the multiplexer 24.

Therefore, the transfer data amount N is set in the transfer counter 10 as shown in the transfer counter 10 in FIG. When the amount of data to be transferred is set in the transfer counter 10, the data transfer control circuit 28 sets the set value of the transfer counter 10 to 0, as shown in the transfer counter 10 of FIGS. 7 and 8.
Data transfer control is performed in the same manner as described above until .

At this time, as shown in FIGS. 6 to 8, processor 8 waits for command transfer to end, the processor 8 does not participate in the above operation after issuing the command transfer start instruction. When receiving data from the host device 1, a latch circuit 22 is used to latch the data sent by the host device 1, and a counter 29 is used to subtract "4" set by the ACK signal. The rest is the same as above, and detailed explanation will be omitted.

[0056]

As explained above, since the present invention causes hardware to execute the process of setting the data transfer amount in the transfer counter, there is no need for software processing, and the processor does not intervene in the data transfer process. The data transfer processing time of the data transfer control device can be shortened.

[Brief explanation of the drawing]

[Figure 1] Block diagram explaining the principle of the present invention

[Figure 2
] Block diagram of a circuit showing one embodiment of the present invention

[Figure 3
] Time chart explaining the operation in Figure 2 (Part 1)

[Figure 4] Time chart explaining the operation in Figure 2 (Part 2)

[Fig. 5] Block diagram of a circuit showing another embodiment of the present invention

[Figure 6] Time chart explaining the operation in Figure 5 (
Part 1)

[Figure 7] Time chart explaining the operation in Figure 5 (Part 2)

[Figure 8] Time chart explaining the operation in Figure 5 (Part 3)

[Figure 9] Block diagram illustrating an example of conventional technology

[Figure 10] Diagram explaining interface standards

[Figure 11]
Time chart explaining the operation in Figure 9 (Part 1)

[Figure 12] Time chart explaining the operation in Figure 9 (
Part 2)

[Figure 13] Time chart explaining the operation in Figure 9 (
Part 3)

[Explanation of symbols]

1 Host device 2 Disk control device 3 Drive 4 Driver/receiver 5, 22, 23 Latch circuit 6 Buffer memory 7 Drive control circuit 8 Processor 9, 25, 28 Data transfer control circuit 10 Transfer counter 11 Devices 12, 18 Data transfer device 13 , 19 Interface 14, 20 Detection means 15, 21 Setting means 16 Counting means 17 Data transfer means 24 Multiplexers 26, 27 Flip-flops 29, 30 Counter

Claims (2)

[Claims] 1. An interface (13) that operates according to an interface standard in which the amount of data to be transferred is specified by the first data block to be transferred, a counting means (16) for counting the amount of transferred data, and the counting means. The device (11) connected via the interface (13) is provided with a data transfer means (17) that stops the data transfer process when the data transfer of the amount of data specified by (16) is completed.
), the detection means (12) detects the first transferred data block.
4) and setting means (15) for setting the transfer data amount indicated by the first transferred data block to the counting means (16) based on the detection result of the detecting means (14), A data transfer control system characterized in that data transfer is started when the setting means (15) sets the transfer data amount in the counting means (16). 2. An interface (19) that operates according to an interface standard in which the amount of data to be transferred is specified in the middle of the data to be transferred, a counting means (16) for counting the amount of transferred data, and the counting means ( and a data transfer means (17) that stops the data transfer process when the data transfer of the amount of data specified by In the device (18) that performs data transfer, a detection means (20) detects a data block specifying the amount of data to be transferred, and based on the detection result of the detection means (20),
setting means (21) for setting the transfer data amount indicated by the detected data block in the counting means (16);
A data transfer control method characterized in that the data transfer is started when the setting means (21) sets the transfer data amount in the counting means (16).