JPS5667471A - Multiprocessor - Google Patents
MultiprocessorInfo
- Publication number
- JPS5667471A JPS5667471A JP14257979A JP14257979A JPS5667471A JP S5667471 A JPS5667471 A JP S5667471A JP 14257979 A JP14257979 A JP 14257979A JP 14257979 A JP14257979 A JP 14257979A JP S5667471 A JPS5667471 A JP S5667471A
- Authority
- JP
- Japan
- Prior art keywords
- address
- data
- signal line
- arbiter
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To remove restrictions on address processor PC by interrupting address PC after setting up data, which is to be transferred to address PC by source-side PC, in the prescribed area of a common memory.
CONSTITUTION: Respective PCs 5W8 have request circuits 13W16 and accepting circuits 17W20, which are connected to arbiter 21 via address signal line 22, mode signal line 23 and busy signal line 24. Further, PCs 5W8 shares common memory 25. When PC7 is to address data transmission and reception to PC5 at the source side of the data transmission and reception, PC7 sends request signal 29 to arbiter 21 via circuit 15. Then, arbiter 21 selects it and activates one of acceptance signal groups 33 so as to give the right of using signals line groups 22W24, so that a busy display signal will be sent back to PC7 via signal line 24. After storing data to be transferred in the prescribed area of memory 25, PC7 interrupts PC5 to fetch data. Thus, the restriction that address PC should be enabled to accept data at any time can be removed.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14257979A JPS5667471A (en) | 1979-11-02 | 1979-11-02 | Multiprocessor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14257979A JPS5667471A (en) | 1979-11-02 | 1979-11-02 | Multiprocessor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5667471A true JPS5667471A (en) | 1981-06-06 |
Family
ID=15318588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14257979A Pending JPS5667471A (en) | 1979-11-02 | 1979-11-02 | Multiprocessor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5667471A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6043770A (en) * | 1983-08-19 | 1985-03-08 | Fujitsu Ltd | Communication system of subprocessor unit |
JPS60229162A (en) * | 1984-04-27 | 1985-11-14 | Hitachi Ltd | Control system of multiprocessor |
JPS61239329A (en) * | 1985-04-12 | 1986-10-24 | Fujitsu Ltd | System for instructing actuation of service processor |
JPS62295165A (en) * | 1987-05-29 | 1987-12-22 | Nec Corp | Multiport ram |
-
1979
- 1979-11-02 JP JP14257979A patent/JPS5667471A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6043770A (en) * | 1983-08-19 | 1985-03-08 | Fujitsu Ltd | Communication system of subprocessor unit |
JPS60229162A (en) * | 1984-04-27 | 1985-11-14 | Hitachi Ltd | Control system of multiprocessor |
JPS61239329A (en) * | 1985-04-12 | 1986-10-24 | Fujitsu Ltd | System for instructing actuation of service processor |
JPH0464092B2 (en) * | 1985-04-12 | 1992-10-13 | Fujitsu Ltd | |
JPS62295165A (en) * | 1987-05-29 | 1987-12-22 | Nec Corp | Multiport ram |
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