JPS5687151A - Test and set system - Google Patents

Test and set system

Info

Publication number
JPS5687151A
JPS5687151A JP16398279A JP16398279A JPS5687151A JP S5687151 A JPS5687151 A JP S5687151A JP 16398279 A JP16398279 A JP 16398279A JP 16398279 A JP16398279 A JP 16398279A JP S5687151 A JPS5687151 A JP S5687151A
Authority
JP
Japan
Prior art keywords
bus
processor
common bus
common
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16398279A
Other languages
Japanese (ja)
Inventor
Takashi Tazaki
Takao Sakata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16398279A priority Critical patent/JPS5687151A/en
Publication of JPS5687151A publication Critical patent/JPS5687151A/en
Pending legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Memory System (AREA)

Abstract

PURPOSE: To occupy a common bus in readout/write-in of process control words, to avoid the occupany of an unnecessary common bus, and to increase the processing efficiency, by adding a simple control circuit to the test and set controller provided on the common bus.
CONSTITUTION: A plurality of processors 100, common memory device 200, and test and set control table device 400 are commonly connected to the address bus 501, data bus 502 and signal line 504. Further, the common bus usage request signal from the processor 100 is received, and the bus controller 300 transmitting the usage permission signal according to the priority of the processor 100 is connected to each processor 100 via the control bus 503. Further, the control table device 400 is provided with the control circuit which controls rewriting of the content of register with the write-in/readout signal from the processor 100, and the unnecesary occupancy of common bus due to the processor 100 is avoided and then processing efficiency is increased.
COPYRIGHT: (C)1981,JPO&Japio
JP16398279A 1979-12-19 1979-12-19 Test and set system Pending JPS5687151A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16398279A JPS5687151A (en) 1979-12-19 1979-12-19 Test and set system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16398279A JPS5687151A (en) 1979-12-19 1979-12-19 Test and set system

Publications (1)

Publication Number Publication Date
JPS5687151A true JPS5687151A (en) 1981-07-15

Family

ID=15784498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16398279A Pending JPS5687151A (en) 1979-12-19 1979-12-19 Test and set system

Country Status (1)

Country Link
JP (1) JPS5687151A (en)

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