JPS57153341A - Microprogram processing system - Google Patents
Microprogram processing systemInfo
- Publication number
- JPS57153341A JPS57153341A JP56040167A JP4016781A JPS57153341A JP S57153341 A JPS57153341 A JP S57153341A JP 56040167 A JP56040167 A JP 56040167A JP 4016781 A JP4016781 A JP 4016781A JP S57153341 A JPS57153341 A JP S57153341A
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- area
- transfer instruction
- byte
- designated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System (AREA)
- Executing Machine-Instructions (AREA)
Abstract
PURPOSE: To achieve high speed transfer instruction having also a copy function, by realizing the comparison of addresses without comparison of addresses directly.
CONSTITUTION: A data bus 4 connecting a memory 1, an input/output device 2, a central processing device 3 and each device, a source area 5 in L-byte started from an SA designated with a transfer instruction, and destination area 6 in L-byte started from a DA designated with the transfer instruction are provided. Further, the transfer instruction, i.e., an instruction having a function transferring a data in an arbitrary area in the memory is provided. To realize this instruction with a microprogram, the instruction is transferred to the area 6 from the SA one by one-byte and this is repeated by L times, or several bytes are transferred and the number of times of repetition is decreased for high speed transfer.
COPYRIGHT: (C)1982,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56040167A JPS57153341A (en) | 1981-03-19 | 1981-03-19 | Microprogram processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56040167A JPS57153341A (en) | 1981-03-19 | 1981-03-19 | Microprogram processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57153341A true JPS57153341A (en) | 1982-09-21 |
Family
ID=12573204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56040167A Pending JPS57153341A (en) | 1981-03-19 | 1981-03-19 | Microprogram processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57153341A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02306338A (en) * | 1989-02-03 | 1990-12-19 | Nec Corp | Microprogram controller |
JP2012507805A (en) * | 2008-11-05 | 2012-03-29 | インテル・コーポレーション | Instruction optimization performance based on sequence detection or information associated with the instruction |
-
1981
- 1981-03-19 JP JP56040167A patent/JPS57153341A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02306338A (en) * | 1989-02-03 | 1990-12-19 | Nec Corp | Microprogram controller |
JP2012507805A (en) * | 2008-11-05 | 2012-03-29 | インテル・コーポレーション | Instruction optimization performance based on sequence detection or information associated with the instruction |
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