JPH0740408B2 - Memory control circuit of PCM device - Google Patents

Description

The present invention relates to a memory control circuit of a PCM device.

[Conventional technology]

PCM that can record and reproduce audio signals without deterioration of sound quality
As a device, there is a rotary head type digital audio tape recorder (hereinafter referred to as "R-DAT").

FIG. 6 shows the relationship between the R-DAT drum and tape. (8) and (9) are magnetic heads, (22) is a drum,
(23) shows a magnetic tape, and the magnetic tape (23) is wound around the drum (22) at an angle of 90 ° for recording and reproduction.

FIG. 7 shows recording patterns recorded on the magnetic tape (23). (25a), (25b) and (25c) are recording tracks, (26) is a head scanning direction, and (27) is a magnetic tape. The traveling direction of (23) is shown. As shown in the figure, the recording track (25) is slanted with respect to the longitudinal direction of the magnetic tape (23).
Are formed to perform recording / reproduction.

Next, the configuration of the R-DAT recording / reproducing system will be described with reference to FIG.

In the figure, (1) is an input terminal, (2) is a low-pass filter, (3) is an analog-digital conversion circuit (hereinafter referred to as AD conversion circuit), (4) is a memory control circuit, (5) is an encoding circuit, (6) is a modulation circuit, (7) is a switching switch,
(10) is a switching switch, (11) is a demodulation circuit, (12) is a memory control circuit, (13) is a decoding circuit, and (14) is a digital circuit.
An analog conversion circuit (hereinafter referred to as a DA conversion circuit), (15) is a low-pass filter, (16) is an output terminal, and (17) is a clock generation circuit that generates a system clock. The low-pass filter (2), AD Conversion circuit (3), memory control circuit (4), encoding circuit (5), modulation circuit (6)
A recording system (20) is constituted by the demodulation circuit (11), memory control circuit (12), decoding circuit (13), DA conversion circuit (1).
4), the reproduction system (30) is composed of the low-pass filter (15).

Next, the operation of the recording system (20) will be described first. The analog signal to be recorded is input from the input terminal (1), the high frequency component is removed by the low-pass filter (2), and then the digital signal at a constant sampling frequency (hereinafter referred to as Fs) by the AD conversion circuit (3). (Hereinafter referred to as a sample) and stored in a memory (not shown) in the memory control circuit (4). Encoding circuit (5)
Reads the sample stored in the memory, generates a check signal for error correction and error detection, and writes it in the memory. When the encoding is completed, the sample and the check signal are time-compressed and read from the memory, converted into a signal suitable for magnetic recording / reproduction by the modulation circuit (6), and then switched by a switching switch (7). ) Via magnetic head (8) or magnetic head (9) with magnetic tape (23)
Recorded in.

FIG. 9 shows an example of the code configuration.

In the figure, the symbol indicates 8-bit data. This code is doubly encoded with C ₁ code and C ₂ code for 26 audio symbols arranged in the x direction and 28 audio symbols arranged in the y direction. The C ₁ code constitutes a Reed-Solomon code with an inter-code distance of 5 in which four P check symbols (P _{0 to} P ₃ ) are added from 28 audio symbols in the y direction. At this time, the C ₁ code of x = x ₁ is (1)
Meets the formula.

H ₁ [D (X ₁ , 0), D (x ₁ , 1) …… D (x ₁ , 27), P ₀ (x ₁ ) …… P ₃ (x ₁ )] ^T = 0 …… ( 1) Where α is the root of the primitive polynomial (x) T is the transpose of the matrix C _{2 The} code is encoded in the x direction, and the code of y = y ₁ is 6 Q check symbols that satisfy equation (2). (Q ₀ ~ Q ₅ )
Is a Reed-Solomon code with an inter-code distance of 7 added.

H ₂ = _{[D (0, y 1),} D (1, y 1), ...... D (25, y 1), Q 0 (y 1) ...... Q 5 (y 1) ] ^T = 0 ...... (2) In the audio symbol and the check symbol shown in FIG. 9, 32 symbols in the y direction are sequentially recorded as a PCM signal of 1 block, and a signal of 32 blocks is recorded in 1 track.

Fig. 10 shows the block configuration, which includes the synchronization signal (51),
36 control signals (52), block address (53), parity (54), PCM data (55)
It consists of symbol data. Block address (53)
0 to 31 against 32 blocks recorded in one track
To identify the block,
The block address of the block in which 32 symbols in the y direction located at x = x ₁ in FIG. 9 are recorded is x ₁ .

The parity (54) is generated by mod2 addition of the control data (52) and the block address (53), and is added to improve the reliability of the reproduced control data and block address. These control data (52), block address (53), and parity (54) are added by the memory circuit (4) and the synchronization signal (51) is added.
Are added by the modulation circuit (6).

Next, the operation of the reproduction system (30) will be described. The time-compressed reproduction signals from the magnetic head (8) and the magnetic head (9) are switched every unit time, and a switching switch (10).
The signal is alternately supplied to the demodulation circuit (11) via, and is restored to the signal before modulation, and stored in the memory (121) in the memory control circuit (12) shown in FIG. A decoding circuit (13) sequentially reads the reproduced signal from the memory (121) and performs error detection and error correction. The decoded audio symbol in the memory (121) is read at a constant time interval, converted into an analog signal by the DA conversion circuit (14), and then a high frequency component is removed by the low-pass filter (15) in the next stage. And output from the output terminal (16).

The clock necessary for the above signal processing is supplied from the clock generation circuit (17).

FIG. 11 is for explaining the error correction procedure in the decoding circuit (13). FIG. 11 (A) shows a reproduced signal, A1 and A2 are magnetic heads (8), and B1 is a magnetic head. In the signal reproduced in (9), when the synchronization of one rotation of the drum (22) is T, there is a signal-free section every T / 4 (a period in which the drum (22) rotates 90 °). Further, FIGS. 7B and 7C show the memory (12) in the memory control circuit (12).
1) (has the capacity to store the data contained in A1 and B1)
Is divided into first and second areas, and the contents of the processing performed in each area are shown. W is the writing of the reproduction signal,
C1D is an error correction using the C1 code (hereinafter referred to as “C1 decoding”), C2D is an error correction using the C2 code (hereinafter referred to as “C2 decoding”), and FsR is the DA conversion circuit (1
4) shows the read-out for supplying to.

In the memory first area, the signal A reproduced by the magnetic head (8) is written and read. That is, the time t ₀ ~t ₁ to the reproduction signal A1 is written, then the time t ₁
C1 decoding is performed on the reproduced signal A1 during the period from t ₂ to t ₂ . FIG. 9 shows a code structure and a memory map, and an area in the memory is designated by x (x address) and y (y address).

As shown in FIG. 9, the A1 signal taken into the memory (121) is executed from the decoding of the C1 code of x = 0, and the C1 decoding is executed 32 times until x = 31, and then the process is terminated. Then, C2 decoding is executed from time t _2, and ends at time t ₃ . The corrected audio symbol is immediately written to the original address of the memory first area, read from the memory first area during the period from time t ₃ to t ₄ , and supplied to the DA conversion circuit (14).

On the other hand, in the memory second area, the same operation as in the first area is performed on the signal B reproduced by the magnetic head (9), so that the audio symbol supplied to the DA conversion circuit (14) is T / 2. Continuous audio reproduction is performed by switching and reading the memory area for each period.

FIG. 12 shows a memory and a memory address control circuit in the memory control circuit (12).
2) is a selector, (123) is an address detection circuit, (124)
Is a write / decode address generation circuit (hereinafter simply referred to as “address generation circuit”), (127) is an AND gate, (12
8) demodulates the reproduced signal in the demodulation circuit (11) and then the bus (1
An input terminal of a first write clock for writing for writing to a memory (121) via (1a), (12
9) is the demodulation circuit (13) where the error symbol in the memory (121) is
2 shows the input terminal of the second write clock for writing again to the memory (121) via the bus (13a) after the error correction has been performed by the first write clock and the selector (122). ), An address generation circuit (124),
(125) The clock necessary for the operation of the address detection circuit (123) is supplied from the clock generation circuit (17) shown in FIG.

Next, the operation of the memory control circuit (12) will be described with reference to FIGS. 9 and 11.

The demodulated reproduction signal is transmitted from the time t ₀ to t via the bus (11a).
_{During 1 it} is written to the memory (121). At this time, the address generation circuit (124) generates the first address (124a) indicating the values of the x address and the y address shown in FIG. 9, and supplies the first address (124a) to the memory (121) via the selector (122). . The address detection circuit (123) detects the block address from the demodulated data. It performs a parity check to add control data, block address and parity in mode 2. If the check result is "0", the block address (123a) Is output together with the road clock (12
3b) is output, and if the result is "1", it is determined that there is an error and the load clock (123b) is not output. Using this as an input, the address generation circuit (124) loads a block address into a counter (not shown) in the address generation circuit (124) by a load clock. The x address shown in FIG. 9 is supplied to the memory (121) by the loaded block address. On the other hand, for the y address, the counter in the address generation circuit (124) is updated by the symbol clock output from the clock generation circuit (17) for each symbol arranged in the block, and the memory (12
Supplied to 1). As described above, the write address of the reproduction signal is designated and the data from the block address 0 to the block address 31 are sequentially written in the period of t ₀ to t ₁ . While controlling the memory (121) by the address generating circuit 1 (124) from time t _1, C1 decoded from x-address 0 is started terminated at time t _2, C2 decoding a period of time t ₂ ~t ₃ Is executed. Address generation circuit (125) from time t ₃ to t ₄
Memory (121) by the address (125a) given by
The corrected data is sequentially read out and supplied to the DA conversion circuit (14). The first area and the second area of the memory (121) have the same address generation circuit (124), (12
5) is shared and is controlled by the address given in time division by the selector (122).

[Problems to be solved by the invention]

As described above, since C1 decoding and C decoding are processed in the section where there is no reproduction signal, it is possible to share the address generation circuit 1 (124) to perform reproduction signal writing and memory control at the time of decoding. This has the advantage of simplifying the configuration of the address generation circuit. However, the time that can be used for decoding is limited to the period when there is no reproduced signal. Therefore, if complex calculations are performed to obtain high correction capability, the clock rate of the calculations will increase, and when ICs are used, the power consumption will increase. There was a problem that inconvenience occurred.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a memory control circuit of a PCM device that can secure an operation time without increasing the clock rate.

[Means for solving problems]

The memory control circuit of the PCM device according to the present invention uses a plurality of data as one block for each memory block for writing the received data to which the redundant code for error correction or error detection is added. A write address generation circuit that generates based on the added address signal, a memory that writes the received data at this write address, and the write data that is sequentially read from this memory to perform error correction or error detection in the decoding circuit. After that, a decoded address generation circuit for generating a decoded address for writing again in the memory, a judgment means for discriminating whether or not the write address belongs to a memory area which has already been decoded, and a judgment result When the determination is made, the memory is provided with means for prohibiting writing of the received data. It is.

[Action]

According to the present invention, the write address generation circuit for generating the memory address for writing the received data and the decoded address generation circuit for generating the decoded address for performing the error correction or the error detection and then writing the data again in the memory are separately provided. Since it is provided, it is possible to start decoding regardless of the presence or absence of received data. In other words, since it is possible to start decoding from a certain section of received data, the calculation time for decoding Can be sufficiently long, and even if complex calculations are performed to obtain high correction capability, the clock rate of the calculations need not be increased. In addition, it is possible to discriminate whether or not the write address belongs to the memory area that has already been decrypted, and if so, it is possible to prohibit the writing of the received data, so that the correct data is placed in the wrong data. The inconvenience of changing does not occur.

Example of Invention

FIG. 1 is a block diagram showing the construction of an embodiment of the present invention.

In the figure, (130) is a write address generation circuit for generating a memory address for writing a reproduction signal which is an example of received data into the memory (121), (130a) is an address output supplied to the memory (121), and (130b ) Is an x address output at the time of writing, (131) is a decoded address generation circuit for generating a decoded address for writing again in the memory (121) at the time of decoding, (131a) is an address output supplied to the memory (121), (130b ) Is an x-address output of the memory area currently being decoded, and (132) is an address comparison circuit which constitutes an address determination means, and both address generation circuits (13
0) and (131) are compared with each other, and when the x address (130b) is larger than the x address (131b), "0" is output, and otherwise, "1" is output. Reference numeral (133) is an OR gate, and the other constituent parts denoted by the same reference numerals as those in FIG. 12 respectively indicate the same constituent parts.

Next, the operation of this embodiment will be described with reference to FIG. 2 and FIG.

The reproduction signal A1 is written in the first area of the memory (121) by the address output (130a) generated in the write address generation circuit (130) during the period from time t _{0 to} t ₁₂ . This operation is the same as the operation of the address generation circuit (124) shown in FIG. 12 at the time of writing the reproduction signal.

On the other hand, C1 decoding starts at time t ₁₁ shown in FIG. It will be described with reference to FIG. 3 the operation of the memory the first region at a time t _17. FIG. 3 shows data excluding the synchronization signal, and only PCM data is stored in the memory (121). At time t ₁₇ , C1 decoding for x addresses 0 to 2 is completed, and C1 decoding for x address 3 indicated by arrow S is performed. On the other hand, regarding the writing of the reproduction signal, the data writing to the block addresses 0 to 10 is completed, and the data of the block address 11 indicated by the arrow T is about to be written. If an error occurs in the reproduced signal and the control data, block address, and parity all become "0", the parity check result becomes "0" and the block address is incorrect, but the address detection circuit (123) Then, the block address (123a) and the road clock (123a)
Since b) is output, the data that should originally be written in the area of x address 11 is written in x address 0. However, the data at the block address 0 has already been C1 decoded, and if the data at the block address 11 is written here, all 32 symbols of the 0 block will be missed errors and the performance of the C2 decoding at the next stage will be deteriorated, or the ear will lose. There may be noise associated with the noise.

The address comparison circuit (132) is provided to prevent this, and compares the x address (131b) for which decoding is being performed with the reproduction signal writing x address (130b), and reproduces the reproduction signal writing x address (130b). Is smaller than the x address (131b), "1" is output and the OR gate (140) is closed to prevent the write clock (128a) from being supplied to the memory (121). As a result, at the time t ₁₇ , the data of the block address 11 is not taken into the memory (121) and the data of the block 0 remains as it is. In addition, by providing a register for storing a flag corresponding to the x address, initializing "1", and resetting the register corresponding to the x address of the written memory area, the x address of the unwritten memory area is reset. Since "1" remains in the register corresponding to, by using this flag in C2 decoding starting from time t ₁₂ , C2
It is possible to take full advantage of the code and take measures to prevent noise.

In the above embodiment, the data shown in FIG. 9 is an example in which 32 symbols constituting the C1 code in the y direction are transmitted as one block of PCM data, but 32 symbols are selected from n C1 codes. The fourth case is when one block of PCM data is used.
This will be described below with reference to FIGS.

4 and 5 show the case where n = 2.

In FIG. 4, y of the C1 code at x = 0 and x = 1 respectively
= 0 to 15 16 symbols, 32 symbols in total, y = 16 to 31
One block of PCM data is made up of 32 symbols and transmitted sequentially in the order shown by the arrows. As shown in FIG. 5, x = 2n
And from the C1 code of x = 2n + 1 (n = 0,1, ... …… 15) to the 2n,
Making 2nd + 1 block PCM data. In this case, as is clear from FIG. 4, since the reproduction / writing is performed as shown by the arrow, the block addresses 2n and (2n + 1) of the reproduction signal straddle two C1 areas on the memory. X address for writing (2n +
1) -1 is executed when -1 is smaller than the decoded x address. In addition, with a margin (reproduction / write x address-
The reliability is improved by prohibiting when α) is smaller than the decoded x address.

In the above embodiment, the memories are arranged two-dimensionally and controlled by the addresses of x and y, and writing and decoding of the reproduction signal are started from x = 0. However, when starting from x = 31, the writing x address is Even if the writing is prohibited when the address is larger than the x address for decoding, the same effect can be obtained.

Even in the case of control other than the control in which the memory address is separated into x and y, the detection means for detecting the area where the decoding is already completed and the memory area where the reproduction signal is about to be written are outside the area where the decoding is completed. A similar effect can be obtained by providing a judging means for judging that there is such a thing and controlling the writing of the reproduction signal by the judging means. Further, although only the x address is compared, the same effect can be obtained by using the y address comparison together.

〔The invention's effect〕

As described above, according to the present invention, the write address generation circuit for generating the memory address for writing the received data and the decoded address generation for generating the decoded address for performing the error correction or the error detection and the rewriting to the memory. Since the circuit and the circuit are separately provided, it is possible to arbitrarily start the decoding even from a certain section of the received data, so that the operation time for the decoding can be sufficiently long. Therefore, it is possible to perform high-correction performance by performing complex calculations, but it is not necessary to increase the clock rate of the calculations, and it is possible to avoid inconveniences such as an increase in power consumption when integrated into an IC. Moreover, it is possible to discriminate whether or not the write address belongs to the memory area that has already been decoded, and if it belongs, it is possible to prohibit the writing of the received data, so the correct data after decoding is incorrect. It is possible to eliminate the inconvenience of being replaced with data.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of a memory control circuit which is an essential part of one embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of this embodiment, and FIG. 3 is also this embodiment. 4 is a memory diagram for explaining the operation of FIG. 4, FIG. 4 is a signal configuration diagram of another embodiment of the present invention, FIG. 5 is a general signal configuration diagram of the signal configuration shown in FIG. 4, and FIG. FIG. 7 is a diagram showing a positional relationship between a rotary drum and a magnetic tape of a rotary head type digital audio tape recorder which is an example of an object to which the present invention is applied, FIG. 7 is a pattern diagram showing a recording pattern of the magnetic tape, and FIG. 8 is a rotary head type. A block diagram showing the structure of the PCM recording system and reproducing system of the digital audio tape recorder, FIG. 9 is its code structure diagram, FIG. 10 is its specific block structure diagram, and FIG. 11 is a time chart showing the conventional signal processing procedure. Chart, 12th Is a block diagram of a conventional memory control circuit. (12) …… Memory control circuit, (121) …… Memory, (12
2) …… Selector, (123) …… Address detection circuit, (12
5) …… Read address generation circuit, (127) …… AND gate, (130) …… Write address generation circuit, (13
1) ... Decoded address generation circuit, (132) ... Address comparison circuit, (133) ... OR gate. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A memory address for writing received data, to which a redundant code for error correction or error detection is added, is used as one block of a plurality of data, and an address signal added to each block is also included. And a write address generation circuit that generates the received data at the write address, and the write data is sequentially read from the memory, the decoding circuit performs error correction or error detection, and then is written again to the memory. A decoding address generating circuit for generating a decoding address for determining whether the write address belongs to a memory area for which decoding has already been completed, and receiving to the memory when it judges that the writing address belongs according to the judgment result. A memory control circuit of a PCM device having means for inhibiting writing of data. 2. A memory control circuit for a PCM device according to claim 1, wherein said judging means comprises a comparison circuit for comparing a write address and a decoded address.