JPS58125210A - Device for producing memory address information signal - Google Patents

Abstract

PURPOSE:To improve the efficiency of application for a memory of a memory address producing circuit that produces a reading address which varies in accordance with a prescribed rule, by combining four numerical information producing circuits. CONSTITUTION:The output of a WP counter 8 to which clocks CL4 and CL2 are supplied is fed to a full adder 9 along with the output of a WOA producer 10 to which a clock CL1 is supplied. At the same time, the output of an ROA producer 12 to which a clock CL3 is supplied and the output of the adder 9 are supplied to a signal selecting circuit 11 which is controlled by an READ/ WRITE mode switch control signal. Then the output of an HA counter 14 to which a selected output and the CL4 are supplied is supplied to a full adder 13. In such a way, the application efficiency of a memory can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory address information signal generating device that generates address information signals corresponding to read addresses and write addresses that change regularly and independently of each other and supplies them to a memory.

For example, P
CM (Palge Code Modtlat@o
n) In the recording/reproducing power type, an error correction code is added and interleaving is performed to facilitate correction of burst code errors occurring on the recording medium. For this reason, the code string read from the recording medium is such that the sequence order has been changed on the time axis based on a predetermined agreement.
During playback, it is necessary to perform so-called de-interleaving to return the code string to its original arrangement. This de-interleaving is performed, for example, by controlling the address of the buffer memory so that the code strings read from the recording medium are sequentially written into the buffer memory from the first address in the order in which they were read, and then the written code strings are returned to the original arrangement. This is done by reading the data while doing so. In such a case, when writing a code string to the buffer memory, a write address is generated that regularly increases by 1, and when reading the code string from the buffer memory, the arrangement of the code string is changed according to a predetermined rule so as to return to the original arrangement. A memory address information signal generator is often used that generates a read address that corresponds to the read address. Such a memory address information signal generating device detects the occurrence of memory overflow and underflow, and detects the amount of jitter margin according to the difference between a write address and a read address in order to prevent the occurrence of these overflows and underflows. It is desirable to have a configuration that can be easily implemented and furthermore, can easily accommodate changes in the interleap size.

Memory overflow is a phenomenon in which the number of write addresses increases abnormally, causing new data to be written to a location where previously written data has not yet been read. Underflow is a phenomenon in which the read address increases abnormally and erroneous data is read from a location where new data has not been written.

A conventional example of a memory address information signal generating device constructed as described above is shown in FIG. In FIG. 1, 1 is a WL (lower address for writing) counter of the 1 bit. W
A timing pulse generator (not shown) outputs a clock input terminal of the L counter 1 every time a predetermined number of pinpoints of data forming a code string are written into a buffer memory (not shown) for deinterleaving. WRITE data clock CLI is supplied. The count value of this WL counter 1 is increased by 1 in response to the clock CLI, and the count value of the WL counter 1 returns to zero when the same number of clock CLIs as the number of data forming one frame are generated. Also, the output of WL counter 1 forms the lower m bits of the write address and (%-In) bits of W
It is supplied to one input terminal group of the signal selection circuit 3 together with the output of the H (higher address for writing) counter 2 . lol
A clock input terminal of the H counter 2 is supplied with a WRITE frame clock CL2 outputted from a timing pulse generator every time data for one frame is written into the buffer memory. The output of the wH counter 2 forms the upper (?1-rn) pino)1 of the write address. The control input terminal of the signal selection circuit 3 receives a mode switching control signal READ/WRIT for setting the buffer memory to either write mode or read mode.
E is supplied. - When the data written in the buffer memory is read out from the buffer memory, the timing is changed.
The output signal CL3 is supplied to the clock input terminal of the BL (lower address for reading) counter 4 of the first bit. This RL counter 41! , the same number of clocks CL as the number of data forming one frame, similar to WL counter 1.
When 3 occurs, the count value returns to zero. R
1. The output of the counter 4 forms the lower m bits of the read address and is supplied to a group of other input terminals of the signal selection circuit 3, and is also supplied to m address input terminals of a ROM (read-only memory) 5. Ru. R in ROM 5
The storage location designated by the output of the L counter 4 stores (s--) focus data for canceling interleaving. The output of this ROM 5 is the full adder 6
It is added to the output of the (n-m) bit Ru (higher address for outputting a) counter 7. The clock input terminal of the RH counter is supplied with a READ frame clock CL4 outputted from a timing pulse generator every time data for one frame is read from the buffer memory. The output of the full adder 6 forms the upper (n-m) bits of the read address and is supplied to the other input terminals of the signal selection circuit 3 together with the output of the counter RL. Then, this signal selection circuit 3 receives a switching control signal R.
EAD/WRITE outputs an address information signal corresponding to one of the n-bit read address and write address, thereby controlling the address of the buffer memory for deinterleap.

In this case, overflow and underflow detection is w
The value of H counter 2 and the upper (n) of the memory read address
-m) This is possible by detecting the coincidence of the bit values, but detecting the sinter margin requires a distance detection circuit (for example, a subtraction circuit) between the RH counter 7 and the wH counter 2, and the memory Unused portions occur, resulting in poor memory usage efficiency. Eliminating unused portions to increase memory usage efficiency results in overflow and under 70-
The disadvantage was that it was difficult to detect.

Therefore, an object of the present invention is to easily detect the occurrence of memory overflow, underflow, and jitter margin amount, and to improve memory usage efficiency with a configuration that can easily accommodate changes in interleave length. An object of the present invention is to provide a memory address information signal generation device that can generate a memory address information signal.

A memory address information signal generation device according to the present invention includes a first numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes according to a first predetermined rule each time data is written to the memory, and a first numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes according to a first predetermined rule each time data is written to the memory. a second numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes according to a second predetermined rule each time the first predetermined number of data is read from the memory; a third numerical information signal generation circuit that generates all the signals according to the signal; and a third numerical information signal generating circuit that changes by a third predetermined number each time a first predetermined number of data is read from the memory or a first predetermined number of data is written to the memory. a fourth numerical information signal generation circuit that generates a signal corresponding to a numerical value; A signal corresponding to the addition result of the numerical values represented by each output of the third and fourth numerical information signal generation circuits is outputted as a write address information signal, and
A signal corresponding to the result of addition of numerical values represented by each output of the numerical information signal generation circuit will be described in detail with reference to it as a read address information signal.

In FIG. 2, 8 is a wp (write position) counter as a fourth numerical information signal generating circuit. The wp counter 8 is composed of, for example, a q-bit presettable binary counter.

Countdown clock input terminal D of wp counter 8
READ frame clock CL4 and WRIT are connected to the OWN and count-up clock input terminals UP, respectively.
Each of the E frame clocks CL2 is supplied. Further, the preset command input terminal PR of the wP counter 8 is supplied with an initial setting recent signal generated, for example, when the power is turned on. The output of the wp counter 8 is supplied as an addend to an S-bit full adder 9. This full adder 9 has W as a first numerical information signal generation circuit.
The output of OA (WRITE off-cent address generator 1o is supplied as the summand power. WOA generator 1
0 is supplied with the WRITE data clock CLI. This WOA generator 10 includes, for example, a binary counter whose count value changes according to a clock CLI, and a ROM in which the output of this counter is supplied as an address input and the data of r pinto is stored in a memory location specified by the output of the counter. It consists of The output of the full adder 9 is supplied to a group of input terminals of a signal selection circuit 11. A control input terminal of the signal selection circuit 11 is supplied with the output of an ROA (READ offset address) generator 12 as a mode switching control signal READ path. R.O.
The A generator 12 is supplied with a READ data clock CL3.

This ROA generator 12 includes, for example, a binary counter whose count value changes according to a clock CL3, and the output of this counter is supplied as an address input, and t-bit data is stored in a memory location designated by the output of the counter to cancel interleaving. It is composed of a ROM that stores . The signal selection circuit 11 receives a mode switching control signal RE.
The output of full adder 9 and ROA according to AD/WRITE
One of the outputs of the generator 12 is selectively output. The output of this signal selection circuit 11 is supplied to an n-bit full adder 13 as an addend input. Full adder 13
is supplied with the output of an HA (home address) counter 14 as a third numerical information signal generating circuit as a summand. The HA counter 14 is, for example, a U-focus binary counter. The clock input terminal of this HA counter 14 has a READ frame clock CL4.
is supplied. The output of the full adder 13 is then supplied as an address input to a buffer memory for deinterleaving (not shown).

In the above configuration, the mode switching control signal READ/W
When the buffer memory enters the read mode by RITE and the output of the ROA generator 12 is selectively output from the signal selection circuit 11, the value R representing the output of the ROA generator 12 is
Numerical value HAi represented by OAi and the output of the HA counter 14
The full adder 13 outputs a signal corresponding to the read address RMA i obtained by adding f. Further, when the mode switching control signal READ/WRITE is applied, the output of the full adder 9 is selectively outputted from the signal selection circuit 11 when the output memory enters the write mode, and the numerical value WPi and WOA represented by the output of the wp counter 8 are generated. The full adder 13 outputs a signal corresponding to the write address WMAi obtained by adding the numerical value WOAi represented by the output of the adder 10 and the numerical value HA<. Therefore, the number of data in one frame k ND
When I interleaving length fd and jitter margin are M, each of the numerical values ROAj and WOAi is the first
The ROA generator 1 varies as shown in Table and Table 2.
2 and the ROM in the WOA generator 10 in advance, and the precent value of the wp counter 8 is (M+1).
By doing so, the minimum storage capacity Qmin required as a buffer memory for de-incleaving becomes as shown in the following equation, and the buffer memory can be used efficiently.

ND For example, Np=4. d=3. If M=2, then Q,
7. =4 (2+1)+3 (1+2+3+4)=
42 data, and deinterleaving can be performed using a buffer memory having a storage capacity of 42 data. That is, in such a case, full adder 1
3 is like 42 is o, 43 is 1 (the way it comes out, the numerical value HAj,
ROAj, WOAi, WPj, read address RMAj, and write address WMAi change as shown in Table 3. Here, the read position and write position specified by the read address RMAi and the write address wMAi will be explained with reference to FIG.

In FIG. 3, the read addresses specifying the read position of one frame's worth of data are RMA, , RM, respectively.
A2. RMA3. A memory map obtained by dividing the buffer memories 'iRMA1 to RMA4 into four blocks each having a leading address when RMA4 is set, and then arranging each block in parallel with each other so that the last ends are lined up horizontally is shown. In this memory map, the writing positions of one frame's worth of data are arranged horizontally in a line within the writing area EW. That is, 1
If the write address that specifies the write position of one frame's worth of data is wMA11wMA22wMA31wMA4, then for example, the write address of the first frame's worth of data in Table 3 is WMA1 = 12 = R.
MA1+12.

WMA2=24=RMA2+9, WMA3=33=R
MA3+6.

WMA4=39=RMA4+3, as shown in FIG.

Now, if only data for one frame is read, H
The count value of the A counter 14 increases by one, and the count value of the wp counter 8 decreases by one.

In this case, the write area EW moves backward by one address, but the write position does not change, so the distance between the write position and the read area ER becomes smaller. As shown in Table 4, when the number of read data becomes larger than the number of written data and WPi becomes 0, the read address RMAi becomes equal to the write address wMhi, and an underflow occurs.

Furthermore, when only data for one frame is written, WPj increases by one. In this case, the writing area EW does not move, but only the writing position moves due to the release force, and the distance between the writing position and the reading area ER changes. Then, as shown in Table 5, when the number of write data becomes larger than the number of read data and WPi becomes 6, the read address RMA i becomes equal to the write address WPi and an overflow occurs.

Therefore, when the count value of the WP counter 8 is 3, the jitter margin M is as shown in FIG. Therefore, it is important to easily detect the occurrence of overflow and underflow and the amount of jitter margin using only the count value of the wp counter 8. Okay, data read address RMA1 to RMA4 and write address WM
Since addresses A1 to WMA4 change by one address each time a frame changes, there is no unused space in the buffer memory, which improves memory usage efficiency. Furthermore, if the number of data ND in one frame increases, the storage capacity of the ROM in the WOA generator 1o and the ROA generator 12 may be increased, and if the interleap length d is changed, the WOA generator 10 and the data written in advance to the ROM in the ROA generator 12 (Also, if you want to increase the jitter margin M, you only need to increase the bit number of the wp counter 8, so it is possible to use a PCM recording/playback system etc. This makes it easier to respond to system expansion.

For example, ND-6, d=5. When M=3, it can be changed to generate RMAj and WMAj as shown in Table 6 to easily cope with system expansion.

In addition, the minimum storage capacity required for the buffer memory in this case is 6x (3+1)+5 (1+2-4-3-1-
4-1-5+6)=129, and the full adder 13 outputs 129 as 0 and 130 as 1. Also, RM
The read position and write position specified by Ai and WMAi are shown in FIG. 5 in the same manner as in FIG. 3. In FIG. 5, a numerical value indicating an address is attached to each storage location of the buffer memory so that the reading and writing positions of each data of the first frame in Table 6 can be easily understood.

As described in detail above, the memory address information signal generation device according to the present invention is capable of detecting memory overflow.

The structure allows for easy detection of the occurrence of underflow and the amount of jitter margin, as well as for easily responding to changes in interleap length, and also improves memory usage efficiency, making it ideal for digital audio equipment. A memory control device for deinterleaving memory in [two-phase is preferred.

Table 1 Table 2

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a conventional memory address information signal generating device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional memory address information signal generating device. When d=3 and M=2, the memory map of the buffer memory which uses the output of the device shown in FIG. 2 as the address input is shown. FIG. 4 shows the count value of the wp counter 8 and the jitter margin in the device shown in FIG. Figure 5 shows the relationship between ND=6, d=5, M
3 is a diagram showing a memory map of a buffer memory in which the output of the device of FIG. 2 is used as an address input when 3. Explanation of codes of main parts 8... wp counter 9, 13... full adder 1
0...WOA generator 11...Signal selection circuit 12-ROA generator 14...
...HA Counter Applicant Pioneer Co., Ltd. Agent Patent Attorney Hajime Fujimura Hikokan, 1 Figure Qin 3 (21 r ------------------------1■ Akebono L4 [21 Seed 5 Non-56 ■

Claims (1)

[Claims] A memory address information signal generating device that generates address information signals corresponding to read addresses and write addresses that change regularly and independently of each other and supplies them to a memory, each time data is written to the memory. 1st P
a first numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes according to a predetermined rule; and a second numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes according to a second predetermined rule each time data is read from the memory. a numerical information signal generation circuit;
a third numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes by a second predetermined number each time a first predetermined number of data are read from the memory; or the data is stored in the first memory.
a fourth numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes by a third predetermined number every time a predetermined number of information is written; A signal corresponding to the addition result of the numerical values represented by each output of the third and fourth numerical information signal generation circuits is output as write address information, and the addition result of the numerical values represented by each output of the second and fourth numerical information signal generation circuits is output. A memory address information signal generating device characterized in that it outputs a signal corresponding to a read address information signal as a read address information signal.