JPS58139385A - Information signal generator for memory address - Google Patents

Abstract

PURPOSE:To improve the efficiency of use of memories, by providing the 1st, the 2nd and the 3rd numerical information signal generating circuit, and outputting a write address signal in response to the result of summation of numerals of each output of the 1st, the 2nd, and the 3rd circuits and a readout signal with the result of summation of the 1st and the 2nd circuits. CONSTITUTION:At the readout mode, the output of a relative address generating circuit 8 as the 1st numeral information generating circuit and of an absolute address generating circuit 12 as the 2nd numeral information generating circuit is added at a full adder and a signal in response to the readout address is outputted from a full adder 13. At the write mode, the outputs of the circuits 8, 12 and of a presettable up/down counter 15 as the 3rd numerical information generating circuit are full-added and a signal in response to the write address signal is outputted from the full adder 13. Thus, the detection of the generation of overflow/underflow of the memory and the amount of jitter margin is made easy, to improve the efficiency of use of memory.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory address information signal generating device that generates address information signals corresponding to read addresses and write addresses that change regularly and independently of each other and supplies them to a memory.

For example, P
CM (Pa1.?y Codg Modyblation
rL) In the recording and reproducing system, interleaving is performed along with addition of an error correction code in order to facilitate correction of burst code errors occurring on the recording medium.

For this reason, the sequence of code strings read from a recording medium is changed on the time axis based on a predetermined agreement, and when played back, a so-called process that returns the code string to its original arrangement occurs. It is necessary to interleave. This deinterleaving is performed, for example, by sequentially writing code strings read from a recording medium into the buffer memory in the order in which they were read, starting from the first address, and then controlling the address of the buffer memory so that the written code strings are returned to their original arrangement. This is done by reading the data while doing so. In such a case, when writing a code string to the buffer memory, a write address is generated that regularly increases by 1, and when reading the code string from the buffer memory, the arrangement of the code string is changed according to a predetermined rule so as to return to the original arrangement. A memory address information signal generator is often used that generates a read address that corresponds to the read address. Such a memory address information signal generating device detects the occurrence of memory overflow and underflow, and detects the amount of knock margin according to the difference between the write address and the read address to prevent the occurrence of these overflows and underflows. It is desirable to have a configuration that can be easily implemented, can easily accommodate changes in interleave size, and is suitable for use as an IC (integral circuit). Memory overflow is a phenomenon in which the number of write addresses increases abnormally, causing new data to be written to a location where previously written data has not yet been read. Underflow is a phenomenon in which the number of read addresses increases abnormally and erroneous data is read from a location where no new data has been written.

A conventional example of a memory address information signal generating device constructed as described above is shown in FIG. In FIG. 1, 1 is an m-bit WL (lower address for writing) counter. W
A timing pulse generator (not shown) outputs a clock input terminal of the L counter 1 every time a predetermined number of bits of data forming a code string are written into a buffer memory (not shown) for de-interleaving. A WRITE data clock CLl is supplied. The count value of this WL counter 1 is incremented by 1 in response to the clock CLl, and the count value of the wL counter 1 returns to zero when the same number of clocks CL1 as the number of data forming 1 frame is generated. In addition, the output of the WL counter l forms the lower m bits of the write address and (n-m) bits of WH
(Upper address for writing) It is supplied to one input terminal group of the signal selection circuit 3 together with the output of the counter 2. W.H.
The clock input terminal of the counter 2 is supplied with a WRITE frame clock CL2 outputted from a pulse generator at timing every time data for one frame is written into the buffer memory. The output of WH counter 2 forms the upper (rL--) bits of the write address. The control input terminal of the signal selection circuit 3 is supplied with a mode switching control signal rule /wRITE for setting the buffer memory in either the write mode or the read mode. On the other hand, when the data written in the loga memory is read out from the buffer memory, the RJDAD data clock CL3 is output from the timing pulse generator, and the m-bit town (lower address for reading 9 addresses) counter 4 is outputted from the timing pulse generator.
is supplied to the clock input terminal of Similar to the WL counter 1, this RLi counter 4 is also configured such that its count value returns to zero when the same number of clocks CL3 as the number of data forming one frame is generated. The output of the RL counter 4 is sent to the signal selection circuit 3 while forming the lower m bits of the read address.
is supplied to the other input terminal group of the ROM (read-only memory) 5, and m address input terminals of the ROM (read-only memory) 5. The memory location designated by the output of the RL counter 4 in the ROM 5K stores (n-m) bits of data for canceling the ink IJ-b. The output of this ROM 5 is sent to the full adder 6 (rL-rIL)
It is added to the output of the bit RH (read upper address) counter 7. The clock input terminal of the RH counter receives the pseudo data D output from the timing pulse generator every time data for one frame is read from the buffer memory.
A frame clock CL4 is supplied. Full adder 6
The output of is supplied to the other input terminal group of the signal selection circuit 3 together with the output of the counter 'FLL, forming the upper (nm) bits of the read address. Then, this signal selection circuit 3 selects the switching control signals R, EAD /WRI TE
By outputting an address information signal corresponding to one of the L-bit read address and write address, address control of the buffer memory for side interleap is performed.

In this case, overflow and underflow detection is performed by W
The value of H counter 2 and the upper memory read address (n-
m) This is possible by detecting the coincidence of bit values, but the notter margin can be detected by using the RH counter 7 and the WH counter.
Not only is a distance detection circuit (for example, a subtraction circuit) with counter 2 required, but an unused portion of the memory is generated, resulting in poor memory usage efficiency. , there was a drawback that it was difficult to detect underflow, etc.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to easily detect the occurrence of memory overflows and underflows and to detect the amount of jitter margin, and to easily adapt to changes in interleave length, thereby providing a configuration suitable for use in a cache IC. An object of the present invention is to provide a memory address information signal generation device that can improve memory usage efficiency.

The memory address information signal generating device according to the present invention generates a signal corresponding to a numerical value that changes according to a first predetermined rule every time data is written to the memory, and when data is read from the memory. a first numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes according to a second predetermined rule each time data is read;
A numeric value that changes by a third predetermined number each time a first predetermined number of data is read from the memory, or a second predetermined number of data is read from the memory, or a third predetermined number is written each time a first predetermined number of data is written to the memory. a third numerical information signal generation circuit for generating a signal; Each output of the second and third numerical information signal generation circuits outputs a signal corresponding to the result of addition of the generated numerical values as a write address information signal, and the numerical values represented by the respective outputs of the first and second numerical information signal generation circuits are added. The configuration is such that a signal corresponding to the result is output as a read address information signal.

Hereinafter, the present invention will be explained in detail with reference to FIGS. 2 to 5.

In FIG. 2, the mode switching control signal READ/WFL
ITE, read data number signal DR, and write data number signal DW are supplied to a relative address generator 8 as a first numerical information signal generation circuit. Read data number signal DB
is, for example, a q-bit counter (not shown) that counts up by 1 each time data is read from a deinterleaving buffer memory, and returns to zero when data for one frame has been read. This is the signal that is output. In addition, the write data count signal is, for example, a q-bit counter that counts up by l each time data is written to a buffer memory for deinterleaving, and returns to zero when data for l frames have been written. (not shown). In the relative address generator 8, these read data number signals DR
and the write data number signal 1)W are respectively supplied to each of the two input terminal groups of the signal selection circuit 90. The control input terminal of the signal selection circuit 9 receives the mode switching control signal 肚劫/
WRITE is supplied. The signal selection circuit 9 selectively outputs either the read data number signal DR or the write data number signal BET in response to the mode switching control signal READ/WRITE. The output of this signal selection circuit 9 is used as an address input in ROM (read-only memory).
10 is supplied. The most significant address bit input terminal of this ROM10 is the mode switching signal RF, I mountain/W.
RITE is supplied. Then, r-bit data is stored in each storage location in the ROM 10 designated by the output of the signal selection circuit 9 and the mode switching control signal READ/WRITE.

The output of ROM to is added to the output of an absolute address generator 12 as a second numerical information signal generating circuit in an S-bit full adder 11. The absolute address generator 12 is
For example, it consists of a t-pit binary counter. A READ frame clock CL4 is supplied to the count-up clock input terminal UP of the absolute address generator 12. The output of the full adder 11 is supplied as an addend to the full adder 13 of the bit bit. The output of the signal selection circuit 14 is supplied to the full adder 13 as an addend input. One group of input terminals of the signal selection circuit 14 is grounded, and the other group of input terminals is connected to a W-bit Grisetta Blue Azzodown signal as a third numerical information signal generation circuit.
The output of counter 15 is supplied. The control input terminal of this signal selection circuit 14 receives a mode switching control signal READ.
/wRITE is supplied, and the signal selection circuit 14 selects one of the outputs of the counter 15 according to the mode switching control signals R, EIJ peak /WRITE, and the signal corresponding to the U-bit binary data whose all bits are zero. Selectively output either one. Column clock C of counter 15
Each of the L4 and RITE frame clocks CL2 are supplied. At the preset command input terminal PR of the counter 15, an initialization reset signal generated, for example, when the power is turned on, is outputted to the address of the supply interleaving buffer memory.

In the above configuration, the mode switching control signal FLEAD/
When the buffer memory is in the read mode by ITg, the read data number signal DB and the W-bit binary data signal whose all pits are zero are selectively selected from each of the signal selection circuits 9 and 14. When the signal is output to the full adder 13, a signal corresponding to the read address RMAL obtained by adding the numerical value ROAt represented by the output of the relative address generator 8 and the numerical value HILi represented by the output of the absolute address generator 12 at this time is outputted to the full adder 13. It will be outputted.

In addition, the buffer memory is set to the write mode by /wRITE of the mode switching control signal RBA, and the write data number signal and the counter 1 are output from each of the signal selection circuits 9 and 14.
When each of the outputs of 5 is selectively output, the write address obtained by adding the numerical value WOki represented by the output of the relative address generator 8 at this time, the numerical value WPi represented by the output of the numerical value lock and the counter 15. A signal corresponding to VMki is output from the full adder 13.

For this reason, ■ the number of data in a frame is ND1, the interleave length is d1, the jitter margin is M, and the numerical ROA
If data is written in the RAM 10 in advance so that each of i and wOAi changes as shown in Tables 1 and 2, and the preset value of the counter 15 becomes (M+l), the buffer memory for deinterleaving is As a result, the minimum required storage capacity QrrLLn becomes as shown in the following equation, and the buffer memory can be used efficiently.

For example, ND=4. d=3. If M=2, QrI
LLn=4(2+1)+3(1+2+3+4)=4
2, and deinterleaving can be performed using a buffer memory having a storage capacity of 42 data. That is, in such a case, the full adder 13
outputs 42 as 0, 43 as 1, and the numerical value 1IAi,
ROAi, ViOAi, wPi and readout space v'BMki.

The write address 'WMlyi changes as shown in Table 3. Here, the read position and write position specified by the read address RMki and the write address VINiki will be explained with reference to FIG. 3.

In FIG. 3, each read address designating the read position of data for one frame is RMAl.

RMA2. RMA3. A memory map obtained by dividing the buffer memory into four blocks whose starting addresses are RMA1 to RMA4 and then arranging the blocks in parallel with each other so that the last ends are lined up horizontally is shown. In this memory map, the writing position of one frame's worth of data is write area 8w.
They are lined up horizontally inside. That is,
The write address that specifies the writing position of one frame's worth of data is 19 jobutsu.

For example, the write address for the first frame of data in Table 3 is WwL4.
MA=12=RMA+12. WMA2=24=RMA
21 +9, WMA -33=RMA +6, WMA4
=39=RMA4-3 +3, as shown in FIG.

Now, when only the data for frame (2) is read, the count value of the absolute address generator 12 increases by one, and the count value of the counter 15 decreases by one.

Then, the write area Ew moves backward by one address, but the write position does not change, so the distance between the write position and the read area ER becomes smaller. Then, as shown in Table 4, when the number of read data becomes larger than the number of write data and WPt becomes 0, the read address Rh/iAi becomes equal to the write address WMAi and an underflow occurs.

Further, when only data for one frame is written, WPi increases by one. In this case, the writing area Ew does not move, but only the writing position moves backward, and the distance between the writing position and the reading area ER changes. Then, as shown in Table 5, when the number of write data becomes larger than the number of read data and WPt becomes 6, the read address RMki becomes equal to the write address WPi, causing an overflow.

Therefore, when the count value of the counter 15 is 3, the jitter margin M is as shown in □ shown in FIG. You will be able to do what you want. Also, the data read address HM
A, ~RMA4 and write address WMA1~WMA
Since address number 4 changes by one address each time the frame changes, there will be no unused portion in the buffer memory, and memory usage efficiency can be improved.

Furthermore, when the number of data ND in one frame increases, the storage capacity of ROM 10 may be increased, and when the interleap length d is changed, the data written in advance to ROM 1o may be changed; When it is desired to increase the jitter margin M, it is sufficient to simply increase the number of bits of the counter 15, so that it is easy to cope with system expansion in a PCM recording/playback system or the like. For example, ND=5. When d=5 and M=3, as shown in Table 6 (RMki).

It is possible to easily respond to system expansion by changing the system to generate WMAi. In addition, the minimum storage capacity required for the buffer memory in this case is 6X (3+1
) + 5 (1 + 2 + 3 + 4 + 5 + 6) = 129 units,
Full adder 13. outputs 129 as 0 and 130 as 1. Further, the read position and write position designated by RMki and WMAi in this case are shown in FIG. 5 in the same manner as in FIG. 3. In this FIG. 5, a numerical value indicating an address is attached to each storage location of the buffer memory so that the reading position and writing position of each data in the first frame in Table 6 can be easily recognized.

Further, in the memory address information signal generating device according to the present invention, the relative address generator 8 is configured to be used in common both when generating a write address and when generating a read address, so the circuit configuration is simplified. Since the number of wiring lines required can be reduced and the structure can be configured using a single l, the input decoder circuit and output buffer circuit forming the decoy can be made into a single unit. Therefore, according to the present invention, it can be expected that the chip area can be reduced when converting digital audio equipment into an IC.

As described in detail above, the memory address information signal generating device according to the present invention can easily detect the occurrence of memory overflow, underthrow, and jitter margin amount, and can easily cope with changes in interleave length. can improve the usage efficiency of I
Since the configuration is suitable for C conversion, it is suitable for use in a memory control device for deinterleaving memory in digital audio equipment.

In the above embodiment, the inputs to the signal selection circuit 90 are the read data number signal DB and the write data number signal. However, the number of inputs to the signal selection circuit 9 may be two or more; It is possible to add a correction data number signal to enable error correction of data in the read area. However, it is necessary to increase the storage capacity of ROM10 by the increase in the number of inputs.

7-' Table 1 Table 2

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional memory address information signal generating device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional memory address information signal generator. 4 is a diagram showing the relationship between the count value of the counter 5 and the jitter margin in the device of FIG. 2, and FIG. Figure 5 shows ND=6. d=5. 3 is a diagram showing a memory map of a buffer 7 memory in which the output of the device of FIG. 2 is used as an address input when M=3; FIG. Description of symbols of main parts: Relative address generators 11, 13, full adder 12, absolute address generator 14, signal selection circuit 15, counter 111 Applicant: Nono Ionia Co., Ltd. Agent Motohiko Fujimura, patent attorney Figure 1

Claims (1)

[Claims] A memory address information signal generation device that generates address information signals corresponding to read addresses and write addresses that change regularly and independently of each other and supplies them to a memory, wherein when data is written to the memory, the data generates a signal corresponding to a numerical value that changes according to a first predetermined rule each time data is written; and generates a signal corresponding to a numerical value that changes according to a second predetermined rule each time data is read from the memory; a first numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes by a second predetermined number each time a first predetermined number of data are read from the memory; a third circuit, each time the first predetermined number of data is read from the memory or the first predetermined number of data is written to the memory;
a third numerical information signal generation circuit that generates a signal corresponding to a numerical value that changes by a predetermined number; 2nd and 3rd
A signal corresponding to the addition result of the numerical value represented by each output of the numerical information signal generation circuit is output as a write address information signal, and a signal corresponding to the addition result of the numerical value represented by each output of the first and second numerical information signal generation circuit is outputted. A memory address information signal generating device characterized in that the signal is output as a read address information signal.