JPS6386161A - Error correcting device - Google Patents

Abstract

PURPOSE:To process various formats by only one erasion/error correcting device, by using a select signal with regard to input information having various formats, and executing an error correction conforming with each format. CONSTITUTION:An input data is stored in a RAM 11. In accordance with input information having plural formats, various format select signals are applied to an error correcting part. On the error correcting part, one determined error correcting part is provided, and a control part 9 varies a TIMING signal by a format signal which has been inputted and applies it to the correcting part 8, and controls an operation of the correcting part 8. By forming an error correcting device of such a constitution to one chip, various formats can be processed by only one erasion/error correcting device.

Description

[Detailed Description of the Invention] [Technical Summary] The present invention is in the field of error correction (encoding or decoding) for improving the error rate of communication paths of optical disks, magneto-optical disks, etc.
belongs to

[Prior art]

Traditionally, this type of device has been configured to operate on a predetermined format (code length of error correction code, correction capability, interleaving), so it can be used for different formats or for various formats. The disadvantage is that it cannot be easily applied when blocks are sent serially.

Furthermore, optical disks and magneto-optical disks are usually sector-managed. A sector contains not only data information but also address information.

It is important to protect these two types of information. Conventionally, as means for protecting information, an error correction code such as a Reed-Solomon code has been used in the data portion, and an error detection code such as a CRC has been used in the address portion. If the address field is incorrectly recognized, the entire sector will be in error, so conventionally, for the address field, emphasis has been placed on detection ability rather than correction ability, and multiple writes or retries have been performed in the case of errors. . However, a medium that is rewritable but cannot be overridden, such as a magneto-optical disk, requires three rotations of erasing, writing, and checking for rewriting. Address detection is required each time, but in a medium with a low error rate, the number of attempts increases and the delay time increases. Furthermore, if an error correction code is used in the address field, the hardware configuration of the error correction code is more complicated than that of an error detection code, and one modem is used for the data field and the address field, as shown in Figure 2. However, there is a drawback in that two error correction devices, an error correction section 13 for addresses and an error correction section 14 for data, are required.

In addition, the present applicant previously proposed a device that can handle free formats only for error correction (Japanese Patent Application Laid-Open No. 6-0-7
9674) L. However, it can be said that if it can support free formats for erasure correction, it will be optimal for even more free formats.

〔the purpose〕

In view of the above-mentioned points, the present invention uses a selection signal to perform error correction on input information having various formats by erasure/error correction means including the same erasure error correction.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, let's consider decoding.

Usually, a Reed-Solomon code (hereinafter referred to as an RS code) has a cross-interleaved structure (see FIG. 9). Therefore, one block must undergo two error corrections, C1 and C2.

When input information comes in uninterruptedly, delay time will accumulate unless there is an erasure error correction unit for CI and C2. As shown in the time chart shown, one erasure/error correction section is processed at double speed (■, ■). Furthermore, when there is no interleaving or when the transfer rate is high, the erasure/error correction section is made to be able to process at a constant speed. In FIG. 3, data is input in response to gate-in, the data is input to RAM II (2), and after an error correction operation is performed, the data is output (2). As is clear from the figure, compared to the data input/output time, the input/output time for ■ and ■ is 1/2.

Therefore, as shown in FIG. 4, the hardware configuration of the error correction unit includes a RAM 11 for storing input data, and one decision error correction unit (ERRORCORRECT BLOCK).
8, and includes a control section (CONTROL BLOCK) 9 that varies a TIMING signal for controlling the correction section according to an input format select signal.

First, various methods have been proposed for error correction, but TI
When the MING (timing) signal becomes variable, the algorithm shown in FIG. 5, which has a simple hardware configuration and is easy to handle, is used. FIG. 6 is a hardware configuration diagram for the decoding.

Next, encoding will be explained.

Usually, encoding is performed by multiplying information by a generator polynomial.

However, here we will consider an encoding method by changing the control of the error correction unit used for decoding. The hardware configuration is shown in FIG.

Parity pits are generated according to the calculation flow shown in FIG.

The above decoding and encoding can be integrated as described above, and the configuration thereof is shown in FIG.

1f″・　　　　　　　　　　　.

■ S=H-J=H・(I+E,)=H・Here i, j,
, disappears at position 42 I +H-E=H-E ・・・・・・・・・
...If (3) has occurred, then multiplying both sides by A-1, A-1 can be expressed as if t, j, and λ are known, then ex
CX= s, J, ni, IL) is...
...... (6) -Since it can be obtained arbitrarily, the output can be obtained as follows.

・・・・・・・・・・・・(8) However, if the error is ■i, j, k (triple), in the case of ■i, A becomes.

, j (double); ■ i (single); The operation is to multiply 30 to S by a constant, and it can be seen that it can be realized with the same circuit configuration as encoding. Its block diagram is not shown in FIG. In the A-1 generation circuit, since i-°C is fixed, it can be determined using several ROMs.

Therefore, an encoding/decoding circuit including erasure correction can be constructed as shown in FIG.

At this time, in order to switch between normal encoding/decoding and erasure correction, the erasure correction selection signal ER is used to switch between ROM5 and erasure correction.
1.52 needs to be switched. For that purpose, ROM5
1.52 should use a ROM for state control.

Furthermore, since the correction operation is delayed by one received word after the syndrome is generated, the received word must be stored in the buffer 53 once. Furthermore, the error pattern calculated at the time of syndrome generation is synchronized with the output from the buffer 53, and once the address 1-fl of the buffer 54 is outputted at the position i-°C.
It is necessary to store it in Then, the output from AD is t-U
When this happens, if that value is output, an error pattern will be output in synchronization with the buffer 53.

Note that if there is no interleaving or if this device is used for only one error correction operation for high-speed processing, it may be left as is.

Next, consider a case where this device is used for two error correction operations by interleaving. Note that interleaving is the 10th
Error correction operations are performed vertically and horizontally as indicated by the arrows shown in FIG.

Double-speed processing is possible by doubling the clock and trigger rates, so the problem is the difference between the formats of C1 and 52, but the correction ability T and code length n and k are different from C1 and C2.
can be made variable by giving them separately. FIG. 10-2 shows a circuit diagram when interleaving is performed. nl, n2
゜When TI and T2 are set, C select signal
n, T, and k become variable with C1 and C2.

For example, if the correction ability and code length of C1 and 02 are C1, then C=
When O, C2, it can be selected by setting C=1, and k is n
Since it is obtained by -2.TH, interleaving processing becomes possible.

By setting the C signal to D→1 or 1→D, the vertical and horizontal processing of the format can be arbitrarily selected.

In this way, by integrating a general-purpose error correction device into a single chip and making it compatible with various formats, it can be applied not only to optical disks, magneto-optical disks, etc., but also to all communication paths with low error rates. Ru.

In addition, by further interleaving and cascading such chips, the present invention can be applied to fields where error rates are high and high-speed processing is required.

In FIG. 11, S and M are sector marks indicating the start of a sector. At 5YNC, the clock component is extracted and the ID is read. I
A and M of D are address marks indicating the start of ADDRESS (address). A GAP is placed between the ID part and the DATA part to absorb jacks, etc., and 5YNC of the data part.

Absorbs the deviation between A, M, and DATA. The same goes for the data section, and the last GAP absorbs the gap between it and the next sector. Even if the address mark and the data part are encoded in different formats, they can be processed here by the device of the invention.

〔effect〕

As described in detail above, according to the present invention, an error correction device having a general-purpose format selector section and an erasure correction/reduction section (including an erasure position input section) is integrated into a single chip, so that it can be used uniformly for various formats. This has the advantage that only one erasure/error correction device is required.

Further, input information having a plurality of formats can be subjected to error correction in the same erasure/error correction unit according to each format by using select signals of various formats.

In addition, when erasing and error correcting interleaved data, there is an erasure/error correction device having a control unit that operates one erasure/error correction unit at double speed and operates at a constant speed for other erasure/error correction units or at a high transfer rate. can be provided.

Furthermore, in a device for erasure/error correction of information organized into sectors, it is possible to perform error correction not only on the data within a sector but also on the address information of the sector by the same erasure/error correction unit as the data section.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the hardware configuration of erasure/error correction. Figure 2 is a diagram showing the encoding/decoding circuit including erasure/error correction of the present invention. Figure 3 is data from data-in to error-corrected data. Figure 4 is a diagram showing the head configuration of the error correction section, Figure 5 is a flowchart of error correction, Figure 6 is a diagram of the hardware configuration for decoding, Figure 7 is the flow of calculation. Figure 8 is a hardware configuration diagram of encoding, Figure 9 is a configuration diagram of an encoder and decoder, Figure 10-1 is an explanatory diagram of interleaving, and Figure 10-2 is a configuration for interleaving. 11 is a diagram showing the position of error correction, 8 ------One error correction block 9 -----
--Control block 11 ------ RA
M l 5 -------Buffer

Claims (7)

[Claims] (1) Means for generating select signals of respective formats in accordance with input information having a plurality of formats; Erasure/error correction means for performing error correction including erasure error correction on the input information; An error correction device comprising a control means for controlling the error correction means to perform error correction according to each format. (2) The error correction device according to claim 1, wherein the erasure/error correction means uses a Reed-Solomon code. (3) In claim 1, the error is characterized in that erasure/error correction is performed in the erasure/error correction means, respectively, using data and address information in sector-structured information as input information. correction device. (4) The error correction device according to claim 1, wherein the erasure/error correction means includes erasure/error correction encoding or error decoding means. (5) An error correction device according to claims 1 and 3, wherein the input information is interleaved data. (6) In claim 1, the error correction means is characterized in that, depending on whether the format of the input information is interleaved or not, the control means increases the transfer rate to the error correction means at double speed or more. correction device. (7) The error correction device according to claim 1, characterized in that the format processing order can be freely selected vertically and horizontally.