JPS5658114A - Data delaying device - Google Patents

Data delaying device

Info

Publication number
JPS5658114A
JPS5658114A JP13205879A JP13205879A JPS5658114A JP S5658114 A JPS5658114 A JP S5658114A JP 13205879 A JP13205879 A JP 13205879A JP 13205879 A JP13205879 A JP 13205879A JP S5658114 A JPS5658114 A JP S5658114A
Authority
JP
Japan
Prior art keywords
counter
address
ram34
counting
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13205879A
Other languages
Japanese (ja)
Inventor
Tadashi Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13205879A priority Critical patent/JPS5658114A/en
Publication of JPS5658114A publication Critical patent/JPS5658114A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/10527—Audio or video recording; Data buffering arrangements

Abstract

PURPOSE:To simplify the constitution of the device at the same time eliminate the initial setting when the counting is started, by reducing the number of address counters down to one. CONSTITUTION:When the writing signal is delivered from the R/W control circuit 35, the RAM34 is set under the writing mode. And if it is supposed that the output data CA of the address counter 28 is CA, the word W1 is written into the address corresponding to the data obtained by applying the extent of the delay 3D given from the decoder 33 to the AC via the adder 29. After this, the words W2-W8 are written respectively into the RAM34 with every delay of D given. When the reading signal is delivered from the circuit 35, the RAM34 is set under the reading mode. Then the data is read out for the address corresponding to the data obtained by applying the output data CB of the buffer counter 30 to the output data CA of the counter 28 via the adder 29. The counter 30 starts the down-counting when receives the supply of the write address clock signal, and then carries out the up- counting with supply of the read address clock signal.
JP13205879A 1979-10-13 1979-10-13 Data delaying device Pending JPS5658114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13205879A JPS5658114A (en) 1979-10-13 1979-10-13 Data delaying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13205879A JPS5658114A (en) 1979-10-13 1979-10-13 Data delaying device

Publications (1)

Publication Number Publication Date
JPS5658114A true JPS5658114A (en) 1981-05-21

Family

ID=15072524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13205879A Pending JPS5658114A (en) 1979-10-13 1979-10-13 Data delaying device

Country Status (1)

Country Link
JP (1) JPS5658114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139385A (en) * 1982-02-10 1983-08-18 Pioneer Electronic Corp Information signal generator for memory address

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58139385A (en) * 1982-02-10 1983-08-18 Pioneer Electronic Corp Information signal generator for memory address

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