JPS54145445A - Bubble memory unit - Google Patents

Abstract

PURPOSE: To make it possible to simplify the discrimination of a fault element as well as the detection of a fault at the time of a read by finding an indefective minor loop among margin minor loops and then by writing parity information generated for each element to the indefective minor loop.

CONSTITUTION: Over a bit-by-bit comparison between write data and defect information, write data to bubble elements 1₁ to 1₁₀ are generated in data register 5. Next, the content of corresponding resister 5 is added, bit by bit, to parity registers 3₁ to 3₁₀ provided corresponding to respective bits of register 5. Now, when data are supposed to be written to minor loops out of seventy loops to the sixty seven one, write data lines 6₁ to 6₁₀ are changed over to parity register lines 7₁ to 7₁₀ for access to the remaining sixty eighth one; and then, registers 3₁ to 3₁₀ are inhibited, under the control of defect information register 4, from outputting when corresponding bits are defective, and writes to element groups 1₁ to 1₁₀ are done when not. At the time of the read, the parity of each element is regenerated as to all minor loops in registers 3₁ to 3₁₀ at the same time as an ordinary read.

COPYRIGHT: (C)1979,JPO&Japio