JPS57198596A - Nonvolatile memory device - Google Patents

Nonvolatile memory device

Info

Publication number
JPS57198596A
JPS57198596A JP57078238A JP7823882A JPS57198596A JP S57198596 A JPS57198596 A JP S57198596A JP 57078238 A JP57078238 A JP 57078238A JP 7823882 A JP7823882 A JP 7823882A JP S57198596 A JPS57198596 A JP S57198596A
Authority
JP
Japan
Prior art keywords
loop
information
storage
loops
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57078238A
Other languages
Japanese (ja)
Other versions
JPS6118277B2 (en
Inventor
Junshi Asano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57078238A priority Critical patent/JPS57198596A/en
Publication of JPS57198596A publication Critical patent/JPS57198596A/en
Publication of JPS6118277B2 publication Critical patent/JPS6118277B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To read information in parallel, by allowing a storage loop to include a data storage loop and one, at least, auxiliary loop similar to the data storage loop.
CONSTITUTION: Proper optional information is written in one bit, for example, 21 out of idle bits which has the same address in each of all storage loops including a defective loop position storage loop 18 and a parity check loop 19, and the sum of written information gives a parity error. Information "111...1", information "000...0" or other information is used as this information; in short, only addresses 21 give a parity error. Addresses 21 are not accessed in the normal memory operation. In this mode, if the number of indefectible loops out of storage loops is higher than a prescribed value, it does not matter where defective loop exists.
COPYRIGHT: (C)1982,JPO&Japio
JP57078238A 1982-05-12 1982-05-12 Nonvolatile memory device Granted JPS57198596A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57078238A JPS57198596A (en) 1982-05-12 1982-05-12 Nonvolatile memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57078238A JPS57198596A (en) 1982-05-12 1982-05-12 Nonvolatile memory device

Publications (2)

Publication Number Publication Date
JPS57198596A true JPS57198596A (en) 1982-12-06
JPS6118277B2 JPS6118277B2 (en) 1986-05-12

Family

ID=13656448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57078238A Granted JPS57198596A (en) 1982-05-12 1982-05-12 Nonvolatile memory device

Country Status (1)

Country Link
JP (1) JPS57198596A (en)

Also Published As

Publication number Publication date
JPS6118277B2 (en) 1986-05-12

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