CA1316269C - Interleaving method and apparatus - Google Patents

Abstract

ABSTRACT

An interleaving method and apparatus suitable for burst error correction occurring in data transmission or reading of recording medium. In the interleaving method in which data to be transmitted is once written in a storing means and then read to be output in order different from a writing order, a plurality Or counters for dividingly generating addresses of the storing means is used; and an operational relationship between the counters is changed between writing and reading of the storing means. ROMs for address translation can be omitted so that the number of gates is reduced very much.
Thus, a reasonable interleaving apparatus suitable for LSI formation can be realized. In addition, since ROMs for address translation interposed between the counter and the storing means in the convetional apparatus are omitted, access time for the storing means can be shortened substantially.

Description

1 31 6~

This invention relates to an interleaving method and appa,ratus suitable for correction of, so-called burst error which might occur during data transmission or reading of the recording medium.

Fig. 1 is a block diagram showing a structure of the present invention;

Fig. 2 is a circuit diagram of a first embodiment of the present invention;

Fig. 3A and Fig. 3B are state tables showing an operation of the circuit shown in Fig. 2;

Fig. 4A and Fig. 4B are timing diagrams of a counter shown in Fig. 2;

Fig. 5 is an explanatory view for explaining an operation of the circuit shown in Fig. 2;

Fig. 6 is a circuit diagram of a second embodiment of the present invention;

Fig. 7 is a circuit diagram of a third embodiment of the present invention;

Fig. 8A and Fig. 8B are state tables of an operation of the circuit shown in Fig. 7;

Fig. 9 is a block diagram showing a configuration of a conventional interleaving apparatus, ,~

~4 ~

Fig. lOA, Fig. lOB, Fig. lOC, Fig. 11 and Fig. 12 are explanatory views for explanation of the apparatus shown in Fig. 9.

Errors massedly generated in the form of burst during data transmission by a transmission system or reading of data on an optical recording medium have been known as a burst error. For example, data is recorded at a high density within a limited space of a recording medium in the optical recording medium, so that even a small flaw would result in a number of defect bits.

In general, as an error correcting code for correcting an error, there has been widely used BCH code ~Bose-Chaudhuri-Hocquenghem code) including Reed-Solomon Code.

Even when the error lasts too long to be correctable by such an error correcting code, an interleaving method may be used. According to this method, recorded data or transmission data is broken up according to a certain rule, so that when the data is restored, the burst error is dispersed into various portions and errors in the respective portions are correctable by the error correcting code.

Fig. 9 illustrates a block diagram of a conventional interleaving apparatus. For convenience, 3 x 4 interleaving for each 12 data is illustrated for an example. A basic method for interleaving is such that:

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-1 31 62~q when data from a data source 50 is transmitted or recorded on a recording medium, data output from the data source 50 i6 sequentially written once into a read/write memory (~AM) 48 and the data is read in an address sequence dirrerent rrom an address sequence when the data is written, to interleave the da-ta.
In the conventional apparatus Or Fig.9, a counter 40 is used for generating an address and read-only-memories (ROM) 42 and 46 are used ror changing the output data rrom the counter between reading and writing. Numerals shown in Figs.lOA and lOB, for example, are written in ROMs 42 and 46.
A brier description of an operation of the conventional apparatus will be now given.
If data A, B, C, D, E, F ... is output rrom the data source 50 as illustrated in an upper row of Flg.ll, the data ls once wrltten in RAM 48. In the writing, a reading/writing switching signal ~/W (hereinarter rererred to simply as signal RW) becomes "low" and ROM 46 is enabled, while ROM 42 is disabled through an inverter 44.
Since data same as the addresses Or ROM 46 are written in ROM 46 (in this case, ROM 46 functions ~ust as a buf~er), the addresses Or RAM 48 are addressed in an ascending order ir the counter 40 is an up-counter and written in as illustrated in Fig.lOC.
When RAM 48 is read, RW signal becomes "high" and ROM is enabled, while ROM 46 is disabled. Thererore, the output data rrom the counter 40 is translated by ROM 42.
More particularly, the addresses Or RAM 48 are addressed in order Or O ~ 4, 8, 1, 5 . . . as illustrated in Fig.lOA.
As a result of this, the data is read from RAM 48 in a sequence dirrerent from the writing sequence as illustrated in a lower row Or Fig.ll.

t 31 62~'9 The processing operation as described above is equivalent to an operation reading, sequentially in a column direction, a matrix Or 3 x 4 Or Fig.12, in which serial data is sequentially arranged in a row direction.
A receiving unit for transmitted data or a reproducing unit for a recording medium comprises an apparatus as shown in Fig.9 which restors the serial data into an original order by carrying our a procedure reverse to the write/read procedure as described above. More particularly, the data is once written in RAM 48 according to the output rrom ROM 42 and it is therearter read according to the output rrom ROM 46.
Since ROMs are used in the conventional apparatus as described above, a considerably large number Or gates are needed. This is a problem to form the circuit Or the apparatus in LSI. Further, since address signals from the counter ror addressing a storing means are translated by ROM, an accessing time Or RAM is substantially increased, preventing speed-up Or an interleaving operation.

DISCLOSURE OF INVENTION

Therefore, it is an ob~ect Or the present invention to provide an interleaving method and apparatus which is suitable to be formed in LSI and capable Or accessing a storing means directly by an address.signal rrom a counter.
The present invention provides, to solve the problems as described above, the rollowing two inventions.
A rirst invention features an interleaving method in which data to be transmitted is once written in a storing 1 31 62~q means and then read to be output in order difrerent rrom a writing order, which method is characterized in that a plurality Or counters ror dividingly generating addresses Or the storing means is used; and an operational relationship between the counters is changed between writing and reading Or the storing means.
A second invention reatures an interleaving apparatus in which data to be transmitted is once written in a storing means and then read to be output in order dirferent from a writing order as illustrated in Fig.1, which apparatus comprises:
a plurality Or counters C1 and C2 each having a data output terminal connected to a part Or address input terminals Or the storing means; and a counter control means 2 which receives a clock signal and a write/read switching slgnal for the storing means to switch the operational relationship between the respective counters by the write/read switching signal.
In the second invention, two counters are prererably used and a sum Or output bits Or the counters is an address Or the storing means.
Or, the counter control means preferably comprises AND gates, an inverter and OR gates.
If output bit numbers Or the counters C1 and C2 are n and m, respectively, (n + m)bits are used as addresses ror (n + m) bits Or the storing means.
The data to be written once into the storing means may be one bit or plural bits.
The description "operational relationship" as given above meanæ a relationship in which one Or the counters is clock driven per cycle Or another counter and the description "the operational relationship is changed"
means the relationship in which a certain counter is clock driven per cycle Or another counter is changed.

One cycle of the counter means all N values of a divided-by-N counter are counted, but the order may be ascending or descending.

The clock to be input into the counter is not always of a fixed period.

According to the present invention, addresses of the storing means are dividedly generated by a plurality of counters and the operational relationship between the respective counters is changed between the writing and reading of the storing means, so that the storing means can be accessed directly by address signals from the counters and the conventional ROM for address translation interposed between the counter and the storing means can be omitted.
Therefore, the gate number can be reduced very much and the access time for the storing means can be shortened very much.

Furthermore, various interleaving modes can be attained by selecting the number of the counters used and/or switching up/down-counting in write/read operation. This also enables relatively complicated data enciphering. More particularly, ~O since original data cannot be restored on a data receiving (reproducing) side unless a method or apparatus corresponding to the method and configuration of the interleaving on a data transmitting (recording) side, the enciphering effect can be increased as the interleaving becomes more complicated.

Embodiments of the present invention will now be described. Although the following description refers to an example wherein 3 x 4 interleaving is carried out, a larger matrix may be used.

1 31 62Gq (Configuration of First Embodiment) Fig. 2 is a circuit diagram of an one form of an interleaving apparatus according to one embodiment of the present invention.

In this embodiment, counters C1 and C2 are a divide-by-four counter and a divide-by-three counter, respectively. A
storing means comprising RAM 4 has an address of 4 bits.
Output terminals QO and Ql of the ~9 1 31 62u9 counter C1 are connected to address input terminals A0 and A1 of RAM 4, respectively. Output terminals QO and Ql Or the counter C2 are connected to address input terminals A2 and A3 Or RAM 4, respectively. A counter control circuit 2 generates clock signals for the counters C1 and C2 in response to a clock CLK or a write/read switching signal RW. A data source 6 ror generating data to be written in RAM 4 is omitted in Fig.2.
A counter control circuit 2 comprises AND gates 21, 23, 25 and 27, an inverter 24 and OR gates 22 and 26.
The AND gate 21 receives, at one input terminal thereor, the clock CLK and receives, at another input terminal, the read/write switching signal RW through the inverter 24. The AND gate 25 receives, at its two input terrninals, the clock CLK and the read/write switching signal RW. The AND gate 23 receives, at its one input terminal, the switchlng signal RW and receives, at another input terminal, an output rrom Q1 Or the counter C2.
The AND gate 27 receives, at its one input terminal, the switching signal RW through the inverter 24, while it receives, at another input terminal, an output rrom Q1 Or the counter C1. The OR gate 22 receives, at its two input terminals, outputs from thé AND gates 21 and 23, respectively. The OR gate 26 receives, at its two input terminals, outputs rrom the AND gates 25 and 27, respectively. Outputs from the OR g~tes 22 and 26 are connected to clock input terminals Or the counters C1 and C2, respectively.

(Operation Or First Embodiment) An operation o~ the circuit shown in Fig.2 will now 1 31 62~'9 be described. Fig.3A shows states of the counters and states Or written data when RAM 4 is in an writing operation and Fig.4A is a timing diagram Or the respective counters. Similarly, ~ig.3B shows states Or the counters and states Or data when RAM ll is in a read operation and Fig.4B is a tim:lng diagram of the respective counters.
As in the description Or the conventional apparatus, the data source generates serial data A, B, C, D, E ...
In writing when the switching signal RW becomes "low", the clock CLK passes through the A~D gate 21 and the OR
gate 22 to drive the counter C1. In this case, the counters count up by trailing ends Or input clocks.
The counter C2 counts up by a trailing end Or the output rrom Q1 Or the counter C1 (i.e., carry Or the counter C1). As a result Or this, a write address Or RAM
4 changes sequentially as 1, 2, 3, 4, 5 .... Thus, the serial data ls written in order o~ the address.
After twelve data have been written, the switching signal RW becomes "high" and RAM 4 is put into a reading state. At this time, the clock CLK is passed through AND
gate 25 and the OR gate 26 to drive the counter C2.
The counter C1 counts up by a trailing end Or the output from Q1 Or the counter C2 (i.e., carry Or the counter C2) as can be seen from Fig.4B. As a result Or this, the order Or the reading address Or RAM 4 changes in order (O, 4, 8, 1, 5 ...) difrerent from that Or the writing address. Thus, the serial data is read in the order difrerent from that in the writing operation.
These write/read operation with reference to RAM 4 is repeated until the serial data ends.
Fig.5 shows the values (binary numbers) Or the counters C1 and C2 and the addresses (decimal numbers) Or RAM 4 in the form Or matrix. The writing operation as 1 31 62~9 described above corresponds to the access Or the addresses which starts from the lert Or the uppermost row to the left Or the lower row. The reading operation corresponds to the access Or the addresses from the upper to the lower Or the leftmost column and to the upper Or the next column.
In the receiving unit or the reproducing unit, write/read operation may be carried out in a procedure reverse to that as described above to restore the serial data Or the original order. To attain this, only the output rrom the OR gate 22 Or Fig.2 may be applied to the counter C2 and the output from the OR gate 26 may be applied to the counter C1.
Although the counter as used above is an up-counter, it may alternatively be a down-counter. Further, the writing is errected in order Or the addresses and reading is carried out not in order Or the addresses in the embodiment as described above, but the writing may be errected not in order Or addres~e~ and the reading may be carried out in order Or addresses.

(Conriguration Or Second Embodiment) Fig.6 is a circuit diagram Or a second rorm Or an interleaving apparatus according to the present invention. This invention is similar to the rirst embodiment except ror the conriguration Or the counter control circuit 2. Only this dirference will now be described.
The counter control circuit 2 Or the present embodiment comprises a 1/3 frequency divider 31, a 1/4 frequency divider 35, a multiplexers 32 and 34 and inverter 33.
The multiplexer 32 receives, at its A input 1 31 62Gq terminal, a clock CLK through the divider 31 and directly receives the clock CLK at its B input terminal. The input A or B is selected by an inverted signal Or the switching signal W~ inverted by the inverter 33. The multiplexer 34 receives the clock CLK at its A input terminal through the divider 35 and directly receives the clock CLK at its B input terminal. The input A or B is selected according to the switching signal WR. The division ratios Or the dividers 31 and 35 are determined according to the division numbers Or the counter C2 and C1, respectively.

(Operation Or Second Embodiment) In the writing operation when the switching signal is "low", the multiplexers 32 and 34 select the input B
and the input A, respectively. Thererore, the counter C1 i8 directly clock driven by the clock CLK. The counter C2 receives the clock CLK through the divider 35, so that it i8 clock driven once whenever the counter C1 is clock driven rOur times. As a result Or this, the changes or Or the states Or the respective counters, timing thereor or the order Or the writing addresses are equivalent to those Or the rirst embodiment as shown in Figs.3A and 4A.
In the reading operation when the switching signal is "high", the multiplexer 32 selects the input A and the multiplexer 34 selects the input B. Thererore, the counter C2 is directly clock driven by the clock CLK, while the counter C1 receives the clock CLK through the divider 31, so that it is clock driven once whenever the counter C2 is clock driven three times. As a result Or this, the changes Or the states of the counters, timing and the order Or the reading addresses are equivalent to those Or the rirst embodiment as shown in Figs.3B and 4B.

1 31 62~q (Conriguration Or Third Embodiment) Fig.7 illustrates a conriguration Or a third rorm Or an interleaving apparatus according to the present invention.
In this embodiment, the counters C1 and C2 are formed Or programmable array logic (PAL) 20 x 8 manuractured by MONOLITHIC MEMORIES CO., LTD. The counter control circuits are considered to be inherent in the respective counters.
In this embodiment, the counter C1 loads data (which determines the division number Or the counter) Or eight bits into input terminals S0 to S7 by a rising e~d Or the clock CLK when a signal LDA to be input to a LD terminal is outpu-t. The counter C1 counts down by the clock CLK
when a slgnal BOUTO is output rrom an output terminal OUTO terminal Or the counter C2.
The count value is output through output terminals A0 to A7. When the count value becomes zero, a "low"
signal is output through the output terminal OUTO. The down-counting is errected only by the clock CLK when the switching signal RW to be input to an input terminal SAKI
is "low" and by a rising end Or the clock CLK when the switching signal RW is "high" and the signal BOUTO is "low".
Similarly, the counter C2 can load data Or elght bits into input terminals S0 to S7 by a rising end Or the clock CLK when a signal to be input to a LD terminal is output and counts down its value only by the clock CLK or the clock CLK when a signal BOUTO is output from an output terminal OUTO Or the counter 1. The count value is output through output terminals B0 to B7.
When the count value reaches zero, a "low" signal is 1 31 626q ~utput through the output terminal OUTO. The down-counting i8 carried out by by the clock CLK when the swLtching signal R~ to be input to the input terminal ATO
is "high" and by a rising end of the clock CLK when the switching signal RW is "low" and the signal AOUTO is "low".
The output data AO to A7 and BO to B7 are input to input terminals A8 to A15 and AO to A7 Or RAM 4, respectively. Although RAM 4 has separate input/output terminals for data in Fig.4, RAM 4 does not necessarily have separate terminals. Further, RAM 4 shown in Fig.4 has an input/output terminal for one-bit data, but if the data is Or plural bits, a plurality Or RAMs 4 may be employed or RAM ror multiple-bit data.

(Operation Or Third Embodiment) The counters C1 and C2 are loaded with data at a timing when a clock immediately arter the respective count values have become zero. To function the counters C1 and C2 as a divide-by-four counter and a divide-by-three counter, respectively, the counter C1 is loaded with 3 (decimal number) and the counter C2 is loaded with

2 (decimal number).
Since the down-counter is used in the present embodiment, the orders Or the writing addresses and the reading addresses are reverse to those in the foregoing embodiments.
According to the present embodiment, the division number Or the counter can be changed easily by changing the value to be loaded to the counter. More, particularly, this embodiment is flexible in that the size Or the matrix as shown in Fig.5 can be changed freely .

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(Modification) Both the counters C1 and C2 are up-counters or down-counters in the foregoing embodiments, but one of the counters may be an up-counter, while the other being a down-counter. Further, although the foregoing embodiments have two counters, three or more counters may be used to dividely share the addresses Or ~AM between them.

Claims

THE EMBODIMENTS OF THE INVENTION IN WHICH AN EXCLUSIVE PROPERTY OR
PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
(1) An interleaving method in which data to be transmitted is once written in a storing means and then read to be output in order different from a writing order, which method is characterized in:
that a plurality of counters for dividingly generating addresses of the storing means is used; and an operational relationship between the counters is changed between writing and reading of the storing means.
(2) An interleaving apparatus in which data to be transmitted is once written in a storing means and then read to be output in order different from a writing order, which apparatus comprises:
a plurality of counters each having a data output terminal connected to a part of address input terminals of the storing means; and a counter control means which receives a clock signal and a write/read switching signal for the storing means to switch the operational relationship between the respective counters by the write/read switching signal.

(3) An interleaving apparatus according to claim 2, in which two counters are used and a sum of output bits of the counters is an address of the storing means.

(4) An interleaving apparatus according to claim 2, in which said counter control means comprises AND gates, an inverter and OR gates.

(5) An interleaving apparatus according to claim 2, in which said counter control means comprises frequency dividers, multiplexers and an inverter.