JPS6127781B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a main memory device.

As shown in Figure 1, the data system control unit of a conventional main memory device includes an interface control unit 1 that exchanges data with a host device such as a central processing unit, and a register that stores write data when a partial write request is made. 2. A selection circuit 3 that generates rewrite data from write data and read data at the time of a partial write request and switches between full write data and rewrite data depending on the difference between a full write request and a partial write request;
It is composed of an error correction code generation circuit 4 that generates an error correction code from write data that is the output of the selection circuit 3, an error detection and correction circuit 5 that detects and corrects errors in read data, and a storage section 6 that stores data. There is. Furthermore, when performing n-way interleaving, n sets of the above configuration are required.

In order to explain the operation of the main memory device having the above configuration, a case will be described in which a partial write request in which a read operation and a write operation are performed within one cycle is given from a host device. When a partial write request is received for a certain memory module, the write data from the host device is stored in the register 2 of the corresponding bank. Thereafter, the data read from the address of the storage section where the partial write request was made is provided to the selector circuit 3 via the error detection and correction circuit 5, and is matched with the write data of the register 2 to generate rewrite data. Ru. An error correction code is generated for the rewrite data by the error correction code generation circuit 4, and the error correction code is rewritten into the storage unit 6 together with the rewrite data.

As described above, in the case of a partial write request in which a read operation and a write operation are performed within one cycle, the write path, that is, the selection circuit 3 → the error code generation circuit 4 → the storage unit 6, and the read path, that is, the storage unit 6 → Both error detection and correction circuits 5 are occupied until the end of the cycle. Therefore, n
When way interleaving is performed, the write path and the read path must be provided for each bank, which has the disadvantage that the amount of hardware becomes extremely large.

An object of the present invention is to prevent write operations that reach other memory modules for a certain period of time after a certain period of time has elapsed from the start of a partial write operation to a certain memory module in a main memory device that performs n-way interleaving. The present invention provides a main memory device in which a write control section for each bank can be shared.

The device of the present invention includes n storage means each storing data in a main storage device that performs n-way interleaving;
a partial write data storage means for storing partial write data in response to a partial write request to the storage means; and selection of all write data given from the outside and data from the partial write data storage means in response to a write request. a selection means for generating an error correction code based on the write data from the selection means, a writing means commonly connected to each of the n storage means and writing the error correction code together with the write data; reading means commonly connected to each of the storage means for reading out data and an error correction code and correcting the data;
The present invention is characterized in that while data and error correction codes are being written into one of the storage means, operations other than writing are performed on the other storage means.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

As shown in the block diagram of one embodiment of the present invention in FIG. 2, an interface control section 1 is provided for exchanging data with a central processing unit, etc., and an interface control section 1 is provided for each bank that stores write data at the time of a partial write request. A register 2, a selection circuit 3 that generates rewrite data from write data and read data at the time of a partial write request, and switches between full write data and rewrite data in response to a full write request or a partial write request, and an output of the selection circuit 3. It is comprised of an error correction code generation circuit 4 that generates an error correction code from write data, an error detection and correction circuit 5 that detects and corrects errors in read data, and a storage section 6 that stores data. The storage unit 6 is composed of modules #1 to #n corresponding to each bank to enable n-way interleaving.
Write data and read data are each connected by a common signal line.

The n-way interleaving operation in FIG. 2 will be explained.

In the case of a full write request, the write data is written to the storage section 6 of the bank specified by the write path of interface control section 1 -> selection circuit 3 -> error correction code generation circuit 4 -> storage section 6. When all write requests to different banks are made sequentially, the storage units (#1 to #n) of the designated bank are sequentially written, and n-way interleaving becomes possible.

In the case of a read request, the read data is stored in the storage unit 6.
->Error detection and correction circuit 5 -> Read from the storage unit 6 of the bank specified by the read path of the interface control unit 1. When read requests from different banks are made sequentially, reading is performed sequentially from the storage units (#1 to #n) of the designated bank, making n-way interleaving possible.

Even if all write requests and read requests are mixed and come sequentially, since the write pass and read pass are independent as described above, operations are performed on the storage unit 6 of the corresponding bank in sequence according to the requests. hand,
N-way interleaving is possible.

A case where partial write requests and full write requests coexist will be explained using FIG. 3.

FIG. 3 is a diagram illustrating an n-way interleaving operation when partial write requests and full write requests coexist in the main storage device having the configuration shown in FIG. 2. When a request such as a partial write request to perform a write operation or a read operation on the storage unit 6 within one cycle is given to the main memory device, the partial write data is stored in the register 2 of the corresponding bank. After that, the entire write data path, that is, the path from interface control unit 1 → selection circuit 3 → error correction code generation circuit 4 → storage unit 6, is opened, so that following the above request, operations due to full write and partial write requests to different banks are performed. It becomes possible.
After time t ₁ has elapsed, the rewrite data due to the partial write request is input to the selection circuit 3, and from that time onwards, for the time t ₂ necessary to write the rewrite data to the storage unit 6, the interface for all write requests to different banks is input. The path from the ace control unit 1 to the storage unit 6 becomes unusable. Therefore, the time t ₁ after issuing a partial write request to the main memory in the host device
If control is adopted that does not issue a request for all written data to be input to the selector circuit 3 later, there will be no competition between all written data and rewritten data in the selection circuit 3, and n-way interleaving becomes possible. The data system control circuit of each bank can be shared. At this time, the time when the request is prohibited
Since _t3 is small compared to the partial write cycle tc, it has little effect on performance.

As explained above, in a main memory device that performs n-way interleaving, the present invention has a method in which, after a certain period of time has elapsed from the start of a partial write request to a certain memory module, write operations to other memory modules are not performed for a certain period of time. This has the effect that the write control section for each bank of the main memory device can be shared.

[Brief explanation of the drawing]

FIG. 1 is a data system block diagram of a conventional main memory device, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a diagram explaining the operation of FIG. 2. 1 and 2, 1...interface control unit, 2...partial write register,
3...Selection circuit, 4...Error correction code generation circuit, 5...Error detection and correction circuit, 6...Storage section.

Claims (1)

[Scope of Claims] 1. In a main memory device that performs n-way interleaving, n storage means each store data, and a partial write data storage that stores partial write data in response to a partial write request to the storage means. means for selecting, in response to a write request, all write data given from the outside and data from the partial write data storage means; and generating an error correction code based on the write data from the selection means. writing means commonly connected to each of the n storage means for writing an error correction code together with the write data; and reading means commonly connected to each of the n storage means for reading the data and the error correction code and correcting the data. and at least said n in response to said partial write request.
1. A main memory device characterized in that, while data and error correction codes are being written into one of the storage means, operations other than writing are performed on the other storage means.