KR0160645B1 - Error correction decoder of digital vcr - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an error correction decoder of a digital signal, comprising: a synchronous detector for inputting reproduction data and searching for a synchronous block to output a synchronous flag, a clock, and data; Inputs an internal decoder for outputting identification flags, clocks and data, a ROM storing the address to be written to as a lookup date, a plurality of memories for storing synchronous block data at addresses obtained from the lockup table, and an output of the internal decoder. A control unit which accesses the ROM according to the error correction flag and the identification data, generates an address to write, writes to one memory according to the address, reads another memory, and outputs the recovered data flag, data, and clock. External decoder to recover and decode sync block by inputting output Having to be decoded to recover the sync blocks have not detected in the reproduced data.

Description

Digital VSD Error Correction Decoder

1 is a block diagram showing a decoder used for a general digital BT,

2a to 2e are waveform diagrams showing examples of signal formats according to the present invention;

3 is a block diagram showing an error correction decoder having a synchronous block recovery function according to the present invention;

4A to 4F are waveform diagrams showing signals of respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: synchronization detector 11: internal decoder

12 control unit 13 ROM

14: memory A 15: memory B

16: external decoder

The present invention relates to a decoder used in a digital video cassette recorder (hereinafter referred to as a D-VCR), and more particularly, to an error correction decoder having a function of recovering a lost SYNC block on each track of a video tape. It is about.

In general, the number of sync blocks carried on each track of a digital video tape is constant, and it is often the case that a sync block near the start of each track cannot be detected. For normal two-dimensional error correction decoding, it is necessary to constantly input the number of sync blocks per track to an external decoder. In the conventional error correction decoding method, however, the synchronization blocks are continuously accumulated and decoded without reference to the identification data ID. Therefore, in the conventional decoding method, there is a problem that the synchronization of the error correction block is broken because the synchronization block is not detected near the beginning of each track.

Accordingly, an object of the present invention has a sync block recovery function for recovering a sync block not detected at the beginning of a video track by using dummy data after internal decoding. An error correction decoder is provided.

In order to achieve the above object, the apparatus of the present invention inputs the reproduction data and searches the synchronization block in the error correction decoder of the digital video cassette recorder which recovers and decodes the synchronization block which is not detected by inputting the reproduction data. A synchronization detector for outputting a clock and data; An internal decoder configured to input an output of the synchronization detector to output a data flag, an error correction flag, an identification flag, a clock, and data;

A ROM storing an address to be written to as a lookup table; A plurality of memories for storing sync block data at an address obtained from the lookup table; Input the output of the internal decoder to generate an address to access and write the ROM according to the correction flag and the identification data, write to the one memory according to the address, and read the other memory to recover the recovered data flag and data A control unit for outputting a clock; And

And an external decoder for recovering and decoding the sync block by inputting the output of the controller.

Next, the apparatus of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram showing a decoder unit of a general digital VCR. In FIG. 1, the decoder unit 7 includes a demodulator 1 for inputting and demodulating a reproduction signal from a video tape TAPE, and a synchronous detector 2 for inputting an output of the demodulator 1 to detect a synchronous block. And an error corrector (ECC- ¹ : 3) for correcting the error by inputting the output of the synchronous detector (2), and an output of the error corrector (3) and the original video data (R, G, B signals). Or a source decoder 4 for decoding to a Y, RY, BY signal. The decoder 7 demodulates the playback signal to correct an error occurring in the playback process, and then expands the compressed data to reproduce the original video data (R, G, B data or Y, RY, BY). That is, the data read from the video tape TAPE is inputted to the demodulator 1, demodulated, and then inputted to the sync detector 2 to detect the sync block. In (4), the compressed data is decompressed. The error correction unit 3 mainly uses a two-dimensional reed-solo decoder in the D-VCR system. The demodulator 1, the sync detector 2, the Reed-Solo only decoder 3 and the source decoder 4 have already been published and known in many papers.

2A to 2E are waveform diagrams showing the signal format according to the present invention. FIG. 2a shows a VHS signal toggled every track, and FIG. 2b shows dummy data a, b at a portion where the VHS signal is toggled. It is. FIG. 2C shows the sync flag SYNC_F, which is 'low' at the 2-byte position of the sync data and has 156 sync blocks per track. FIG. 2D is a data flag D_E representing data excluding 2 bytes of sync data in each sync block, and has a length of 156 x 164 bytes per track when the size of one sync block is 164 bytes. FIG. 2E shows an identification flag ID_E indicating a position of two bytes of identification data ID per sync block, and it can be seen that there are 156 pieces 1,2,3:

3 is a block diagram showing an error correction decoder having a synchronous block recovery function according to the present invention. The error correction decoder of the digital video cassette recorder inputs reproduction data, searches for a synchronization block, and outputs a synchronization flag (SYNC_F), a clock (CLK), and data (DATA0), and a synchronization detector (10). An internal decoder 11 for inputting the output to output the data flag D_E, the error correction flag CORRECT_F, the identification flag ID_F, the clock CLK, and the data DATA1, and stores the address to be written to the lookup table. A ROM (ROM: 13), a plurality of memories 14 and 15 storing the synchronous block data, and outputs of the internal decoder 11, and inputted according to the error correction flag CORRECT_F and the identification data ID_F. The ROM 13 is accessed by the address add A, inputs an address add B to be written, and is written into the memory A 14 or the memory B 15 in accordance with the address add B, and the memory B 15 is written. ) And the data flag D_E1 and the data DATA4 recovered by reading the memory A 14 and And a control unit 12 for outputting a clock CLK, and an external decoder 16 for inputting the output of the control unit 12, restoring and decoding the sync block, and recovering the sync block that was not detected by inputting reproduction data. Decode In FIG. 3, the sync detector 10 searches the track data to find a sync code, and outputs a sync flag SYNC_F signal, a clock CLK, and data DATA0. At the 2-byte position of the sync data, the sync flag SYNC_F is 'low'. The number of sync blocks per track in the current system is 156. The internal decoder 11 inputs the output of the synchronization detector 10 and inputs a data flag (D_E) signal representing pure data obtained by subtracting 2 bytes of synchronization data from each sync block, and an error correction flag (CORRECT_F) indicating whether the internal decoding result is error corrected. ) And an identification flag (ID_F) indicating the identification data (ID), a clock (CLK), and data (DATA1). When the size of one sync block is 164 bytes, the width when the data flag D_E signal is 'high' is 156 x 164 bytes per track. During this period, a signal indicating the position of two bytes of identification data ID per sync block is the identification flag ID_F. However, at the beginning of the track some miss sync blocks occur. In the embodiment of the present invention, it is assumed that two synchronization blocks are missed initially. Since two sync flags have been lost, the size of the data flag D_E at this time is 154 x 164 bytes. The control unit 12 inputs the output of the internal decoder 11 to track the track with reference to the identification data ID and the error correction flag CORRECT_F when the data flag D_E per track changes from 'low' to 'high'. The recovered data flag D_E1, the data DATA4, and the clock CLK are output so that the number of synchronization blocks per block is always maintained at 156. In the case where two sync blocks are lost as described above, when the third sync block is inputted, the address (ROM) is transmitted to the ROM 13 with reference to whether the identification data ID and the correction flag of the third sync block are 'high'. output add A) to find the write address add B from the lookup table, and output the first address to be written to memory A 14 (that is, the address where the third sync block is to be placed in the embodiment of the present invention). Data is written to the memory A14. On the other hand, the memory A 14 and the memory B 15 reorder the sync block data by toggling reads and writes. Therefore, when reading memories A and B (14, 15), dummy data is read by accessing the undetected sync block address of the initial part of the track, and memories A and B are lost even if the sync block is lost in the initial part of several tracks. When reading at (14, 15), the number of 156 sync blocks is maintained. Therefore, some sync blocks that have missed track leads are recovered to keep the number of sync blocks input to the external decoder 16 in one track at 156 at all times. Therefore, when the recovered data flag D_E1 signal is 'high', it is 156 x 164 bytes. The control unit 12 checks the identification data ID of the corrected synchronization block near the area where the data flag D_E changes from 'low' to 'high', generates a write address, and outputs a read address. That is, when the error correction flag CORRECT_F is 'high' after the internal decoding of the synchronization block, the identification data ID is indexed to jump the address by the number of the synchronization blocks missed by the synchronization detection unit 10, and the track memory A is separated from the internal memory. Write to B (14.15), and at the time of read, sync blocks not read from the tape are filled with dummy data and sent to the external decoder 16 for correction. The external decoder 16 inputs the output of the control unit 12, decodes it, and outputs error-corrected data.

4A to 4F are waveform diagrams showing signals of respective parts of FIG. FIG. 4A shows a data flag D_E representing data excluding 2 bytes of sync data in each sync block, FIG. 4B shows an error correction flag CORRECT_F, and FIG. 4C shows an error correction flag CORRECT_F. 4C shows an identification flag ID_F indicating the position of two bytes of identification data ID per sync block. Since the identification flag ID_F in FIG. 4C did not detect two sync blocks at the beginning of the track, it can be seen that only 154 sync blocks were detected. FIG. 4d shows the recovered data flag D_E1, and FIG. 4f shows the data DATA. In FIG. 4D and FIG. 4E, the 'C' section is a section in which the synchronous blocks which were not detected are recovered, and two synchronous blocks (first and second synchronous blocks) are recovered so that 156 synchronous blocks are stored in the external decoder 16. You can see that the output is In addition, the hatched portions in Fig. 4f represent dummy data.

As described above, according to the present invention, the system is stabilized by maintaining the synchronization block by recovering and decoding the synchronization block that is not detected at the beginning of the track.

Claims (2)

An error correction decoder of a digital video cassette recorder which recovers and decodes a synchronous block which has not been detected by inputting reproduction data, comprising: a synchronization detection unit for inputting the reproduction data, searching for the synchronization block, and outputting a synchronization flag, a clock, and data; An internal decoder configured to input an output of the synchronization detector to output a data flag, an error correction flag, an identification flag, a clock, and data; A ROM storing an address to be written to as a lookup table; A plurality of memories for storing sync block data at an address obtained from the lookup table; Input the output of the internal decoder to generate an address to access and write the ROM according to the error correction flag and the identification data, and perform an address jump by the number of recovery blocks missed when writing to the one memory according to the address; A control unit which fills a block to be restored at the time of reading from the other memory with dummy data and outputs a restored data flag, data and a clock; And an external decoder which recovers and decodes the sync block as an output of the controller. 2. The error correction decoder of claim 1, wherein the plurality of memories toggle reads and writes to rearrange and store data of a sync block.