KR20010017823A - Data recording and playing method for digital data recording/playing apparatus - Google Patents

Abstract

PURPOSE: A method for recording and reproducing data is provided to reduce error rate while reproducing by recording a specific data in a dummy packet at absence of data to be recorded. CONSTITUTION: By emptiness of a smooth buffer, a dummy mark is displayed in a head for reading a prior synchronizing block data to record the header. Otherwise, the dummy mark is cleared for reading a synchronizing block data to record the header. To reproduce the data, error of a first synchronizing block is corrected by ECC inner decoding for writing the ECC result in a memory. By incorrectness of the error, a second synchronizing block is corrected. By incorrectness of the error in the second block, ECC fail information is marked in the second synchronizing block in the memory. Otherwise, the second synchronizing block is decided as a dummy data to write the ECC decoding result of the second synchronizing block in the memory of the first synchronizing block.

Description

DATA RECORDING AND PLAYING METHOD FOR DIGITAL DATA RECORDING / PLAYING APPARATUS}

The present invention relates to a data recording and reproducing method of a digital data recording and reproducing apparatus. In particular, when there is no data to be recorded, the data recording and reproducing apparatus of the digital data recording and reproducing apparatus can reduce the error rate during reproduction by recording specific data in a dummy packet. It relates to a regeneration method.

In general, the data recording and reproducing apparatus takes out the contents of the smooth buffer at a predetermined rate during recording and processes the contents according to the recording format. When the smooth buffer is empty due to the low input rate, an empty packet is stored as a dummy packet. In place of MPEG TP, the dummy data is removed during reproduction, and only MPEG TP is transmitted to the output terminal. Such a prior art will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a detailed configuration of a general digital VRF format processing unit. As shown in FIG. 1, a sms buffer 10 sequentially receiving and storing an MPEG is used to control the memory controller 11. ECC outer encoder 12 which receives the data of the smooth buffer 10 and performs error correction, and receives data of the ECC outer encoder 12 and corrects the error by the control of the memory controller 11. ECC inner encoder 13 for performing the operation, the synchronization and ID inserting unit 14 for receiving the data of the ECC inner encoder 13, and adding a synchronization signal and ID to record on the tape, and the data recorded on the tape ECC inner deco, which receives data from the synchronization and ID detection unit 15 to detect the synchronization signal and ID, and decodes the error correction. 16, the ECC outer decoder 17 which receives data of the ECC encoder decoder 16 under the control of the memory controller 11 and performs decoding for error correction, and the ECC outer decoder 17 of the ECC outer decoder 17; It is composed of a disbuffer buffer 18 which receives data under the control of the memory controller 11 and sequentially stores the data. The operation of the recording and reproducing method of the apparatus configured as described above will be described.

First, when recording data on a tape, the format processing unit receives an MPEG (TPEG TP) from the broadcast receiving apparatus and converts it into a recording format of the tape, that is, records the MPEG (10) of the program input to the smooth buffer 10 ( After the MPEG TP is sequentially stored, the data of the smooth buffer 10 is taken out at regular intervals by the control of the memory controller 11 and subjected to an encoding process for error correction.

At this time, in the encoding process, ECC outer encoding is sequentially performed after predetermined control of the memory controller 11, and then ECC inner encoding is performed. Then, the synchronization and ID inserting unit 14 receives the data corrected through the error correction. The synchronization signal and ID are inserted to record the data on the tape.

When the tape recorded on the tape is played back, the synchronization and ID detection unit 15 receives the data read from the tape, detects the synchronization signal and the ID, and then decodes the inner error correction by the predetermined control of the memory controller 11. After the outer error correction decoding process is performed sequentially, the outer error correction decoding process is sequentially performed, and the data stored in the disbuffer buffer 18 is output while maintaining the same time difference as the input time of the MPEG tip during recording.

The data generated during the recording and reproducing process as described above is not the MPEG data, but during recording, the memory controller 11 reads and processes the contents of the smooth buffer 10 at a constant rate.

That is, when the smooth buffer 10 is empty because the input rate is low, the dummy packet is recorded instead of the MPEG. The dummy packet should be indicated in the sync block and the header data portion as shown in FIG.

Here, Fig. 5 shows the relationship between the recording rate and the recording time recorded in the VRT, which can record 49 hours in the LS mode, about 7 hours in the standard STD mode, and about 3.5 hours in the HS mode of high quality recording. In all of the above modes, the data recorded on the VRC is not always input at the recording rate, and the input rate is high and the data input at any moment may be lower than the recording rate. Is recorded.

At the time of reproduction, the memory controller 11 refers to the dummy display unit of the header data of the reproduced sync block and stores the result in the dispers buffer 18 because it is an MPEG if it is not dummy data, and discards it if it is dummy data. .

That is, the dummy packet recorded when the case where the input rate is lower than the recording data rate continues to fill a packet with meaningless data together with the dummy mark in the related art.

In addition, the data of which synchronization and ID are detected is subjected to inner decoding in order to perform error correction.

However, in the prior art as described above, when error correction is performed on data detected by synchronization and ID, the error correction is performed in the ECC encoder and the error correction is performed again in the ECC outer decoder. The outer decoder has a problem in that the error correction cannot be performed when the range is exceeded because the error correction is limited.

Accordingly, the present invention devised in view of the above-described problems provides a data recording and reproducing method of a digital data recording and reproducing apparatus in which there is no data to be recorded so that specific data can be recorded in a dummy packet to lower an error rate during reproduction. The purpose is.

1 is a block diagram showing the configuration of a general digital V seed.

2 is a schematic diagram showing the structure of sync block data;

Fig. 3 is a schematic diagram showing the structure of a header in Fig. 2;

4 is a schematic diagram showing the structure of an ECC block for error correction;

Fig. 5 shows the relationship between the recording rate and digital recording time of a digital V seed.

Fig. 6 is an operational flowchart of the data recording method of the digital data recording and reproducing apparatus of the present invention.

Fig. 7 is an operation flowchart of a data reproducing method of the digital data recording and reproducing apparatus of the present invention.

***** Description of the symbols for the main parts of the drawings *****

10: Smooth Buffer 11: Memory Controller

12: ECC outer encoder 13: ECC inner encoder

14: Synchronization and ID insertion unit 15: Synchronization and ID detection unit

16: ECC inner decoder 17: ECC outer decoder

18: smooth buffer

According to the present invention for achieving the above object, if the smooth buffer is empty due to low input rate, a dummy mark is displayed in the header, and then the previous sync block data is read and the header is pasted and recorded in the data of the previous sync block. Steps; If the smooth buffer is not empty, the second step of clearing the dummy mark of the header and reading one sync block data and attaching the header to the data of the sync block is performed.

In order to achieve the above object, the present invention writes the ECC result in the memory when the error is corrected by ECC inner decoding on the first sync block in which the sync and the ID are detected. A first step of determining whether the error is corrected by ECC inner decoding; If the error correction is not corrected for the second sync block as a result of the determination in the first step, the ECC fail information is marked on the second sync block and written to the memory. If the second sync block is error corrected, the second sync block is written. Determining whether the data is dummy data; If the second sync block is not dummy data, the ECC fail is marked and written to the memory. If the second sync block is dummy data and error is corrected, the ECC decoding result for the second sync block is written. A third step of writing to the memory of one sync block is performed.

Hereinafter, operations and effects of the data recording and reproducing method of the digital data recording and reproducing apparatus according to the present invention will be described in detail with reference to the accompanying drawings.

The apparatus structure of the present invention for digital VRC data recording and reproducing method is the same as that of FIG.

6 is a flowchart illustrating a data recording method of the digital data recording and reproducing apparatus according to the present invention. As shown in FIG. 6, when the smooth buffer 10 is empty because the input rate is low, a dummy mark is displayed on the header to display previous sync block data. Reading and attaching the header to data of the previous sync block; If the smooth buffer 10 is not empty, a second step of clearing the dummy mark of the header, reading one sync block data, and attaching the header to the data of the sync block is performed.

7 is a flowchart illustrating a data reproducing method of the digital data recording and reproducing apparatus according to the present invention. As shown in FIG. Writing and if it is not error corrected, then determining whether the error is corrected by ECC inner decoding the second sync block; If the error correction is not corrected for the second sync block as a result of the determination in the first step, the ECC fail information is marked on the second sync block and written to the memory. If the second sync block is error corrected, the second sync block is written. Determining whether the data is dummy data; If the second sync block is not dummy data, the ECC fail is marked and written to the memory. If the second sync block is dummy data and error is corrected, the ECC decoding result for the second sync block is written. A third step of writing to the memory of one sync block will be described.

First, in the case of recording data, the MPEG data is received from the broadcast receiving apparatus, converted into a recording format of the tape, and recorded on the tape, that is, the MPEG data of the selected program is stored in the smooth buffer 10 and the stored data is stored. Under the control of the memory controller 11, the data is read at regular intervals, subjected to ECC inner encoding, and then subjected to ECC outer encoding. An ID and a synchronization signal are added to the recording data and recorded on the tape.

At this time, if the smooth buffer 10 is empty because the input rate is low as shown in FIG. 6, the dummy mark is displayed on the header, the previous sync block data is read, the header is added to the data of the previous sync block, and the smooth buffer is reversed. If (10) is not empty, the dummy mark of the header is cleared, one sync block data is read, and the header is added to the data of the sync block.

When data is reproduced from the tape, the data read from the tape is ECC inner decoded after ECC inner decoding is performed after the synchronization signal and ID are detected and stored in the smooth buffer 18, and then the smooth buffer ( The data stored in 18) is output from the broadcast receiving apparatus while maintaining the same time difference as the input time of the tip packet.

Here, the data recorded on the tape and outputted are not all MPEG data, that is, during recording, the memory controller 11 processes the data stored in the smooth buffer 10 at a constant rate.

When the input rate of the data stored in the smooth buffer 10 is low and empty, the empty packet is recorded as a dummy packet instead of an MPEG. In this case, the sync block header data portion of FIG. 3 indicates a dummy packet.

Then, the memory controller 11 controls to store in the buffer buffer 18 because it is an MPEG if the header data of the reproduced sync block is not displayed, and discards if it is displayed.

Here, the ECC inner decoding process at the time of reproduction is explained in detail with reference to the flowchart of FIG.

First, the data of which synchronization and ID are detected performs inner decoding to perform error correction. If the error is corrected, the data is subjected to ECC outer decoding once again under the control of the memory controller 11, and then a dispers buffer ( 18) is outputted to the tippy stream, and if the error correction is not corrected, the data subjected to the ECC inner decoding is subjected to error correction through ECC outer decoding once again, wherein the error correction is performed using the ECC outer decoding. There is a limit, so if this limit is exceeded, error correction cannot be performed.

Accordingly, the error correction can be performed within the error correction range of the ECC outer decoding by performing a lot of error correction by the ECC inner decoding.

That is, when the first sync block data having detected sync and ID is error corrected through ECC inner decoding, the ECC result is written to the memory. If the first sync block data is not error corrected, the second sync block is then ECC inner. Decode and perform error correction.

Next, if error correction is not performed on the second sync block, the ECC fail information is marked on the second sync block and written to the memory. If the second sync block is error corrected, the second sync block is dummy data. If it is determined that the second sync block is not dummy data, an ECC fail is marked and written to the memory. If the second sync block is dummy data and error correction is performed, the ECC decoding result for the second sync block is determined. 1 Write to the memory of the sync block.

On the contrary, if the second sync block is dummy data and no error correction is made, the ECC fail information is marked and written to the memory.

Thereafter, the ECC outer decoding is performed by the memory controller 11. That is, the completed data of the ECC inner decoding is stored in the memory and decoded one by one in the outer vertical direction when the ECC block is full.

At this time, the bit set among the eraser array bits to perform the erasure decoding means that the inner decoding of the inner data has failed.

Since the input data is not always input at a constant ratio, a smooth buffer 10 is provided to buffer these data. If the input data is momentarily large, the smooth data is stored in the smooth buffer 10 until the data is written. If data is continuously input even after the size of the smooth buffer 10 is exceeded, this data is discarded without being recorded.

Contrary to the above, if the recording speed is constant but the input data is not instantaneously, there is no data to be instantaneously recorded on the tape. In this case, random data is recorded and this is called dummy data, and dummy data is displayed in the header as shown in FIG. do.

4 shows a configuration of an ECC block for performing ECC outer decoding.

In other words, when the dummy data is recorded as necessary, the present invention records the inner data of the previous sync block immediately after the dummy data and vice versa. Then, the error of the sync block is corrected, and if the sync block is dummy data, it is determined to be the same as the error correction of the previous stage, and the ECC decoding result is written to the memory of the sync block of the preceding stage.

As described in detail above, the present invention performs inner decoding by using dummy data during reproduction, thereby improving the efficiency of error correction, which is a performance indicator of digital VRF, and when there is a large amount of dummy data in the VDL recorded data. In other words, the lower the input data rate, the lower the error rate.

Claims (3)

If the smooth buffer is empty because the input rate is low, a first step of displaying a dummy mark on the header, reading previous sync block data, and attaching the header to the data of the previous sync block; And if the smooth buffer is not empty, performing the second step of clearing the dummy mark of the header and reading one sync block data and pasting the header to the data of the sync block. . If the error is corrected by ECC inner decoding for the first sync block in which the sync and ID are detected, the ECC result is written to the memory. If the error is not corrected, the second sync block is then ECC inner decoded to determine whether the error is corrected. Step 1; If the error correction is not corrected for the second sync block as a result of the determination in the first step, the ECC fail information is marked on the second sync block and written to the memory. If the second sync block is error corrected, the second sync block is written. Determining whether the data is dummy data; If the second sync block is not dummy data, the ECC fail is marked and written to the memory. If the second sync block is dummy data and error is corrected, the ECC decoding result for the second sync block is written. And a third step of writing to the memory of the first sync block. 3. The data reproduction method of a digital data recording and reproducing apparatus according to claim 2, wherein if the second sync block is dummy data and error correction is not performed, the ECC fail information is marked and written to the memory.