JP3292092B2 - Data processing controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing control device, and more particularly to a data processing control device having a feature in generating a checksum for error detection.

[0002]

2. Description of the Related Art Conventionally, a data processing control device is disclosed in
What is described in -281277 is known.

A conventional data processing control device will be described with reference to FIG. In FIG. 4, the syndrome calculation circuit 13 calculates a syndrome for the frame data group stored in the buffer memory 11, finds an error pattern, performs a correction process in the error correction circuit 14, and stores the error pattern in the buffer memory 11. Then, the checksum generation circuit 15 generates an error detection code for the corrected frame data, and compares the error detection code with reference data from another system in a comparator 16 to obtain the frame data. This is a system that detects whether there is an error in the system. Here, the bus arbiter 12 includes a syndrome calculation circuit 13, an error correction circuit 14, and a checksum generation circuit 15.
Arbitration in response to an access request to the buffer memory 11 from the server.

The syndrome calculation circuit 13 reads the frame data and accompanying parity data from the buffer memory 11 and performs a syndrome calculation for error correction to generate an error position and an error code for a series of data strings to be corrected. The error correction circuit 14 reads the error position data from the buffer memory 11 and writes the read data and an ExOR value of the error code (corrected data) in the original position of the buffer memory 11.

The checksum generation circuit 15 reads data sequentially from the head of the frame and performs checksum generation processing on the entire error-corrected frame data in the buffer memory 11. In the checksum generation processing, the ExOR of all the data of the frame is calculated, and the ExOR value (checksum value or the same as the error detection code) is transferred to the comparator 16.

The comparator 16 compares the ExOR value (checksum value or the error detection code) of all the frame data generated by the checksum generator 15 with reference data from another system, and determines the error in the frame data. Detection is performed.

To show a specific example, the buffer memory 11
FIG. 3 shows a configuration example of the frame data string and the parity data associated therewith. The frame data is composed of 16 symbols D0 to D15. Parity data is in four or five columns, and is prepared for each row. For example, parity data P0 and P1 correspond to symbols D0, D4, D8 and D12. Similarly, D1, D5, D9, D
13, P2 and P3 are D2, D6, D10, D14
P4 and P5 correspond to D3, D7, D11 and D15, respectively. First, the data in the 0th row from the buffer memory 11 is D0, D4, D8, D
12, P0, and P1 are read into the syndrome calculation circuit 13 in order, and the syndrome calculation circuit 13 performs the syndrome calculation, and generates an error symbol position and an error code for correcting the error symbol.
For example, if the erroneous symbol is D4 and the error code is X, the error correction circuit 14
Is read, and the ExOR value of D4 and X is calculated,
The ExOR value is overwritten on the position D4 in the buffer memory 11, whereby D4 is corrected. Below, 1, 2, 3
The same processing is performed for rows. Next, the checksum generation circuit 15 converts the error-corrected frame data D0 to D15 of the buffer memory 11 into D0, D1, D2, D3,
D4, D5, D6, D7, D8, D9, D10, D1
1, in order of D12, D13, D14, D15,
Calculate ExOR of all symbols D0 to D15,
The ExOR value is transferred to the comparator 16. The comparator 16 compares the ExOR value with reference data (a checksum value serving as a reference) from another system. If the values match, the frame data is regarded as normal. If not, it is determined that a data error exists. .

[0008]

However, in the above conventional configuration, when processing one frame data, the syndrome calculation circuit and the checksum generation circuit access the buffer memory separately, and the buffer memory Access frequency increases.

SUMMARY OF THE INVENTION In view of the above problems, the present invention reduces the total number of accesses to the buffer memory by simultaneously processing the syndrome calculation and checksum generation and eliminating access to the buffer memory of the checksum generation circuit. It is the purpose.

[0010]

In order to solve the above-mentioned problems, a data processing control device according to the present invention includes a syndrome calculating means for correcting an error of frame data, an error correcting means , In a data processing device comprising a checksum generating means for generating a checksum of data, an error from the buffer memory is generated.
The frame data before correction is
ExOR processing of one frame of the checksum generation means
While simultaneously input to the section, the error co of the checksum generation means generates an error code in the error correction means
Ex of the one frame input to ExOR processing unit over de
The output of the OR processing unit and the EXOR processing unit of the error code
It is characterized by having a checksum generating means for generating a checksum by obtaining an exclusive OR with an output .

According to the present invention, it is possible to provide a data processing control device capable of reducing the number of times of access to the buffer memory and reducing the time required for error correction processing and error detection processing for frame data.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment) An embodiment of the present invention described in claim 1 of the present invention will be described below with reference to FIGS. 1, 2 and 3. FIG.

FIG. 1 shows a configuration of a data processing control device according to the present invention, FIG. 2 shows a checksum generation circuit, and FIG. 3 shows an arrangement diagram of frame data and parity data on a buffer memory.

In FIG. 1, a difference from the conventional configuration is that a checksum generation circuit 15 for inputting frame data from a buffer memory 11 and generating an error detection code (same as a checksum value) is used for a syndrome calculation circuit 13.
Is input as input data (1A) and the error code (1B) generated by the error correction circuit 14. Here, the syndrome calculation circuit 13, the error correction circuit 14, and the checksum generation circuit 15 access the buffer memory 11 via the bus arbiter 12.

The syndrome calculation circuit 13 reads the frame data and parity data from the buffer memory 11 and performs a syndrome calculation for error correction to generate an error position and an error code for a series of data strings. The data at the error position is read from the buffer memory 11, and the read data and an ExOR value of the error code (corrected data) are written to the original position of the buffer memory 11.

At the same time as the above processing, the frame data read by the syndrome calculation circuit 13 is simultaneously input to the checksum generation circuit 15, and the checksum generation circuit 15
Calculates ExOR for all frame data (1A) before error correction, and calculates ExOR for all error codes (1B) generated by the error correction circuit 14,
Further, by calculating the ExOR of the two ExOR values, the same checksum value for the data after error correction as in the checksum generation circuit of the conventional embodiment is output. The output data is compared with reference data from another system by the comparator 16 to detect an error in the frame data.

FIG. 2 shows the internal configuration of the checksum generation circuit 15. The conventional checksum generation circuit has only the configuration of the one-frame ExOR processing unit 31 in FIG. 2, but the checksum generation circuit 15 in the embodiment of the present invention.
Has a configuration in which an ExOR processing unit 32 for error codes is added to the ExOR processing unit 31 for one frame. The input data of the syndrome calculation circuit 13 is input to an input terminal 3A of the checksum generation circuit 15, an ExOR calculation of one frame data is performed, and an error used by the error correction circuit 14 at the time of data error correction is input to the input terminal 3B. A code is input, and ExOR calculation of all the error codes generated for one frame is performed. The ExOR operation of the two ExOR calculated values is E
The calculation is performed by the xOR circuit 33, and the calculation result is output to the output terminal 3C. The checksum value of the output terminal 3C is the same as the checksum value for the error-corrected data output from the checksum generation circuit 15 in the conventional embodiment.

A specific example will be described. As shown in FIG. 3, the data structure of the frame data and parity data existing in the buffer memory 11 is the same as that of the conventional embodiment. First, the data in the 0th row from the buffer memory 11 is read into the syndrome calculation circuit 13 in the order of D0, D4, D8, D12, P0, and P1, and is also read into the checksum generation circuit 15. The syndrome calculation circuit 13 performs a syndrome calculation for the six symbols, and generates an error symbol position and an error code for correcting the error symbol. At the same time, the checksum generation circuit 15
Calculate the ExOR of 0, D4, D8, and D12 and calculate the ExOR
The OR value A0 is temporarily stored. The error correction circuit 14 performs the same error correction processing as in the conventional example using the error symbol position and the error code for correcting the error symbol, and generates a checksum for the error code. Transfer to the circuit 15. The checksum generation circuit 15 temporarily holds the error code B0.

Next, also in the first row, the syndrome correction circuit 13 and the error correction circuit 14 perform the same error correction processing as described above, and the error correction circuit 14 transfers the error code B1 to the checksum generation circuit 15. At the same time, the checksum generation circuit 15 performs an ExOR operation on the D1, D5, D9, and D13 and the five symbols A0 temporarily held last time.
Is calculated, and the ExOR value A1 is temporarily stored, and the ExOR of the error code B1 from the error correction circuit 14 and the temporarily stored B0 last time is calculated.
The xOR value is held as B1.

Next, in the second row, the syndrome correction circuit 13 and the error correction circuit 14 perform the same error correction processing as described above, and the error correction circuit 14 transfers the error code B2 to the checksum generation circuit 15. At the same time, the checksum generation circuit 15 outputs D2, D6, D10, D14, and the ExO of the five symbols A1 that were temporarily held last time.
R is calculated and the ExOR value A2 is temporarily held, and the ExOR of the error code B2 from the error correction circuit 14 and the temporarily held B1 last time is calculated, and the ExOR value is held as B2. Keep it.

Finally, in the third row, the same error correction processing as described above is performed by the syndrome calculation circuit 13 and the error correction circuit 14, and the error correction circuit 14 transfers the error code B3 to the checksum generation circuit 15. At the same time, the checksum generation circuit 15 outputs D3, D7, D11, D15,
And the five-symbol Ex of A2 previously held temporarily
OR is calculated and the ExOR value A3 is temporarily held, and the EXOR of the error code B3 from the error correction circuit 14 and the temporarily held B2 last time is calculated, and the ExOR value is held as B3. Keep it. Finally, the checksum generation circuit 15 holds A3, which is the ExOR value of all the symbols of the frame data before error correction, and the ExOR value B3 of all the error codes output by the error correction circuit 14, and stores A3 and B3. The ExOR value is transferred to the comparator 16. Here, E3 of A3 and B3 output to output terminal 3C
The xOR value is the same value as the output of checksum generation in the conventional example.

As described above, according to the embodiment of the present invention, the input to the syndrome calculation circuit 13 and the input to the checksum generation circuit 15 are simultaneously input to the checksum generation circuit 15 according to the conventional embodiment. This eliminates the need for accessing the buffer memory 11 and improves the bus utilization efficiency.

[0023]

As described above, according to the data processing control device of the present invention, the number of accesses to the buffer memory is reduced, and the time required for error correction processing and error detection processing for frame data can be reduced. Equipment can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data processing control device according to an embodiment of the present invention.

FIG. 2 is a block diagram of a checksum generation circuit used in the configuration of the present invention.

FIG. 3 is a layout diagram of frame data and parity data on a buffer memory.

FIG. 4 is a block diagram showing a configuration of a conventional data processing control device.

[Explanation of symbols]

 Reference Signs List 11 buffer memory 12 bus arbiter 13 syndrome calculation circuit 14 error correction circuit 15 checksum generation circuit 16 comparator 31 ExOR processing unit for one frame 32 ExOR processing unit for error code 33 ExOR circuit

Continuation of the front page (58) Fields investigated (Int. Cl. ⁷ , DB name) H03M 13/00 G06F 11/10 310 G11B 20/00 H04L 1/00

Claims (1)

(57) [Claims] A syndrome calculating means for correcting an error of frame data via a buffer memory and an error correction
Ji performing checksum generation means and the frame data
A data processing apparatus comprising a Ekkusamu generating means, as well as simultaneously input error correction previous frame data from the buffer memory to the ExOR section of one frame of the checksum generation means and said syndrome calculating means, said error correction means Generate an error code at
ExOR processing error code of the checksum generation means
The output of ExOR section of the one frame input to part
Exclusive logic of the error code with the output of the ExOR processing unit
Checksum to generate a checksum by the sum
A data processing control device characterized by generating means .