JP2001237715A - Decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a decoder which can perform error correction/descrambling processing of a product code at a high speed. SOLUTION: Data is read from a buffer memory 11 and data subjected to error correction processing by an error correction circuit 12 is used directly. A descrambling circuit 13 performs a descrambling processing without accessing the buffer memory 11 again.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a decoding apparatus and a decoding method for descrambling and error correction in a data transfer system, and more particularly to descrambling of data including a multidimensional error correction code such as a product code. The present invention relates to a decoding device and a decoding method for processing.

[0002]

2. Description of the Related Art As recording, reproduction, and transmission of video information having a large amount of information have been performed as digital signals, error correction has been performed in order to increase the reliability of recorded information or transmitted information. And the importance of error checking increases. In particular, when real-time recording or reproduction is required, high-speed processing is required to perform error correction and inspection for such a large amount of information.

A conventional data transmission system, for example, a recordable / reproducible magneto-optical disk device, adds an error correction code composed of a product code to received data and stores the data on a recording medium. Here, the data stored in the recording medium is scrambled in advance and subjected to error correction coding. Thereafter, the stored data is called to an error correction device as necessary, and after error correction, descramble processing is performed and output to the outside.

Similarly, in a read-only optical disk device, stored data is called to an error correction device as necessary, and after error correction, descramble processing is performed and output to the outside.

[0005] In a conventional error correction system, for example, in a DVD (Digital Video Disc), data called from a disk is once stored in, for example, an SDRAM.
(Synchronous Dynamic Random Access Memory). Thereafter, the data is read by the error correction device, and the error is corrected. Here, for example, in a DVD, a product code is used in which data is arranged in a rectangular shape and error correction codes in two directions of a vertical direction (hereinafter also referred to as a PO direction) and a horizontal direction (hereinafter also referred to as a PI direction) are added. .

FIG. 12 is a schematic block diagram showing a configuration of a conventional error correction apparatus 2000 for realizing the above-described error correction calculation.

Referring to FIG. 12, error correction device 2000
In, the data read into the external memory 21 is first subjected to error correction by the error correction circuit 22.

The error correction circuit 22 reads data from the external memory 21 and corrects the error.
The data after the error correction is written again in.

Subsequently, after all errors have been corrected, a descrambling operation is next performed in the descrambling circuit 23.

The descrambling circuit 23 is connected to the external memory 2
After reading data from 1 and performing descrambling conversion,
The descrambled data is written into the external memory 21 again.

That is, the basic processing pattern for decoding is based on the following procedure.

1. External memory (for example, SDRAM)
The data in the PI direction is read from 21 to calculate the syndrome.

2. The error amount and error position are calculated from the syndrome value, and the error is corrected on the external memory 21.

3. Next, data in the PO direction is read from the external memory 21 to calculate a syndrome.

4. The error amount and the error position are calculated from the syndrome value, and the error is corrected for the data stored in the external memory 21.

An error is corrected by repeating these processes. 5. After these error corrections are completed, the external memory 21
Data (D ′ _k : data _obtained by scrambling the data D _k is represented by D′ _k ) is read out, and the descrambling processing circuit 23 performs descrambling based on the following equation.

D _k = D ′ _k Exor S _k (k = 0 to 2047) (1) Here, S 0 is given as an initial value by a table prepared in advance. Further, the data D'k is descrambled using the data Sk given by the following equation.

T ₀ = {7′d0, S0} (2) T _{n + 1} [14: 0] = {T _n [13: 1], (T _n [14] Exor T _n [10]) ３ (3) (n = 0 to 8 × 2047) S _k = T _8k [7: 0] (4) Here, in the equation (2), “7′d0” is 7 when data “0” is 7 means that line up pieces, formula (2), this seven "0", by connecting the S0 given as an initial value, up to the 14 to 0th bits, a 15-bit data T ₀ Means that

Equation (3) is obtained from the 13 th bit to the 13 th bit of the data T _n [14: 0] generated at the n-th step.
Data T _n [13: 0] up to the 0th bit and data T _n
The 14th bit data T _n [1] of [14: 0]
4] and the result of the exclusive OR operation of the tenth bit data T _n [10] are arranged in the (n + 1) th step, so that the data T consisting of the 15th bit from the 14th bit to the 0th bit is obtained. _{n + 1} [14: 0] is generated.

Further, equation (4) shows that among the data T _n [14: 0] generated in this way, the seventh to the seventh bits of data T _8k [14: 0] formed in steps of multiples of 8
This indicates that the data up to the 0th bit corresponds to the data _Sk .

[0021]

However, in the circuit configuration shown in FIG. 12, the amount of access to the external memory becomes enormous, which takes time, and it is difficult to speed up error correction and descrambling processing. Met.

Next, a conventional technique for solving such a problem will be further described.

FIG. 13 is a schematic block diagram showing the configuration of an error correction device 3000 disclosed in Japanese Patent Application Laid-Open No. 10-126279 as such a conventional technique.

Referring to FIG. 13, first, external memory 31
First, the syndrome calculation circuit 32, which is a part of the error correction calculation, performs the syndrome calculation.

At this time, the read data is sent to the descrambling circuit 33 at the same time, and the descrambling process is performed. The data for which the descrambling process has been completed is written to the external memory 31.

Thereafter, the syndrome obtained by the syndrome calculation is sent to the error amount calculator 34, and the error position and the error amount are calculated. The error amount calculator 34 calculates
The data corresponding to the error position is read from the external memory 31, and after correcting the error, the data is written to the external memory 31 again.

According to such a method, the amount of access to the external memory is reduced by about 2/3, but is not yet a sufficient amount.

No consideration is given to repetition processing peculiar to product codes, and it is difficult to effectively perform error correction / descrambling processing on an actual DVD or the like.

That is, in a product code, error correction is generally performed a plurality of times in each direction (PO direction and PI direction). Here, since the syndrome calculation for performing error correction is performed using data before descrambling, if the descrambling process is performed as shown in FIG. 13, it is necessary to repeatedly perform the next error correction. Requires that the data stored in the external memory 31 be re-scrambled, resulting in an increase in the amount of calculation and the circuit scale.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a decoding device capable of processing error correction and descrambling of a product code at high speed. It is to be.

[0031]

According to a first aspect of the present invention, there is provided a decoding apparatus for decoding data including an error correction product code, wherein the control means controls the operation of the decoding apparatus, and the data is transmitted. A first storage element for temporarily storing data, an error correction means for performing an error correction process on data read into the first storage element, and a descrambling for data stored in the first storage element Descrambling means for performing processing, the control means causes the error correction means to perform error correction processing on the data read into the first storage element, and the data after the error correction processing is transmitted to the descrambling means. After transferring and descrambling the data after the error correction processing, the data is written back to the first storage element.

According to a second aspect of the present invention, in addition to the configuration of the first aspect, the error correction means temporarily stores the unit data for the error correction process read from the first storage element. A second storage element for storing; and an error correction operation unit for performing an error correction process on data in the second storage element.

According to a third aspect of the present invention, there is provided a decoding device for decoding data including a product code for error correction, wherein the control unit controls the operation of the decoding device and temporarily stores the transferred data. A first storage element for performing error correction processing in a first direction on data read from the first storage element, a descrambling means for performing descrambling processing on the data, Second error correction means for receiving an error correction processing result in the first direction and performing error correction processing in the second direction, wherein the control means reads i) the data read from the first storage element. After performing the first-direction error correction processing on the data, the descrambling means performs the descrambling processing on the data after the first-direction error correction, and ii) converting the descrambled data. Written back to one storage element, iii)
In parallel with the descrambling process, the second error correction means performs error correction on data stored in the first storage element, and writes the data back to the first storage element.

According to a fourth aspect of the present invention, in the decoding apparatus, the data including the error correcting product code is subjected to error correction in the first direction and second error correction.
A control device for controlling the operation of the decoding device, a first storage element for temporarily storing transferred data,
First error correction means for performing error correction processing in a first direction on data read from the first storage element, and descrambling means for writing back the result of descrambling the data to the first storage element; And second error correction means for performing error correction processing in the second direction in response to the error correction processing result in the first direction, and receiving data from the first error correction means. When error correction in the first direction is performed, data is supplied to the descrambling means. When error correction in the first direction is not performed last, data is written back to the first storage element. The control means i) performs error correction processing in the first direction on data read from the first storage element, and then supplies the first error correction processing data to the branch means. ii) most When the error correction in the first direction is performed, the descrambling means performs descrambling processing on the data after the error correction in the first direction, and stores the descrambled data in the first storage element. In parallel with the descrambling process, causing the second error correction means to perform error correction on the data stored in the first storage element, and write back to the first storage element.
iii) When the error correction in the first direction performed last is not performed, the data after the error correction in the first direction is stored in the first direction.
Of the data stored in the first storage element, and write back to the first storage element.

According to a fifth aspect of the present invention, in addition to the configuration of the third or fourth aspect of the present invention, in parallel with the descrambling process, the control means sends the first error correction means to the second error correction means. When performing error correction on data stored in the storage element, error correction is performed on data corresponding to the error position obtained in the second error correction processing among the data stored in the first storage element. Let

According to a sixth aspect of the present invention, in addition to the configuration of the third or fourth aspect of the present invention, the second error correction means receives an error correction processing result in the first direction and temporarily And a second storage element for storing data in the first storage unit, based on the data after the error correction in the first direction sequentially transferred from the first error correction unit and the data stored in the second storage element. Syndrome calculation means for calculating a syndrome for error correction in two directions and overwriting the calculation result in the second storage element.

[0037]

[First Embodiment] An error correction and descrambling circuit according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram showing a configuration of a disk reproducing apparatus 1000 provided with an error correction and descrambling circuit according to the present invention.

Referring to FIG. 1, drive drive circuit 149
The data read from the disk by the drive 141 driven by the
Is demodulated. The servo circuit 143 includes the signal reading circuit 14
Drive drive circuit 1 based on the signal read by
49 is controlled.

Data from the disk is read by a signal reading circuit 1
After being demodulated at 42, it is transferred to the data buffer 11 in the decoding circuit 1100. The transferred data is corrected for errors by an error correction circuit 12, subjected to a descrambling process by a descrambling circuit 13, and
The information data is transferred to the host PC via.

In the following description, an apparatus and method for error correction and parallel checking of a product code corresponding to data recorded on a DVD will be described by taking a DVD as an example, but the present invention is limited to such a case. One without
The present invention is applicable to a product code error correction device and an error correction method in which an error correction product code is arranged for block data.

FIG. 2 is a conceptual diagram showing the format of the error correction product code in the DVD shown in FIG. One block consists of two-dimensionally arranged 172 × 192 bytes of information data to which a 10-byte parity PI in the horizontal direction and a 16-byte parity PO in the vertical direction are added.

FIG. 3 is a block diagram for describing a configuration of decoding circuit 1100 shown in FIG. Decoding circuit 11
The operation of 00 is controlled by the decryption processing controller 10.

The decoding circuit 1100 will now be described with reference to FIG.
Will be described.

In the first step, input data is transferred to the buffer memory 11. Here, for example, SD
The RAM is used as the data buffer memory 11.

In the second step, the error correction circuit 12
Data serving as a unit for error correction, for example, data for one codeword is read from the buffer memory 11 and error correction processing is performed. Here, the error correction circuit 12 includes a storage element 12 for temporarily storing data for one codeword before correction.
1 and an error correction operation unit 122, and corrects the data temporarily stored in the storage element 121 with the correction amount obtained by the error correction operation unit 122.

In the third step, the corrected data thus obtained and temporarily stored is sent to the descrambling circuit 13, and the descrambling process is performed.

FIG. 4 is a schematic block diagram for explaining a configuration of descrambling circuit 13. The data input to the descramble circuit 13 is obtained by combining the value obtained from the descramble pattern generator 51 with the exclusive OR operation circuit 5.
The exclusive OR is calculated at 2 and output.
Here, the descramble pattern generator 51 has a DV
D based on the data stored in advance on D
₀ is given.

Returning to the description of the operation of the decoding circuit 1100 in FIG. 3 again, in the fourth step, the data after the descrambling process is written into the buffer memory 11.

With such a circuit configuration, access to the data buffer memory 11 can be reduced to about 1/2. Therefore, it is possible to process error correction and descrambling of the product code at high speed.

[Second Embodiment] FIG. 5 is a schematic block diagram for describing a configuration of a decoding circuit 1200 including a product code error correction and descrambling circuit according to a second embodiment of the present invention.

The operation of the decoding circuit 1200 is controlled by the decoding processing controller 10.

In the second embodiment, the feature of the error correction in the processing of the product code is taken into consideration. As will be described below, the error correction using the product code of the DVD as shown in FIG. In descrambling processing and the like, higher-speed processing can be performed.

The error correction of the product code in the decoding circuit 1200 according to the second embodiment is performed, for example, by using the inner code (P
This is applied when the outer code (PO) is executed after the execution of I).

FIG. 6 is a flowchart for explaining the operation of decoding circuit 1200 according to the second embodiment shown in FIG.

The configuration and operation of decoding circuit 1200 according to the second embodiment will be described below with reference to FIGS.

When the process is started, first, in a first step, input data is transferred to the buffer memory 11 (step S102). Here, for example, an SDRAM is used as the data buffer memory 11.

In the second step, the buffer memory 11
For example, data for one code word necessary for further error correction is read and temporarily stored in the data storage element 41 (step S104).

Subsequently, in the third step, the temporarily stored data is read from the data storage element 41, and the syndrome is calculated in the first syndrome calculation circuit 42 (step S106).

In the fourth step, the calculated syndrome value is sent to the first error amount calculation circuit, and the error amount is calculated (step S108).

Here, if no error exists, it is assumed that the error amount is calculated as “0” in the calculation.

In the fifth step, the error amount thus calculated and the data temporarily stored in the data storage element 41 are subjected to an exclusive OR operation in an exclusive OR operation circuit 47, whereby error correction is performed. All the data obtained are obtained (step S110).

In the sixth step, the corrected data thus obtained is sent to the descrambling circuit 13 (step S112).

Here, the configuration of the descrambling circuit 13 is the same as that of the first embodiment. In the seventh step, the descrambled data is written back to the buffer memory 11 in the descrambling circuit 13 (step S114).

On the other hand, in the eighth step, the data sent to the descrambling circuit 13 in the sixth step is sent to the second syndrome calculation circuit 45 in parallel. Furthermore, the syndrome calculation is performed by the second syndrome calculation circuit 45 by storing the value in the middle of the calculation of the syndrome in the syndrome storage element 44 (step S116).

In the ninth step, the value of the syndrome calculated in this way is sent to the second error amount calculation circuit 46, where the error amount is calculated (step S11).
8).

In the tenth step, the data in the buffer memory subjected to the descrambling process in the seventh step is read only at the position where the second error is detected,
The exclusive OR operation is performed by the exclusive OR operation circuit 48 and written back to the buffer memory 11 (step S1).
20).

In the above processing, in the third step (step S106), the syndrome is calculated in the first syndrome calculation circuit 42, and in the eighth step (step S116), the storage for the syndrome is performed. The processing performed by the second syndrome calculation circuit 45 using the element 44 will be described in more detail as follows.

That is, first, FIG. 7 shows the state shown in FIG.
FIG. 3 is a conceptual diagram showing a data array in data of a block. That is, 208 bytes of data from ROW0 to ROW207 are arranged in the column direction, and 182 bytes of data from COL0 to COL181 are arranged in the row direction.

FIG. 8 is a block diagram showing the structure of the first syndrome calculation circuit 42.

As is well known, when the received polynomial y (x) of a code string containing an error is represented by the following equation (5), the syndrome is given by equation (6).

Y (x) = y _m−1 x ^m−1 + y _m−2 x ^m−2 +... + Y ₁ x + y ₀ (5)

[0073]

(Equation 1)

Where m is the number of terms in the primitive polynomial, and
In the product code block shown in (1), m = 182 when error correction is performed on the line code of the PI sequence, and m = 2 when error correction is performed on the line code of the PO sequence.
08.

Further, t is the number of correctable errors, and α
Is the root of a primitive polynomial. The first syndrome calculation circuit 42 realizes the syndrome calculation formula by a circuit. However, in this case, an exclusive OR operation is performed instead of a simple OR operation.

The first syndrome calculation circuit 42 has n circuits including an exclusive OR circuit 412an, a register 412bn, and a multiplier 412cn.

For example, in the DVD format as shown in FIG. 2, since it is agreed that a parity PI of 10 bytes is added, n = 10 (0 to 9).
This corresponds to j in equation (6).

FIG. 9 is a block diagram showing a configuration of the syndrome storage element 44 and the second syndrome calculation circuit 45. The syndrome storage element 44 includes a storage element 413bm (m = 0 to 15), and the second syndrome calculation circuit 45 includes an exclusive OR operation circuit 413am
(M = 0 to 15) and a multiplier 413 cm (m = 0 to 1)
5).

The second syndrome calculation circuit 45 is the same as the first syndrome calculation circuit 42 in realizing the syndrome calculation of the equation (6), except that the exclusive OR circuit 413am and the storage element 413bm are multiplied. Vessel 413c
m are provided. For example, in the DVD format as shown in FIG. 2, since it is agreed to add a parity PO of 16 bytes, m = 1
6 (0 to 15). The storage element 13bm is for sequentially storing values during the course of calculating the syndrome.
Although not particularly limited, for example, SRAM (Static Rando
m Access Memory).

Based on the above configuration, the syndrome calculation operation will be described according to the steps shown by arrows in FIG.

When a decoding instruction is given from the controller 10 to the decoding circuit 1200, the decoding circuit 1200 starts error correction processing and descrambling processing for one block of product code blocks.

First, the PI series line data of ROW0 in FIG. 7 is transferred from the buffer memory 11 to the data storage element 41, and the first syndrome calculation circuit 42 performs syndrome calculation on the code of the PI series line. Then, an error correction operation is executed by the first error amount calculation circuit 43 and the exclusive OR operation circuit 47.

That is, from the buffer memory 11, FIG.
Data yi for each line of the product code block PI sequence shown in FIG.
(I = 181-0) are sequentially exclusive OR circuits 412an
(N = 0-9), and the operation result is temporarily stored in the register 412bn (n = 0-9). Then, the data accumulated in the register 412bn is multiplied by the multiplier 4
12cn (n = 0~9) by α ^{n (n} = ^0~9) are multiplied and the result and the next data y (i-1) and is calculated by the exclusive OR circuit 412An. By repeating this, the syndrome is calculated.

After calculating the syndrome, the first error amount calculation circuit 43 and the exclusive OR operation circuit 47 perform an error correction operation, and the error correction operation for these PI series lines is completed.

Next, the data corrected for each line from the exclusive OR operation circuit 47 is supplied to the descrambling circuit 13.
And the second syndrome calculation circuit 45
And error correction in the PO direction is executed.

The corrected data from the exclusive OR operation circuit 47 is descrambled by the descrambling circuit 13 and then transferred to the buffer memory 11 and also to the second syndrome calculation circuit 13. You.

Here, the exclusive OR operation circuit 47 outputs the corrected PI series line data yi (i = 181).
To 10) are exclusive OR circuits 413an (n = 0 to 1)
15), and the operation result is stored in the storage element 413bn
(N = 0 to 15).

However, regarding the PI series line data of ROW0, the storage elements 413bn (n = 0 to
Since there is no data stored in 15), the value as it is is stored in the storage element 413bn. That is, at this point, the PI series line data of ROW0 in FIG. 7 is input to the second syndrome calculation circuit 45, and 172 bytes of data are stored in the storage element 413bn.

Next, the PI series line data of ROW 1 is transferred from the buffer memory 11, and the first syndrome calculation circuit 42, the first error amount calculation circuit 43, and the exclusive OR operation circuit 47 transmit the PI series line data. Is performed, the corrected ROW1 data is descrambled by the descrambling circuit 13, transferred to the buffer memory 11, and the error is corrected on the buffer memory 11.

On the other hand, the corrected data from the exclusive OR operation circuit 47 is transferred to the second syndrome calculation circuit 45 at the same time as being transferred to the descrambling circuit 13. Here, first, when y (181) in the PI series line data of ROW1 is input, the second syndrome calculation circuit 45 shown in FIG. 9 stores y (181) (ROW0 of ROW0) stored in the storage element 413bn. PI sequence data) is generated and transferred to the multiplier 413cn (n = 0 to 15), and α ⁿ (n = 0 to ¹ ) is output by the multiplier 413bn.
5), the result and y (181) in the PI series line data of ROW1 are calculated by an exclusive OR circuit 413an, and the value is converted to y (181) stored in the storage element 413bn. Overwrite.

Thereafter, similarly, every time the PI series line data y (i) of ROW1 is input, the storage element 413b
n and reads out the corresponding data from the exclusive OR circuit 41.
The value is overwritten on y (i) stored in the storage element 413bn.

As described above, in the storage element 413bn, new data is only sequentially overwritten.
Bytes (= 182 bytes-10 bytes) × m (= 16)
It is only necessary to provide a very small storage capacity for storing the data of.

By repeating the above operation up to ROW 207 in FIG. 7, P in the product code block is obtained.
The error correction operation for the codes of all the lines of the I series ends, and the syndrome calculation for the codes of all the lines of the PO series ends.

After that, the error amount is calculated in the second error amount calculation circuit 10 and the exclusive OR operation circuit 4
At 8, an exclusive OR operation with the data in the buffer memory 11 is performed, so that error correction in the PO direction is performed.

In the configuration of the decoding circuit 1200 described above, the following operation and effect can be obtained.

(1) The storage element 413bn stores the progress of the calculation of the syndrome, and is configured to be sequentially overwritten each time new data is input, so that it has only a very small storage capacity. And an increase in circuit area and power consumption can be suppressed.

(2) Since the corrected data from the exclusive OR operation circuit 47 is transferred to the second syndrome calculation circuit 45 at the same time as the transfer to the descrambling circuit 13, the corrected data is transferred to the buffer memory 11. , The number of times of access is reduced, and the error correction process can be speeded up accordingly.

[Third Embodiment] FIG. 10 is a schematic block diagram illustrating a configuration of a decoding circuit 1300 according to a third embodiment of the present invention.

The configuration of the decoding circuit 1300 according to the third embodiment is basically the same as the configuration of the decoding circuit 1200 according to the second embodiment, however, as shown in FIG. Whether to perform the descrambling process in response to the request and to perform the second syndrome calculation.
The difference is that a branch circuit 50 for performing one branch process is provided. In other respects, the configuration is the same as that of decoding circuit 1200 of the second embodiment, and therefore the same portions are denoted by the same reference characters and description thereof will not be repeated.

FIG. 11 is a flowchart for explaining the operation of decoding circuit 1300 according to the third embodiment of the present invention.

In the description of the third embodiment, it is assumed that error correction is performed in the order of inner code (PI), outer code (PO), and inner code (PI) of a product code.

In this case, when the first inner code processing is performed in the second embodiment, data is written back to buffer memory 11 without performing descrambling processing.
By performing the descrambling process at the time of the processing of the inner code, the high-speed processing can be realized without increasing the circuit scale.

Referring to FIG. 10, when the process starts (step S400), the input data is transferred to buffer memory 11 (step S402).

Subsequently, error correction processing in the first direction is performed (step S404). Next, in the branch circuit 50, error correction in the second direction is performed, and error correction in the last first direction is performed. It is determined whether or not there is (step S
406, step S408).

If it is determined that error correction in the second direction is to be performed, error correction processing in the second direction is performed (step S410), and then data and error data in the buffer memory after the first correction processing are read. Error correction is performed using the quantity (step S412).

On the other hand, when it is determined whether or not the error correction is in the last first direction (step S408), if it is not the error correction in the last first direction, the buffer memory 1
1 is written into the memory data (step S414), and the process returns to step S402.

On the other hand, if the error correction is the last error correction in the first direction (step S408), a descrambling process is executed (step S416), and data is written to the buffer memory 11 (step S418). Ends (step S420).

It should be noted that when the product code is processed four times in the order of inner code (PI), outer code (PO), inner code (PI), outer code (PO), The same can be applied. in this case,
As described above, in the case of performing the first inner code processing, the data is written back to the buffer memory without performing the descrambling processing, and the descrambling processing is performed in the second inner code processing. Accordingly, high-speed processing can be realized without increasing the circuit scale.

Further, even if the number of correction processes for the inner code or the outer code increases, the same process can be performed.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0111]

As described above, according to the present invention, the descramble processing is performed using the data after error correction read from the data buffer, so that the access to the buffer memory can be reduced by about 1/2. It is possible to cope with high-speed processing of data.

Further, at the time of product code processing, the syndrome of the outer code is calculated based on the data before descrambling, and error correction is performed on the data after descrambling, thereby minimizing access to the buffer memory. Since the configuration is such that the processing is performed while suppressing it, high-speed processing can be performed effectively.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a configuration of a disk reproducing apparatus 1000 provided with an error correction and descrambling circuit.

FIG. 2 is a conceptual diagram showing a format of an error correction product code in a DVD.

FIG. 3 is a block diagram illustrating a configuration of a decoding circuit 1100.

FIG. 4 is a schematic block diagram for explaining a configuration of a descrambling circuit 13;

FIG. 5 is a schematic block diagram illustrating a configuration of a decoding circuit 1200 including a product code error correction and descrambling circuit according to a second embodiment.

FIG. 6 is a flowchart illustrating an operation of a decoding circuit 1200 according to the second embodiment.

FIG. 7 is a conceptual diagram showing a data array in one block of data shown in FIG. 2;

FIG. 8 is a block diagram showing a configuration of the first syndrome calculation circuit 42.

FIG. 9 is a block diagram showing a configuration of a syndrome storage element 44 and a second syndrome calculation circuit 45.

FIG. 10 is a decoding circuit 1300 according to the third embodiment of the present invention.
FIG. 2 is a schematic block diagram for explaining the configuration of FIG.

FIG. 11 is a decoding circuit 1300 according to the third embodiment of the present invention.
5 is a flowchart for explaining the operation of FIG.

FIG. 12 is a schematic block diagram illustrating a configuration of a conventional error correction device 2000.

FIG. 13 is a schematic block diagram illustrating a configuration of a conventional error correction device 3000.

[Explanation of symbols]

Reference Signs List 11 buffer memory, 12 error correction circuit, 13 descramble circuit, 41 data storage element, 42 first syndrome calculation circuit, 43 first error amount calculation circuit, 44 syndrome storage element, 45 second syndrome calculation circuit , 46 second error amount calculation circuit, 47
First error correction operation circuit, 48 Second error correction operation circuit, 1000 disk reproducing device, 1100, 1
200, 1300 Decoding circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toru Arisaka 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hideki Yamauchi 2-5-2 Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. F term (reference) 5J065 AB02 AC03 AD02 AF01 AG02 AH02 AH04 AH16

Claims (6)

[Claims] An apparatus for decoding data including a product code for error correction, comprising: control means for controlling the operation of the decoding apparatus; and a first means for temporarily storing transmitted data. A storage element; error correction means for performing error correction processing on data read into the first storage element; and descrambling means for performing descrambling processing on data stored in the first storage element. The control means causes the error correction means to perform an error correction process on the data read into the first storage element, and transfers the error-corrected data to the descrambling means; A decoding device for causing the data after the correction processing to be descrambled and then writing the data back to the first storage element. A second storage element for temporarily storing unit data for an error correction process read from the first storage element, wherein the error correction means includes: 2. The decoding device according to claim 1, further comprising an error correction operation unit for performing an error correction process on the data. 3. A decoding device for data including an error correction product code, comprising: control means for controlling the operation of the decoding device; and first storage for temporarily storing transferred data. An element; first error correction means for performing error correction processing in a first direction on data read from the first storage element; descrambling means for performing descrambling processing on the data; Receiving the error correction processing result in the second direction,
Second error correction means for performing error correction processing in the direction of: i) performing error correction processing in the first direction on data read from the first storage element. Then, the descrambling means performs a descrambling process on the data after the error correction in the first direction, ii) the data after the descrambling process is written back to the first storage element, and iii) the data In parallel with the scrambling process, the second
A decoding device for causing the error correction means to perform error correction on data stored in the first storage element and writing back to the first storage element. 4. A decoding device for repeatedly performing error correction in a first direction and error correction in a second direction on data including a product code for error correction, the decoding device controlling the operation of the decoding device. Control means; a first storage element for temporarily storing transferred data; and a first error for performing error correction processing in the first direction on data read from the first storage element. Correcting means, descrambling means for writing back the result of descrambling the data to the first storage element, and receiving the error correction processing result in the first direction;
A second error correction means for performing error correction processing in the direction of..., And receiving the data from the first error correction means and performing error correction in the first direction which is performed last. When the data is provided to the scramble means, and the error correction in the first direction which is performed last is not performed, the first
Branching means for writing back the data to the storage element of (i), the control means comprising: i) performing an error correction process in the first direction on the data read from the first storage element; Providing the first error correction processing data to the branching means; ii) when the last error correction in the first direction is performed, the descrambling means provides the data for the data after the error correction in the first direction to the descrambling means. A scramble process is performed, the data after the descrambling process is written back to the first storage element, and the second error correction means stores the data in the first storage element in parallel with the descrambling process. Error correction for the data to be performed, and write back to the first storage element. Iii) If the error correction in the first direction to be performed last is not performed, the error after the error correction in the first direction is performed. The data is written back to the first storage element, and the second error correction means performs error correction on the data stored in the first storage element, and is written back to the first storage element. , Decoding device. 5. The control unit, when causing the second error correction unit to perform error correction on data stored in the first storage element, in parallel with the descrambling process. The decoding device according to claim 3, wherein, of the data stored in one storage element, error correction is performed on data corresponding to an error position obtained in the second error correction processing. 6. The second error correction unit, comprising: a second storage element for temporarily storing a result of the error correction processing in the first direction; Calculating a syndrome for error correction in the second direction based on the error-corrected data in the first direction and the data stored in the second storage element sequentially transferred; The decoding apparatus according to claim 3, further comprising a syndrome calculation unit that overwrites a calculation result in the second storage element.