JP2000251418A - Digital data recording device, its reproducing device and product mark geneating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of accesses between an error correction code generating circuit and a RAM while generating a product code by transmitting a second inspection symbol being generated and the corresponding data or a first inspection symbol to a modulation circuit after generating the second inspection symbol by a second inspection symbol generating circuit. SOLUTION: 16 data sectors are read from a RAM 104 by a modulation block 107, PI computations are conducted and data are converted into one IEC block. Then, an interleave process is executed for every row in a same block to constitute 16 recording sectors and these sectors are modulated to constitute 16 physical sectors. By having a circuit, which conducts a PI computational process in a modulation block 107, against a system, which inserts a PI computing circuit 108 and a PO computing circuit 106 in an error correction code generating block 105, the number of accesses between the block 105 and the RAM 104 and the number of accesses from the RAM 104 to the modulation block are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a digital data recording device, and more particularly to a digital data recording device for recording data with an error correction code added thereto.

[0002]

2. Description of the Related Art In a recording signal format such as DVD and DAT, a product code is used as an error correction code. The product code is made by combining two codes, the encoder and the compounder are relatively simple, and the error correction capability is high. Another feature is that not only random errors but also burst errors can be corrected relatively easily.

A related application of a data transmission apparatus including an error correction code generation circuit for generating a product code is disclosed in Japanese Unexamined Patent Application Publication No.
No. 22197, a frame forming means for forming a frame constituting a product code by a block code, and a sending means for sending data in the same direction as a horizontal coding direction in a frame formed by the frame forming means There is a description of a data transmission device provided with the above.

In a digital data recording apparatus, in order to increase the data recording rate, it is necessary to increase the speed of signal processing in a digital data signal processing circuit. It is also necessary to increase the speed of the error correction code generation circuit that generates the product code.

[0005]

As a process for generating a product code, it is common to store data in a random access memory (RAM) and generate a code for a data string in a different direction while reading the data. It is. For this reason, it is necessary for the RAM to frequently read or write data in different directions. Read RAM /
Write access is affected by the RAM bus width and the number of bytes that can be input / output in one access. Therefore, the speeding up of the data signal processing circuit largely depends on the access control of the RAM.

The conventional method does not disclose a method for reducing the number of accesses between the error correction code generation circuit for generating the product code and the RAM.

An object of the present invention is to reduce the number of accesses between an error correction code generation circuit and a RAM when a product code is generated, thereby shortening the time required for processing for generating a product code.

[0008]

The first aspect orthogonal to the data sequence is described.
A product code generation system for adding a check symbol and a second check symbol, a storage circuit for temporarily storing input digital data, reading data from the storage circuit to generate a first check symbol, and generating A first check symbol generation circuit for writing the obtained first check symbol to the storage circuit, and a second check symbol generation for reading data and the first check symbol from the storage circuit to generate a second check symbol In a digital data recording apparatus including a circuit and a modulation circuit that modulates the data, the first check symbol, and the second check symbol, the second check symbol generation circuit generates a second check symbol. A digital data recording apparatus, wherein the generated second check symbol and data for the second check symbol or the first check symbol are sent to the modulation circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

First, digital data will be described in this embodiment by taking a DVD as an example.

FIG. 2 shows that “1 data sector 208”, “16 recording sectors 212”, “1”
It is a flow chart which showed the order of processing which generates 6 physical sectors 214 ".

In FIG. 2, reference numeral 201 denotes identification data (I
D) and 202 indicate the ID error detection code (IED) 401 as I
Processing added to D201, 203 is ID201 and IED
6-byte data composed of 401, 204 is ID2
01, IED 401, and copyright management information (CPR_MA
I) 2060 composed of 402 and main data 301
Byte data 205 is an error detection code (EDC) 40
3 is added to the data 204, 206 is one data sector before scrambling to add fixed random data, and 207 is the main data 30 included in the data 206.
A process of performing scrambling for adding fixed random data to 1 is performed, 208 is a data sector, 209 is a 16 data sector, and 210 is a process of performing ECC encoding on a 16 data sector 209 (described later with reference to FIGS. 4 to 7). ), 211 is a P
A process of performing interleaving for rearranging each of the 16 rows of O into each data sector of 16 data sectors, 212
Is 16 recording sectors, 213 is 8 in 16 recording sectors 212
/ 16 modulation is performed, and SYNC codes SY0 to SY7 are added to the head of every 91 bytes of the data.
Indicates a physical sector.

By performing the processing shown in FIG. 2 in this way, a disk recording signal (signal to be recorded in physical sector units) is formed from the main data 301.

FIG. 3 shows one data sector 208 created by performing the processing up to the middle stage of the flow shown in FIG.
4 is a flowchart showing signal processing until a is created.

In FIG. 3, reference numeral 301 denotes main data of 2048 bytes; 302, identification data (ID) 201;
D error detection code (IED) 401, copyright management information (C
PR_MAI) 402 is added to the main data 301.

First, the main data 30 of 2048 bytes
1, 4-byte ID 201, 2-byte IED40
A CPR_MAI 402 of 1 or 6 bytes is added, and an EDC 403 of 4 bytes is added. Finally, scramble processing 207 for adding fixed random data to only the main data 301 of the 2064-byte data is performed.
One data sector 207 of 2 rows × 172 bytes is configured.

As described above, by performing the processing shown in FIG. 3, one data sector 207 shown in FIG. 4 is formed.

FIG. 5 is a flowchart showing signal processing from the 16 data sectors 209 shown in FIG. 2 to the creation of 16 recording sectors 212.

In FIG. 5, reference numeral 501 denotes processing for adding a 16-byte outer code parity (PO501) to each of 172 columns of 16 data sectors 209; 502, data obtained by adding PO601 to 16 data sectors 209;
In each of the 08 rows, a 10-byte inner code parity (PI60
A process 504 for adding 2) represents one ECC block composed of 208 rows × 182 bytes.

One ECC block 504 is composed of 16 data sectors 209 formed by superimposing one data sector 208 16 times.
(12 rows × 16 data sectors × 172 bytes), 10 bytes of inner code parity (PI) are added to each row, and 16 bytes of outer code parity (PO) are added to each column. You.

The 16 recording sectors 212 are formed by performing an interleaving process 211 on one ECC block 504 to rearrange the 16 rows of PO one by one among the 16 data sectors. 1 recording sector 60
3 is composed of 13 rows × 182 bytes in the ECC block after row interleaving.

Where PI is

[0023]

(Equation 1)

[Here, α9, α7,... Α0 are elements of GF (28), respectively. ] (182, 17)
2,11) code, and PO is

[0025]

(Equation 2)

[Here, α15, α14,..., Α0 are elements of GF (28), respectively. ] (208,
192, 17).

As described above, by performing the processing shown in FIG. 5, the sixteen data sectors 209 can be used as shown in FIG.
6 recording sectors 212 are configured.

FIG. 7 is also a flowchart showing signal processing from the 16 data sectors 209 shown in FIG. 2 to the creation of 16 recording sectors 212 in FIG. The flowchart showing the signal processing from the 16 data sectors 209 shown in FIG. 5 to the creation of the 16 recording sectors 212 in FIG. 6 and the 16 data sectors 209 shown in FIG.
In the flowchart of FIG. 8 showing the signal processing until the 16 recording sectors 212 are created, the order of adding PI and PO is different, but the 16 recording sectors 212 are created exactly the same.

In FIG. 7, reference numeral 701 denotes a process for adding a 10-byte inner code parity (PI 702) to each of 192 rows, 702 denotes data obtained by adding a PI 702 to 16 data sectors 209, and 703 denotes a data obtained by adding 16 bytes to each of 182 columns. Processing for adding an outer code parity (PO701) of bytes;
Reference numeral 4 denotes one ECC block composed of 208 rows × 182 bytes.

One ECC block 704 is composed of 16 data sectors 209 in which one data sector 208 is superimposed 16 times.
(12 rows x 16 data sectors x 172 bytes), 16 bytes of outer code parity (PO) are added to each column.
Next, it is constituted by adding 10 bytes of inner code parity (PI) to each row.

The 16 recording sectors 212 are formed by performing an interleaving process 211 on one ECC block 704 to rearrange the 16 rows of PO in each of 16 data sectors. 1 recording sector 60
3 is composed of 13 rows × 182 bytes in the ECC block after row interleaving.

Here, PI is an RS expressed by the following equation (1).
(182, 172, 11) code, and PO is an RS (208, 192, 17) code consisting of (Equation 2).

As described above, by performing the processing shown in FIG. 7, the 16 data sectors 209 can be used as shown in FIG.
6 recording sectors 212 are configured.

FIG. 9 is a flow chart showing signal processing from one recording sector 603 to one physical sector 907.

In FIG. 9, reference numeral 901 denotes one recording sector 60;
3 is divided (1 line is divided into 2), 902 is 13 lines ×
A data structure of 91 bytes (1st to 91st bytes), 903 is 13 rows × 91 bytes (92th to 18th bytes)
(2nd byte) data structure 904, 8/16 modulation of data 903 from the first row, adding SYNC code SY0 to SY4 at the beginning of each row, 905: 8/16 modulation of data 604 from the first row Modulate and SYNC code at the beginning of each line
Processing for adding SY5 to SY7, 906 is processing 904 and processing 9
The processing 907 for synthesizing the data obtained by performing step 05 represents one physical sector.

First, one physical sector 907 performs a process 901 of dividing one recording sector 603 into 182 bytes per row and dividing each data into 91 bytes each, and obtains 13 rows × 91 bytes (the first byte to the 91st byte of one recording sector). Data structure 903
And a data structure 904 of 13 rows × 91 bytes (92nd to 182nd bytes). Next, the data 903 is subjected to 8/16 modulation from the first row, and
Processing 904 for adding SYNC codes SY0 to SY4, and data 6
04 is modulated 8/16 from the first line, and SY is added at the beginning of each line.
The processing is performed by adding the NC codes SY5 to SY7, and the two are combined.

By performing the processing shown in FIG. 9 in this manner, one recording sector 603 forms one physical sector 907 shown in FIG.

Hereinafter, an embodiment of the digital recording apparatus of the present invention which performs the above-described digital data conversion will be described.

Note that the present invention is not limited to this format, and any other format may be used as long as a product code is added. Further, the conversion method of digital data is not particularly limited to this conversion method.

FIG. 1 is a block diagram showing a first embodiment of a digital data recording apparatus according to the present invention, which can reduce the number of accesses to a RAM required for generating an error correction code.

In FIG. 1, reference numeral 101 denotes main data 30
1 input terminal, 102 is a scramble circuit, 103 is RA
M control circuit, 104 is a RAM, 105 is an error correction code generation block, 106 is a PO operation circuit, 107 is a modulation block, 108 is a PI operation circuit, 109 is a modulation circuit, 11
0 represents a head, and 111 represents a recording medium.

However, the RAM used in the first embodiment
Reference numeral 104 denotes a RAM having a bus width of 128 bits (16 bytes) mainly used as a built-in RAM, and the PO operation circuit 106 and the PI operation circuit 108 are described as circuits capable of processing 16-byte data in parallel.

Next, the general operation of the first embodiment will be described.

First, the main data 301 is inputted from the main data input terminal 101 and the scramble circuit 102
Sent to The scramble circuit 102 converts the main data 301 into one data sector 208 and writes the data into the RAM 104 for temporarily storing data.
In the processing so far, the data in the RAM 104 forms one data sector 208.

Next, the error correction code generation block 105
The PO operation circuit 10 in (described later with reference to FIG. 14)
In step 6, the data 208 is read from the RAM 104,
A PO calculation is performed, and a process of writing the PO 601 into the RAM 104 is performed. In the processing so far, the data in the RAM 104 constitutes 16 data sectors & PO502.

Next, the modulation block 107 (which will be described later with reference to FIG. 11) uses the 16 data sectors & PO50.
2 is read from the RAM 104, a PI operation is performed, and the data is converted into one ECC block 504. Next, in the same block, a process 211 of interleaving the 16 rows of PO line by line is performed to form 16 recording sectors 212, and further a process of modulating the 16 recording sectors 212 to form 16 physical sectors 214 is performed. Do. In the processing so far, the data constitutes the disk recording signal.

Finally, the disk recording signal is written via the head 111 for recording on the recording medium 110.

The RAM control circuit 103 is a circuit for controlling access between the scramble circuit 102, the error correction code generation block 105, the modulation circuit 109 and the RAM 104. Also, the scramble circuit 102 and the RAM 104
Error correction code generation block 105 and RAM 104
Between the RAM 104 and the modulation block 107, data is transmitted in 16 bytes.

In the error correction code generation block 105, the PI
In a system including the arithmetic circuit 108 and the PO arithmetic circuit 106, one data sector 208 to one ECC block 50
4, the number of accesses between the error correction code generation block 105 and the RAM 104 indicates that the number of accesses to read data from the RAM 104 to the PO operation circuit 106 is one.
160 columns of 172 columns of 6 data sectors 209 are converted to 16
192 rows × (160 columns ÷ 16 bytes) times = 1920 times for reading in bytes, and 192 lines × 1 for reading the remaining 12 columns of 16 data sectors 209 in 16 bytes.
Times = 192 times total 1920 times + 192 times = 2112
The number of times of access from the PO arithmetic circuit 106 to the RAM 104 is 16 rows × (160 columns ÷ 16 columns) in order to write 160 columns of 172 columns of PO 601 with 16 bytes.
(Bytes) times = 160 times, the remaining 12 columns of PO601 are written in 16 bytes, but 16 rows × 1 time = 16 times, a total of 160 times + 16 times = 176 times, and reading from RAM 104 to PI operation circuit 108 When the number of accesses is 160 bytes out of 172 bytes of the data for one row of 16 data sectors & PO 502, 16 bytes are read, and the remaining 12 bytes are read out at once (1
60 bytes ÷ 16 bytes) times +1 times = 11 times, so
To read 16 data sectors & PO502 with 16 bytes, (192 + 16) rows × 11 times = 2288 times, and the number of times of writing access from the PI arithmetic circuit 108 to the RAM 104 is to write 10 bytes of PI602 with 16 bytes. (192 + 16) rows × 1 time = 208 times are required, and the error correction code generation block 105 and the RAM 10
The number of accesses between 4 is 2112 + 176 + 22
88 times + 208 times = 4784 times.

Also, the modulation block 10
In the number of times of reading access to No. 7, 176 bytes out of 182 bytes of 182 bytes of data of one row of one ECC block 504 are read out by 16 bytes, and the remaining 6 bytes are read out by one time (176 bytes ÷ 16 bytes) times. +1 times = 1
Therefore, to read one ECC block 504 with 16 bytes twice, (192 + 16) rows × 12 times = 2496
It is assumed that the number of accesses between the RAM 104 and the PO operation circuit 106 is the number of accesses between the error correction code generation block 105 and the RAM 104 by performing a modulation process without writing to the RAM 104 after the PI operation. 2064 times + 172 times = 2236 times, and the number of read accesses from the RAM 104 to the modulation block 107 is 16 data sectors & PO
To read 160 bytes out of 172 bytes of 172 bytes of data of one line of 502 and 16 bytes and read out the remaining 12 bytes at once, (160 bytes ÷ 16 bytes) times + 1 times =
11 times, therefore 16 data sectors & PO502
To read in bytes, (192 + 16) rows x 11 times =
2288 times.

Therefore, the error correction code generation block 105
In the system in which the PI operation circuit 108 and the PO operation circuit 106 are provided, the modulation block 107 has a circuit for performing the PI operation, so that the number of accesses between the error correction code generation block 105 and the RAM 104 and the RAM 10
4, the number of accesses to the modulation block 107 is decreased by (4784 + 2496) times− (2236 + 2288) = 2756 times.

FIG. 11 shows a modulation block 107 in the block diagram (FIG. 1) of the first embodiment of the digital recording apparatus of the present invention.
This is a diagram showing the configuration of FIG.

In FIG. 11, reference numeral 1100 denotes a data input terminal for one row of one data sector 208 of 128 bits (16 bytes) or a data input terminal for PO 6011 rows;
1 is a data buffer, 1102 is a data buffer, 11
03 is a selector, 1104 is a control circuit, 1105 is a select signal, and 1106 is a 128-bit disk recording signal output terminal.

The circuit operation of the modulation block 107 shown in FIG. 11 will be described.

First, the data input terminal for one row of one data sector 208 of 128 bits (16 bytes) or the data input terminal for PO6011 row is input from the input terminal 1100, and the data buffer 1101 storing 16 bytes and the PI
The signal is transmitted to the arithmetic circuit 108. The PI calculation circuit 108 calculates the calculated PI with 80 bits (10 bytes) and 10 bits.
The data is output to the data buffer 1102 for storing bytes. Then, the 16-byte data from the data buffer 1101 is transmitted to the selector 1103, and the data buffer 11
The 10-byte data from 02 is also transmitted to the selector 1103. The selector 1103 selects the select signal 110
5 is switched by a control circuit 1104 that controls the control circuit 5.
The selected signal is transmitted to the modulation circuit 109 as 16-byte data.

Next, switching of the select signal 1105 in the control circuit 1104 will be described. Input terminal 110
0 to 1 row of data in data sector 208 or
In order to transmit PO6011 rows of data to the modulation circuit 109, the data buffer 1101 storing 16 bytes first selects 10 times (160 bytes) once each,
The data is transmitted to the modulation circuit 109. In the processing up to this point, data for one row of one data sector 208 or P
160 bytes out of 172 bytes of data for the O6011 row are transmitted to the modulation circuit 109.

Next, one row of data of one data sector 208 or PO 601 is read from the data buffer 1101.
The remainder (12 bytes) of one row of data is selected and transmitted to the modulation circuit 109, and the PI 602 is selected one time (10 bytes) from the data buffer 1102.
The signal is transmitted to the modulation circuit 109. In the processing up to this point, one row of data of one data sector 208 or PO 6011
Row data (172 bytes) + PI (10 bytes) is written to the modulation circuit 109.

Finally, the modulation circuit 109 configures one ECC block 504, and performs a process 211 of interleaving 16 rows of PO codes one row at a time with respect to the one ECC block 504 to configure 16 recording sectors 212. A process of modulating this data 212 and forming 16 physical sectors 214 is performed. By the processing up to this point, the disk recording signal is configured. This data is transmitted to the output terminal 1106 in 128 bits.

By configuring the modulation block 107 in this way, the system of the first embodiment of the digital data recording apparatus which can reduce the number of accesses to the RAM required for generating the error correction code shown in FIG. Can be realized.

FIG. 12 shows a digital data recording apparatus which can reduce the number of accesses to the RAM required to generate an error correction code when accessing the same RAM from a plurality of signal processing circuits according to the present invention. 9 shows a second embodiment of the recording apparatus.

In FIG. 12, reference numeral 1201 denotes a scramble block. However, the RAM 104 used in the first embodiment is mainly used as a built-in RAM.
A RAM having a bus width of 8 bits (16 bytes) is used.
The O operation circuit 106 and the PI operation circuit 108 are described as circuits that can process 16-byte data in parallel.

Next, the general operation of the second embodiment will be described.

First, the main data 301 is input from the main data input terminal 101 and the scramble block 1
It is sent to 201. In the scramble block 1201 (described later with reference to FIG. 13), the main data 301
Is converted into one data sector 208 and data is temporarily written to the RAM 104 for temporarily storing data, and PI calculation is performed to write the PI 802 to the RAM 104. In the processing so far, the data in the RAM 104 constitutes 16 data sectors & PI 702.

Next, the error correction code generation block 105
The PO operation circuit 10 in (described later with reference to FIG. 14)
In step 6, the 16 data sectors & PI 702 are read from the RAM 104, the PO operation is performed, and the PO 801 is stored in the RAM 10
4 is written. In the processing so far, RAM1
The data in 04 constitutes one ECC block 704.

Next, the modulation circuit 109 reads the one ECC block 704 from the RAM 104 and reads out the 16
A process 211 for interleaving the rows one by one is performed, and
6 recording sectors 212, and the data 2
A process of modulating 12 and forming 16 physical sectors 214 is performed. In the processing so far, the data constitutes the disk recording signal.

Finally, the disk recording signal is written via the head 111 for recording on the recording medium 110.

The RAM control circuit 103 includes a scramble block 1201 and an error correction code generation block 10.
5. A circuit for controlling access between the modulation circuit 109 and the RAM 104. Also, the scramble block 1201
Between the RAM 104 and the RAM 104, between the error correction code generation block 105 and the RAM control circuit 103, and between the RAM 104 and the modulation block 107, data is transmitted in 16 bytes.

The PI in the error correction code generation block 105
In a system including the arithmetic circuit 108 and the PO arithmetic circuit 106, one data sector 208 to one ECC block 50
4, the number of write accesses from the scramble block 1201 to the RAM 104 is 1 in 172 bytes of data for one row of 16 data sectors 209.
To write 60 bytes as 16 bytes and write the remaining 12 bytes at once, (160 bytes ÷ 16 bytes)
+1 times = 11 times, therefore, to write 16 data sectors 209 with 16 bytes, 192 rows × 11 times = 211
Needed twice.

Error Correction Code Generation Block 105 and RAM
In the number of accesses between the 104 and the 104, the number of times of reading from the RAM 104 to the PO operation circuit 106 is 192 rows × (160 columns ÷ 16 bytes), although 160 columns of 172 columns of 16 data sectors 209 are read in 16 bytes. )
Times = 1920 times, the remaining 12 of 16 data sectors 209
192 rows x 1 time = 1 to read column data in 16 bytes
A total of 92 times 1920 times + 192 times = 2112 times, and the number of times of writing access from the PO arithmetic circuit 106 to the RAM 104 is 16 rows × (160 columns ÷) for writing 160 columns of 172 columns of PO601 in 16 bytes. 16
(Bytes) times = 160 times, the remaining 12 columns of PO601 are written in 16 bytes, but 16 rows × 1 time = 16 times, a total of 160 times + 16 times = 176 times, and reading from RAM 104 to PI operation circuit 108 When the number of accesses is 160 bytes out of 172 bytes of the data for one row of 16 data sectors & PO 502, and 16 bytes are read out, and the remaining 12 bytes are read out at once,
(160 bytes ÷ 16 bytes) times + 1 times = 11 times, therefore, to read 16 data sectors & PO502 in 16 bytes, (192 + 16) rows × 11 times = 2288 times, and write access from the PI operation circuit 108 to the RAM 104 The number of times required to write 10 bytes of the PI 602 as 16 bytes is (192 + 16) rows × 1 time = 208 times, and the error correction code generation block 105 and the RAM 10
The number of accesses between 4 is 2112 + 176 + 22
88 times + 208 times = 4784 times.

And 16 data sectors 209 are stored in RAM 1
By performing a PI operation before writing to the RAM 04, the scramble block 1001
In the number of times of writing access to No. 4, 176 out of 182 bytes of data of one row of 16 data sectors & PI 702
Write the byte as 16 bytes and leave the remaining 6 bytes as 16
To write in bytes, (176 bytes ÷ 16 bytes)
Times + 1 times = 12 times, so 16 data sectors & PI7
02 is written in 16 bytes, 192 lines x 12 times =
Needed 2304 times.

In the number of accesses between the error correction code generation block 105 and the RAM 104, the number of accesses to read from the RAM 104 to the PO arithmetic circuit 106 is 16
To write 176 columns of 182 columns of data sector & PI 702 with 16 bytes, 192 rows × (176 columns１７1)
6 bytes) times = 2112 times, 16 data sectors & PI7
To write the remaining 6 columns of 02 in 16 bytes, 19
2 rows x 1 time = 192 times, total 2112 times + 192 times = 2
Needs 304 times.

The number of write accesses from the PO operation circuit 106 to the RAM 104 is 16 rows × (1) to write 176 columns out of 182 columns of PO801 in 16 bytes.
(176 columns / 16 bytes) times = 176 times, and the remaining 12 columns of PO801 are written in 16 bytes, so that 16 rows × 1 time = 16 times, a total of 176 times + 16 times = 182 times are required, and an error correction code is generated. The total number of accesses between the block 105 and the RAM 104 is 2304 + 182 = 2486 times.

Therefore, the error correction code generation block 105
In a system in which a PI operation circuit 108 and a PO operation circuit 106 are provided,
By providing a circuit for performing the I operation, the number of accesses from the scramble block 1201 to the RAM 104 and the number of accesses between the error correction code generation block 105 and the RAM 104 are reduced by (2112 + 4784) − (2304 + 2486) = 2106 times.

FIG. 13 shows a scramble block 1201 in the block diagram (FIG. 10) of the second embodiment of the digital recording apparatus of the present invention.

In FIG. 13, 1301 is a data buffer, 1302 is a data buffer, 1303 is a selector,
1304 is a control circuit, 1305 is a select signal, 130
6 is a data buffer, 1307 is one data sector 208
Or, it indicates a PI802 output terminal.

The circuit operation of the scramble block 1201 in FIG. 13 will be described.

First, 8-bit main data 301 is input from the input terminal 101 and transmitted to the scramble circuit 102. In the scramble circuit 102, the main data 301 is converted into one data sector 208, and a data buffer 1301 for storing 128 bits (16 bytes) and a PI
The data is output to the arithmetic circuit 108 in 8 bits.

Next, the PI calculated by the PI calculation circuit 108
Reference numeral 802 denotes 80 bits, which are output to the data buffer 1302 that stores 80 bits (10 bytes). Then, 16-byte data from the data buffer 1301 is transmitted to the selector 1303, and 10-byte data from the data buffer 1302 is transmitted to the selector 1303. The selector 1303 is switched by a circuit 1304 for controlling the select signal 1305. The selected signal is 16-byte data and transmitted to the data buffer 1306 that stores 16 bytes, and one data sector 208 or PI 802 is output from the output terminal 1307 in 16-byte units.

Next, switching of select signal 1305 in control circuit 1304 will be described. In order to transmit 172 bytes for one row of one data sector 208 from the scramble circuit 102 to the output terminal 1307, the data buffer 1301 that stores 16 bytes first receives 10 bytes at a time.
Select by batch (160 bytes) selector 1303,
1 in data buffer 1306 that stores 16 bytes of data
The data is stored 10 times each time and transmitted to the output terminal 1307 one time. By the processing up to this point, one of the data sectors 208
Output terminal 13 is 160 bytes out of 172 bytes of the line
07.

Next, the remaining one time (12 bytes) in 172 bytes for one row of one data sector 208 is selected from the data buffer 1301 and the data buffer 1306 is selected.
And PI 802 is selected from the data buffer 1302 for one time (10 bytes).
Save to 6. Then, one row remaining (12 bytes) of one data sector stored in the data buffer 1306 + P
I (10 bytes) is transmitted to the output terminal 1307. By the processing so far, one row (172 bytes) of one data sector 208 + PI (10 bytes) is transmitted to the output terminal 1307. The scramble block 1201 repeats this processing, so that the main data 301 input terminal 1
From 01, 16 data sectors & PI 702 are transmitted to the output terminal 1307.

As described above, the scramble block 120
By configuring 1, the system according to the second embodiment of the digital data recording apparatus which can reduce the number of accesses to the RAM required for generating the error correction code shown in FIG. 12 can be realized.

FIG. 14 is a block diagram showing the first and second embodiments of the digital recording apparatus according to the present invention. In the PO operation circuit 106 shown in FIG. FIG. 3 shows an example of a block diagram of a circuit that also serves as arithmetic processing (recording).

In FIG. 14, 1400 is an address generation circuit, 1401 is a syndrome operation circuit, 1402 is an error position operation circuit, 1403 is an erasure correction error position operation circuit, 1404 is a PO operation PO position giving circuit,
405 is a selector, 1406 is a select signal, 1407
Is a selector, 1408 is a control circuit for controlling whether erasure correction is performed or not, 1409 is a select signal, 141
0 is an AND circuit, 1411 is a select signal, 1412 is syndrome data, 1413 is an error value calculation circuit (during reproduction) or a PO value calculation circuit (during recording), 1414
Denotes an error correction circuit (at the time of reproduction) or a PO giving circuit (at the time of recording), 1415 denotes address data, 1416 denotes error correction data or the value of PO, and 1417 denotes a microcomputer.

The circuit operation of the PO operation circuit 106 shown in FIG. 14 will be described.

First, an example of the operation of the selectors 1405 and 1407 will be described.

In the recording mode (select signal 1406: 1), the selector 1405 selects the output data from the PO calculation PO position imparting circuit 1404 by the select signal 1406 output from the microcomputer 1417, and outputs the data in the reproduction mode ( At the time of the select signal 1406: 0), the output data from the arithmetic circuit 1403 at the position of the erasure correction error is switched so as to be selected.

The selector 1407 receives the select signal 140
6 and a select signal 1410 from a control circuit 1408 for controlling whether to perform erasure correction or not.
Select signal 141 generated by performing processing at 410
Switched by 1. When the select signal 1411 is 1, the output data from the error position calculation circuit 1407 is selected, and when the select signal 1411 is 0, the output data from the selector 1405 is switched. At this time, select signal 1 from control circuit 1408 for controlling whether or not erasure correction is performed is performed.
Reference numeral 410 denotes 0 when erasure correction is performed, and 1 when erasure correction is not performed.

Next, the operation at the time of the PO error correction processing (reproduction) will be described. In the PO error correction processing, the control circuit 1408 selects whether to perform erasure correction by a predetermined error correction algorithm.

First, signal processing when erasure correction is not performed will be described. The address data generated by the address generation circuit 1400 is transmitted to the RAM
Request for one ECC block 504, 704 from. Next, the syndrome calculation circuit 1401 receives the 1 ECC blocks 504 and 704 from the RAM 104 and executes a syndrome calculation to determine a syndrome. This syndrome data is transmitted to the error position calculation circuit 1402, and the position of the error is obtained.

Next, the error position data is stored in the selector 1
407 to the error value calculation circuit 1413.
The error value calculation circuit 1413 calculates an error value based on the syndrome data 1412 from the syndrome calculation circuit 1401 and the error position data from the error position calculation circuit 1402, and transmits the error value to the error correction circuit 1414. The error correction circuit 1414 corrects the value of the error, and stores the address 1415 of the data and the error correction data 1416 in the RA.
Send to M104.

Next, signal processing for performing erasure correction will be described. The address data generated by the address generation circuit 1400 is transmitted to the RAM 104, and a request is made for one ECC block 504, 704 from the RAM 104. next,
The syndrome operation circuit 1401 reads 1
The ECC blocks 504 and 704 are received, and a syndrome operation is executed to obtain a syndrome. This syndrome data is transmitted to the error position calculation circuit 1402 to determine the position of the error, but this error position is not used.

On the other hand, in the selectors 1405 and 1407,
Error position data from the erasure correction error position calculation circuit 1403 is selected and transmitted to the error value calculation circuit 1413. The error value calculation circuit 1413 generates the syndrome data 1412 from the syndrome calculation circuit 1401.
And an error value is calculated based on the error position data from the erasure correction error position calculation circuit 1403, and the error correction circuit 1
414. The error correction circuit 1414 corrects the value of the error, and transmits an address 1415 of the data and error correction data 1416 to the RAM 104.

Next, the operation at the time of the PO calculation processing (recording) will be described. The PO calculation processing used here is an example of a method of calculating a PO by performing erasure correction using the position of the PO as an error position. Therefore, in this case, the control circuit 1
It is assumed that the select signal 1409 from 408 is 0 when erasure correction is performed.

The address data generated by the address generation circuit 1400 is transmitted to the RAM 104, and the data from the RAM 104 to which the PO is not added is requested. next,
The syndrome operation circuit 1401 reads P
The data to which O is not added is received, and a syndrome operation is executed to obtain a syndrome. This syndrome data is transmitted to the error position calculation circuit 1402 to determine the position of the error, but this error position is not used.

On the other hand, in the selectors 1405 and 1407,
PO position data from the PO calculation PO position giving circuit 1404 is selected and transmitted to the PO value calculation circuit 1413. In the PO value calculation circuit 1413, the syndrome data 1412 from the syndrome calculation circuit 1401 is output.
And the PO from the position giving circuit 1404 for the PO calculation PO
Calculates the value of PO based on the position data of
414. The PO giving circuit 1414 sends the PO address 1415 and the value 1416 to the RAM 104.

With such a configuration, it is possible to realize a circuit that combines the PO error correction processing (reproduction) and the PO calculation processing (recording).

[0097]

As described above, according to the present invention, in a digital data recording device including an error correction code generation circuit for generating a product code, a RAM, and a modulation circuit, the process of generating the product code includes storing data in the RAM. It is general to generate a code for a data string in a different direction while storing and reading out the data, but a PI for generating a PI for data in the same direction as the data string to be output after generating an error correction code is generated. After the calculation, a system that performs modulation processing without writing to the RAM 104 is provided.

Alternatively, data for generating a product code is represented by R
By using a system that performs a PI operation before writing to the AM 104, the number of accesses between the error correction code generation circuit and the RAM can be reduced, and the time required for processing to generate a product code can be reduced. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a digital data recording device.

FIG. 2 is a flowchart showing a processing order for configuring a physical sector;

FIG. 3 is a signal processing flow (data sector) chart.

FIG. 4 is a diagram showing one data sector.

FIG. 5 is a flow (recording sector) chart showing a signal processing order.

FIG. 6 is a diagram showing one ECC block diagram and 16 recording sectors.

FIG. 7 is a flow (recording sector) chart showing a signal processing order.

FIG. 8 is a diagram showing one ECC block diagram and 16 recording sectors.

FIG. 9 is a flow (physical sector) chart showing a signal processing order.

FIG. 10 is a diagram showing one recording sector diagram and one physical sector.

FIG. 11 is a diagram showing a configuration of a modulation block.

FIG. 12 is a block diagram of a second embodiment of the digital data recording device.

FIG. 13 is a configuration diagram of a scramble block.

FIG. 14 is a block diagram of a circuit that combines a PO error correction process and a PO operation process.

[Explanation of symbols]

101: main data input terminal, 102: scramble circuit, 103: RAM control circuit, 104: RAM, 10
5: error correction code generation block, 106: PO operation circuit, 107: modulation block, 108: PI operation circuit, 1
09: modulation circuit, 110: head, 111: recording medium,
208 ... 1 data sector, 209 ... 16 data sector,
212 ... 16 recording sectors, 214 ... 16 physical sectors, 3
01: main data, 502: 16 data sectors & P
O, 504 ... 1 ECC block, 603 ... 1 recording sector, 907 ... 1 physical sector.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Tomoaki Uno 5-2-1, Josuihoncho, Kodaira-shi, Tokyo F-term in the Semiconductor Division, Hitachi, Ltd. 5J065 AA01 AB01 AC03 AD03 AD13 AF01 AH06

Claims (7)

[Claims] A first check symbol orthogonal to a data sequence and a second check symbol;
And a storage circuit for temporarily storing input digital data, reading data from the storage circuit to generate a first check symbol, and generating the first check symbol. A first check symbol generation circuit for writing a symbol to the storage circuit, a second check symbol generation circuit for reading data and the first check symbol from the storage circuit to generate a second check symbol, In a digital data recording device including a modulation circuit that modulates a first check symbol and a second check symbol, the second check symbol generation circuit generates a second check symbol, and then generates the second check symbol. A digital data recording apparatus, wherein a check symbol and data for the second check symbol or the first check symbol are sent to the modulation circuit. 2. A method according to claim 1, wherein a first check symbol of a product code and a second
In the method of adding a check symbol, the second check symbol is generated for data in the same direction as a data string output after generating an error correction code, and the second check symbol is generated after generating the first check symbol. , Generating the second check symbol for the data and the generated first check symbol, and sequentially outputting the generated second check symbol and the data or the first check symbol for the second check symbol. Product code generation method, characterized in that: 3. A first check symbol orthogonal to a data sequence and a second check symbol.
A product code generation system for adding a check symbol, a storage circuit for temporarily storing data, and a second check symbol,
A second check symbol generation circuit for writing the generated second check symbol to the storage circuit, and a first check symbol for reading data and the second check symbol from the storage circuit to generate a first check symbol In the digital data recording apparatus including the generation circuit, after the input digital data is generated by the second check symbol generation circuit to generate a second check symbol, the generated second check symbol and the second check A digital data recording device wherein data for a symbol or a second check symbol is sent to the storage circuit. 4. A data sequence comprising a first check symbol of a product code and a second
In the method of adding a check symbol, the second check symbol is generated for data in the same direction as a data string to be output after generating an error correction code, and after the second check symbol is generated. Generating the first check symbol for the data and the generated second check symbol, and sequentially outputting the generated first check symbol and the data or the second check symbol corresponding thereto. Product code generation method, characterized in that: 5. A first check symbol generation circuit for generating a first check symbol of a product code in a data sequence, a second check symbol generation circuit for generating a second check symbol, and a data sequence of a product code A digital data recording / reproducing apparatus including an error correction circuit for performing the error correction processing described above, wherein the first check symbol generation circuit is also used as the error correction circuit. 6. An error correction circuit for performing error correction on data of a product code to which orthogonal first and second check symbols are added, and a data for performing error correction on the data. A digital recording / reproducing apparatus including a storage circuit for temporarily storing a second check symbol, the digital recording / reproducing apparatus having a second check symbol generating circuit for generating the second check symbol. 7. The digital recording / reproducing apparatus according to claim 6, wherein said error correction circuit generates a first check symbol.