JPH04140843A - Register file - Google Patents

Abstract

PURPOSE:To prevent a remarkable increase of the hardware quantity and the complication of the device by allowing a scan path to pass through only one address in a register file. CONSTITUTION:By setting a shift mode signal 10 to '0', an address to be read out of a read address line 12 is given to an output selector 3. The output selector 3 reads out the contents of the designated address from a register group 2. By setting a select signal 9 to '1', an input selector 1 selects an output of the output selector 3 sent through a signal line 8, and sends it to the register group 2. Subsequently, '0' number is designated by a write address line 11, and an output of the input selector 1 is written in the address '0' number of the register group 2. Next, the shift mode signal 10 is set to '1', and the contents of the address '0' number are read out by using a scan path.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a register file, and particularly to a register file for an information processing device having a scan path.

[Conventional technology]

Traditional register files either have no scan path at all or have a scan path through every register.

[Problem to be solved by the invention]

If the conventional register file described above has no scan path at all, it is necessary to have special external registers and logic circuits in order to collect the data contents of the register file in the event of a failure, making the device complicated. or become
There is a disadvantage that the amount of hardware increases, and when a scan path passes through all registers, the amount of hardware increases significantly compared to a case where there is no scan path at all.

[Means to solve the problem]

The register file of the present invention is divided into a plurality of words, and includes a register group that has a scan path only in the 17th word, an output register that reads a word specified by a read address from the output of the register group, and a register file that reads a word specified by a read address from the output of the register group. It has an input selector that selects one of the input data and the output of the output register and inputs it to the register group.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram 1 showing one embodiment of the present invention.
is an input selector that selects and outputs one of the input data and the output Q of output selector 3, and 2 is a write address when not in shift mode.The output of input selector 1 is approximately written to the specified address, when in shift mode. is a register group assigned addresses O to F (hexadecimal) where address 0 and C scan path performs a shift operation, and 3 (from the output of each address of register group 2, the address specified by the read address is This is an output selector that selects the output.

The operation of this register file will be described below. First, the normal operation, which is not in shift mode, will be described.

By setting select signal 9 to O, input selector 1
selects the input data sent from the signal line 4 and sends it to the register group 2. Register group 2 receives the output of input selector 1 from signal line 5 . At this time, the shift mode signal 10 is O, so the register group 2 writes the received data to the address specified by the write address line 11.

When the read address is specified using the read address line 12,
The selector 3 selects the output of the specified address from the register group 2 and outputs it to the outside via the signal line 7.

Next, we will describe the operation when reading data in the register file using the scan path.

First, the contents of address No. 0 are read by setting the shift mode signal 10 to 1 and using a scan path. The contents of addresses other than number 0 are read out as follows.

The shift mode signal 10 is set to O, and the address to be read from the read address line 12 is given to the output selector 3. The output selector 3 reads the contents of the designated address from the register group 2. By setting the select signal 9 to 1, the input selector 1 selects the output of the output selector 3 sent through the signal line 8 and sends it to the register group 2. Specify number 0 on write address line 11 and write the output of input selector 1 to address number 0 of register group 2.

Set the shift mode signal 10 to 1 and read the contents of address No. 0 using the scan path.

Finally, we will discuss the operation when writing data to the register file using the scan path.

When writing to address No. 0, shift mode signal 10 is set to 1 and writing is performed using a scan path. When writing to another address, first set the shift mode signal 10 to 1 and write data to address No. 0 using the scan path. After returning the shift mode signal 10 to O, input O to the read address and select the contents of address No. 0 with the output selector 3. The select signal 9 is set to 1, and the input selector 1 selects the contents of the output selector 3 and sends it to the register group 2.

Specify the address you want to write using write address line 1, and write the output of input selector 1.

By having a scan path at only one address in the register file and adding an input selector so that the output of the register file can be input again, it is possible to do this without significantly increasing the amount of hardware or complicating the device. This has the advantage that any address within the register file can be read and written using a scan path.

〔Effect of the invention〕

As explained above, the present invention provides one
By having an input selector that can selectively input input data and the output of its own register file by passing a scan path through only one address, it is possible to input data within the register file without significantly increasing the amount of data or complicating the device. This has the effect of being able to read and write any address from the scan path.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention. 1...Input selector, 2...Address 0 to F (1
A group of registers with a scan path only at address O, 3...output selector, 4 to 8...
Data signal line, 9... Select signal line of input selector, 10... Shift mode line, 11... Write address line, 12-... Read address line.

Claims (1)

[Claims] A register group that is divided into a plurality of words and has a scan path in only one word; an output selector that is connected to the register group and selects a word specified by a read address; 1. A register file comprising an input selector for selecting one of the registers and inputting the selected register to the register group.