JP2788765B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a semiconductor memory device, and more particularly to a random access type semiconductor which can read and write stored information to a desired address in a memory block according to address selection information. For storage devices (hereinafter referred to as RAM: Random Access Memory), by reducing the number of external address input terminals of a large-capacity RAM, a large-capacity RAM with a small IC package and high mounting efficiency on a printed circuit board is provided. A plurality of memory blocks each having a plurality of memory cells, and an external data input terminal connected to a block data input terminal of each memory block for supplying data to each memory block. In the semiconductor memory device provided, a memory input from an external data input terminal at the time of an address selecting operation in the semiconductor memory device is provided. Memory block selecting means for selecting one of the memory blocks based on reblock selection information, and memory for selecting any one of memory cells in the selected memory block based on externally input address selection information Cell selection means, wherein the memory block selection means detects an address selection operation timing from address selection information, and an address selection detection output when the address selection detection means detects the address selection operation timing A memory block selection information holding unit that temporarily holds the memory block selection information based on a signal and outputs the information to the selected memory block.

[Industrial applications]

The present invention relates to a semiconductor memory device, and more particularly to a random access type semiconductor memory device (hereinafter, RAM: Random Access Memory) capable of reading and writing storage information at a desired address in a memory block according to address selection information. About).

In recent years, information processing by computers and the like has increased, and accordingly, it has been required to increase the storage capacity of RAM. However, when the memory cell area is enlarged, the word line becomes longer, the RC time constant becomes longer, and it takes a longer time to select an address.In addition, the bit line becomes longer and the load on the memory cell increases. Therefore, there is a problem that it takes time to read the stored information. Therefore, the memory space of the RAM is divided into a plurality of memory blocks.

[Conventional technology]

FIG. 4 shows a conventional RA divided into a plurality of memory blocks.
Here is an example of M.

This RAM, a plurality of memory blocks MB _1, MB _2, ... MB
and _m, a decoder 30, an external address input terminal A _X, and the external data input terminal D _IN, and Lato enable input terminal WE,
It consists of an external data output terminal D _OUT .

Each of the memory blocks MB _{1 to} MB _m is composed of a plurality of memory cells, each of which has a block address input terminal ▲ ▼
, Block select input terminal ▲ ▼, block data input terminal ▲ ▼, block write enable input terminal ▲ ▼, block data output terminal ▲
And ▼. The external address input terminal _AX has (k + n) input terminals.

 Next, the operation will be described.

First, external address input terminals A _X, the k of terminals are k-bit memory block selection information phi _B is input, the signal from the first being decoded decimal to m is output by the decoder 30. This output signal is applied to each memory block MB
₁ to MB desired memory block MB _i block select input external ▲ ▼ to be applied _m is selected.

Then, n-bit address selection information phi _A is input to the rest of the n-number of terminals of the external address input terminals A _X. This is the block address input terminal in each memory block.
▼ is applied to, to select a previously desired address from among the 2 ⁿ addresses in memory block MB _i is selected (address).

Thereafter, an external write enable input terminal WE is "L" level of the write enable signal phi _E is input becomes the write operation state, the desired memory information is written to the memory cells in the selected address location. If the contrary reading stored information, after selecting the desired address via the same process as above, it is a read operation by inputting the "H" level of the write enable signal phi _E to the external write enable input terminal WE , The storage information at the selected address can be read.

It should be noted that normally, p-bit storage information can be input in parallel to the external data input terminal _DIN . In the computer, the arithmetic processing and the like have p = 8 bits.

From the above, since the number of memory blocks is m and the storage capacity of each memory block is 2 ⁿ bits, it is possible to arbitrarily read and write m × 2 ⁿ bits of storage information as a whole.

[Problems to be solved by the invention]

However, in the RAM, as described above, (k + n) external address inputs are required to select an address in the memory space of m × 2 ⁿ bits. So, for example,
With a memory capacity of 1 mega (10 ⁶ ) bits and m = 2 ^k , from 2 ^{(k + n)} = 10 ⁶ , k + n = 20. In the end, 20 external address input terminals are required. Become. However, increasing the number of input pins in RAM is
This causes an increase in the size of the C package, and consequently causes a problem that mounting efficiency on a printed circuit board is reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. By reducing the number of external address input terminals of a large-capacity RAM, a large-capacity high-capacity mounting on a printed circuit board can be achieved in a small IC package. Aims to provide RAM.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a memory block (MB _{1 to} MB _m ) each having a plurality of memory cells and divided into a plurality of memory blocks (MB _{1 to} MB _m ). in the semiconductor memory device comprises an external data input terminal (D _iN) for being connected to the block data input terminal of the _{MB 1 ~MB m) (▲ ▼} ) to supply data to the respective memory blocks (MB ₁ ~MB _m), At the time of an address selection operation in the semiconductor memory device, the memory block (MB) is selected based on memory block selection information (φ _B ) input from an external data input terminal (D _IN ).
_{1 to} MB _m ) and one of the memory cells in the selected memory block (MB _i ) based on address selection information (φ _A ) input from the outside. A memory cell selecting means, wherein the memory block selecting means comprises: an address selection detecting means (1) for detecting an address selection operation timing from address selection information (φ _A ); Based on an address selection detection signal (φ _C ) output when detecting the address selection operation timing,
And memory block selection information holding means (2) for temporarily holding the memory block selection information (φ _B ) and outputting it to the selected memory block (MB _i ).

[Action]

According to RAM according to the present invention having the above structure, the memory block selection information for selecting a desired memory block _{(MB 1 ~MB m) (φ} B) may be input to an external data input terminal (D _IN) Therefore, an external address input terminal for inputting memory block selection information is not required. Therefore, the number of external address input terminals (A) can be reduced accordingly.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of the RAM of the present invention. This first
In the figure, the same or overlapping parts as those in the conventional example of FIG. 4 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In FIG. 1, a RAM includes an address selection detector 1 as an address selection detection unit, a status register 2 as a memory block selection information holding unit, a decoder 3, a write control circuit 4, and a plurality of memory blocks MB ₁ to MB ₁ . MB _m , external address input terminal A, external data input terminal _DIN , external write enable input terminal WE, and external data output terminal
D _OUT .

Each of the memory blocks MB ₁ to MB _m consists fourth view of a conventional example as well as a plurality of memory cells, each of the block address input terminal, the block select input ▲
▼, a block data input terminal ▲ ▼, a block write enable input terminal ▲ ▼, and a block data output terminal ▲ ▼.

Next, FIG. 2 shows details of the address selection detector 1 and the status register 2 in FIG. Address selector detector 1, the AND circuit 20 for taking a logical product of the address selection information phi _A inputted to the n external address input terminals A ₀ to A _n-1
It is. The write control circuit 4 has an inverter and a two-input
This is a circuit composed of an AND circuit. The output of the AND circuit 20 is connected to one input terminal of the write control circuit 4. The other input terminal of the write control circuit 4 write enable signal phi _E via an inverter is inputted. When selecting a desired memory block from each memory block MB ₁ to MB _m inputs address selection information phi _A of the external address input terminals A ₀ ~A _n-1 of all "H" level By
Address selection detection signal phi _C is the output of the AND circuit 20 becomes "H" level. Then, the write enable signal φ _E
There "L" when the level is the output of the write control circuit 4 write control signal phi _W becomes "H" level, and performs writing to the status register 2. That is, address selection information phi _A is an external address input terminals A ₀ ~A _n-1 of all "H" level every time the memory block selection.

Also, the status register 2, an inverter 21, and NAND circuits 22, 23, 24, 25, when the write control signal phi _W which is the output of the write control circuit 4 is at the "H" level external data at that time Output the information of the input terminal D _IN as it is O
_SR , and thereafter, even if the write control signal φ _W goes to “L” level, the external data input terminal D _IN at that point in time until the write control signal φ _W goes to “H” level next time. Is a register that keeps outputting the information of the same as it is.

 Next, the operation will be described.

First, in order to select the desired block in the m memory blocks, referred to as X address below the external address input terminals A ₀ ~A _n-1 of all "H" level (an address corresponding thereto ) inputs the address selection information phi _a, enter the "L" level of the write enable signal phi _E to the external write enable input terminal WE. As a result, the address selection detector 1 outputs the "H" level address selection signal φ _C
Outputs, the output phi _W of the write control circuit 4 becomes "H" level.

On the other hand, k-bit memory block selection information φ _B for selecting a desired memory block is supplied to an external data input terminal.
It is input to D _IN and transmitted to the status register 2.
Since the output phi _W of the write control circuit 4 is at the "H" level, the memory block selection information phi _B is output to be held is taken into the status register from D _IN O _SR. Then, this address signal passes through the decoder 3 and is converted to a decimal 1
From decoded into signals up m, the desired memory block MB _i is selected from among the m memory blocks. At this time, the memory block MB _i of the address: The address X, the memory block selection information phi _B is written. Therefore, X addresses of each memory block in the address to be selected when all of the external address input terminals A ₀ ~A _n-1 becomes the "H" level, the address to store the memory block selection information other words It can be said that there is. And
Next, when the external address input A ₀ to A at least one input of the _n-1 becomes the "L" level or an external write enable terminal WE is "H" level, the output phi _W of the write control circuit 4 “L”
Level, and the status register holds the state immediately before. That is, the memory block MB _i continues to be continuously selected.

The desired address from among the 2 ⁿ memory cells of the external address input in terminal A ₀ to A by applying a desired address selection information phi _A to _n-1 already memory block MB is selected _i that in this state The user can select and write or read the address. By entering the external write enable input terminal WE "L" level of the write enable signal phi _E, it is possible to write the information that has been inputted to the external data input terminal D _IN at that time. External write enable input pin
WE to "H" level of the write enable signal φ external data output terminal D _OUT information stored in the address selected by entering the _E
Can be output to

Here, FIG. 3 shows a timing chart relating to the operation of the RAM of the present invention.

At the time of the third view Address: X address is selected, this address: data d _i is written as a memory block selection information in the X address. Thus, the numerical data d _i is the status register 2 is held at this point. The data d _i is decoded to i in the decoder 3 is output as the O _SR in the i-th memory block MB
_i has been selected. This state is maintained until the next writing to the address X is performed. At this point, the data _dj is written as the memory block selection information at the address: address X, and the data _dj is captured and held in the status register 2. As a result, the j-th memory block MB _j is selected thereafter.

As described above, in the RAM of the present invention, one cycle is required to switch the memory block. Therefore, for example, when it is necessary to switch the memory block every cycle, it takes two cycles for the substantial write / read operation. However, the CPU (C
In the case where the central processing unit (central processing unit) accesses the memory, it is often considered that frequent switching of the memory block is extremely rare because the addresses of consecutive addresses are often accessed in order. Because when storing data in a memory, it is common to perform a storage operation while securing a certain memory area, so there is a high probability that sequential access to sequentially access addresses at consecutive addresses is performed. This is because when a program is stored in the memory, the CPU accesses the memory sequentially unless there is a branch instruction.

It should be noted that normally, p-bit storage information can be input in parallel to the external data input terminal _DIN . In a computer, arithmetic processing and the like usually have p = 8 bits.

From the above, since the number of memory blocks is m and the storage capacity of each memory block is 2 ⁿ bits, the memory block has a total memory space of m × 2 ⁿ bits, which is shown in FIG. This is the same as the conventional RAM shown. However, in the RAM of the present invention, as described above, the memory block selection information for selecting a desired memory block only needs to be input to the external data input terminal _DIN, and the k external address input terminals corresponding to that are input. Becomes unnecessary as a result. In addition,
Since the data width of D _IN is p bits, the memory block selection signal can use up to a maximum of p bits. As described above, since p = 8 bits in a computer, eight external address input terminals can be reduced in this case.

〔The invention's effect〕

As described above, according to the present invention, since the memory block selection information for selecting a desired memory block may be input to the external data input terminal, the address of the RAM having a huge storage capacity is replaced with the conventional RAM. Can be selected with a significantly smaller number of external address input terminals than
The size of the IC package can be reduced. As a result, there is an advantage that the memory mounting efficiency on the printed circuit board can be increased.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the RAM of the present invention, FIG. 2 is a circuit diagram showing details of an address selection detector and a status register in FIG. 1, and FIG. 3 is an operation of the RAM of the present invention. FIG. 4 is a block diagram showing an example of a conventional RAM. 1 ... Address selection detector 2 ... Status register 3 ... Decoder 4 ... Write control circuit 20 ... AND circuit 21 ... Inverter 22-25 NAND circuit 30 ... Decoder A ... External address input terminal …… Block address input terminal A _X …… External address input terminal ▲ ▼ …… Block address input terminal A _{0 to An-1} …… External address input terminal ▲ ▼ …… Block select input terminal D _IN …… External data input terminal ▲ ▼ ...... block data input terminal D _OUT ...... external data output pin ▲ ▼ ...... block data output terminal MB ₁ ~MB _m ...... memory block O _SR ...... status register output WE ...... external write enable input terminal ▲ ▼ ...... block write enable input terminal X ...... address d _i, d _j ...... data k, p, n ...... bit φ _{A ......} address selection information φ _{B ......} Memoriburo Click selection information φ _{C ......} address selection detection signal φ _{E ......} write enable signal φ _{W ......} write control signal

Claims (1)

(57) [Claims] A memory block (MB _{1 to} MB _m ) having a plurality of memory cells and a block data input terminal (▲) of each memory block (MB _{1 to} MB _m ).
▼) connected to an external data input terminal (D _IN ) for supplying data to each of the memory blocks (MB _{1 to} MB _m ). based on the memory block selection information (phi _B) inputted from the input terminal (D _iN) said memory blocks (MB ₁ ~M
B _m ), and address selection information (φ) externally input to any of the memory cells in the selected memory block (MB _i ).
_A ) a memory cell selection means for selecting based on address selection information (φ
_A ) An address selection detection means (1) for detecting an address selection operation timing from the above, and an address selection detection signal (φ _C ) output when the address selection detection means (1) detects the address selection operation timing. And a memory block selection information holding means (2) for temporarily holding the memory block selection information (φ _B ) and outputting the selected information to the selected memory block (MB _i ). Semiconductor storage device.