JPH04228187A - Random-access-memory-array - Google Patents

Abstract

PURPOSE: To shorten the access time for a RAM cell array used for a computer by latching data in a selected row of the RAM cell array to a first and a second latch circuits and selectively making a latch output enable/disable. CONSTITUTION: A row address by means of row address lines a (2), a (3) is decoded by a row decoder 34, one row of RAM cell array 30 is selected and the data in the row are supplied in parallel/latched to a first and a second latch circuits 40, 42. The latched data are outputted from either of the circuits 40 or 4Z to which an enable signal En is supplied, the data in the other circuit 42 or 40 in the disable state are latched as it is and the circuit 42 or 40 functions as a cache memory. Consequently, when the RAM array is used in a computer, the RAM memory cell array whose access time is shortened is obtained.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD This invention relates to computer memory devices and, more particularly, to an apparatus for reducing the time required to access information in random access memory.

0002

BACKGROUND OF THE INVENTION In a typical conventional random access memory, memory devices are arranged in a matrix format with row address lines that select all memory devices in one particular row. . The values of the memory cells in the selected row are provided on bit lines to a column decoder which uses column address lines to select information from the requested cell. This column decoder can be omitted if all rows of random access memory are used.

The row and column decoder operations required to access random access memory consume a significant amount of computer system operating time. As random access memories become larger, the metal lines become longer and the resulting capacitive load increases. Therefore, it follows that the time to access random access memory increases with the size of the random access memory. Note that random access memory can be used to supply the processor with a register file. Random access memory is widely used as high speed cache memory. Of course, random access memory is an important component of main memory. Because of its wide range of uses, reducing the time required to access random access memory has become a primary challenge in computer systems.

0004

SUMMARY OF THE INVENTION It is an object of the present invention to increase the operating speed of computer systems. Another object of the invention is to reduce the time required to access information in random access memory.

[0005]

[Means for Solving the Problems] These objects of the present invention are as follows:
a matrix of memory cells and a row address circuit for selecting memory cells in a particular row of the matrix;
a first latch having a number of stages for storing signals from the cells in one row of the memory; a second latch having a number of stages for storing signals from cells in a row; and means for providing bit line signals in parallel to the inputs of the first and second latches; and selectively enabling each latch. and means for disabling and selecting signals at the outputs of the first and second latches.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS These and other objects and features of the invention will now be described with reference to the accompanying drawings. below,
Some portions of the detailed description are presented in terms of algorithms and symbolic representations of operations on data bits of a computer memory. These algorithmic representations are the techniques used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and also generally, conceived of as a coherent sequence of steps leading to a goal result. The steps are those requiring physical manipulations of physical quantities. Typically, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. These signals can be defined as bits, values, elements,
It has proven convenient principally for reasons of common usage to refer to things as symbols, letters, words, numbers, etc. It should be borne in mind, however, that these and similar terms, while relating to the appropriate physical quantities, are merely convenient labels given to these quantities.

Furthermore, the operations performed may be denoted by terms typically associated with intellectual operations performed by operators, such as addition or comparison. Such capabilities of the operator are often not required in the operations described herein that form part of the present invention. The operation is a machine operation. Useful machines implementing the operations of the present invention include general purpose digital computers or other similar devices. In any case, it must be remembered that there is a difference between the method of operating the computer and the calculation method itself. The present invention relates to apparatus and methods for operating a computer in processing electrical or other (e.g., mechanical, chemical) physical signals to generate other required physical signals.

FIG. 1 shows an example of a simplified random access memory 10 organized in a typical prior art arrangement. Random access memory 10 is
It includes 16 memory cells 12 connected for access at the intersections of each of the four rows and each of the four columns. Each row is accessed by a row decoder 14, each labeled in the figure to indicate the number of the particular row being accessed. Basically, the row decoder operates in response to a pair of input signals on lines 15, 16;
Row [3. ．． 0] is an AND gate.

Usually, the higher-order bits of the address (bit a[
3] and a[2]) are memory
It is used to activate a single row in the matrix by row decoder 14. For a read operation, each memory cell 12 in the selected row provides its value to its associated bit line 18. The value on each bit line 18 of the cells in the selected row is transferred by sense amplifier 19 to column decode circuit 20. The column decode circuit uses the low order bits a[1] and a[0] of the address on the column address lines to select the particular data being requested. The illustrated arrangement selects a single bit of data d[0]. In the special situation where access to all rows of memory 10 is required,
The column decoding circuit 20 can be omitted, in which case,
All bit line 18 signals are used.

Each time information stored in random access memory 10 is requested, random access memory 10 must be addressed using row address lines and column address lines. A relatively small random access memory 10 can be addressed very quickly, but as the memory becomes larger, the length of the address increases and the rows and bit lines
This would substantially increase the capacitive loading on those lines. This means that the time required for access becomes longer. Tests on certain circuits have shown that it takes 50% more time to access a random access memory that is four times larger than a basic size random access memory.

FIG. 2 shows an arrangement according to the invention in which the time required to access random access memory is considerably reduced. Random access memory 3
0 is arranged similarly to random access memory 10 of FIG. 1, with sixteen memory cells 32 each connected for access at the intersection of four rows and four columns. Each row is accessed by a row decoder 34, each labeled in the figure to indicate the number of the particular row being accessed.

The high order bits of the address (shown as bits a[3] and a[2]) are used by row decoder 34 to activate a single row in the memory matrix. For a read operation, each memory cell 32 in the selected row provides its value to its associated bit line 38. The values on all bit lines 38 of the cells of the selected row are transferred in parallel by a sense amplifier 39 to a pair of latches 40, 42 made up of high speed registers. Multiplexer 44 is used to select the output of latch 40 or 42 and forwards its value to column decode circuit 46. Column decode circuit 46 uses the low order bits a[1] and a[0] of the address on the column address lines to select the particular data being requested.

The operation of the inventive array in which circuits 40 and 42 are latches will now be described. As latches, these circuits transfer any signal present at the input terminal to the output terminal while the latch is supplied with an enable signal. If the enable signal is removed, this output will remain until the new enable signal clocks the new input value into the output terminal, even though the original enable signal has been removed. This means that enabled latches are substantially transparent to the output terminals of decode circuit 46, i.e. the values on the row lines pass through such latches to output decode circuit 46.
It simply means that it is transferred to. Therefore, one of the latches 40 or 42 is always enabled to transfer the output of the bit line for use by the random access memory as if it were operating without a latch in the output path. .

The other of latches 40 or 42, on the other hand, operates as a cache for storing particular lines that are scheduled to be reused by the system. Unless another enabling pulse is applied to the latch, the latch will
It continues to store and provide at its output the original information received on the last enable pulse. If a row of information in random access memory is to be reused, the fact that the information resides in the latch is a problem with external addressing mechanisms (e.g.
tag bits or comparators related to the information in that row)
and multiplexer 4
4 selects the latch that holds that information,
Since there is no need to go through random access memory 30, there are no delays due to row addressing and circuit capacitance. Furthermore, even if the information has already been transferred from the output of the latch, it remains at the output for reuse. In this way, the latch is a random access
Acts as a cache for all lines of memory. Therefore, enabling the latch determines what information the latch captures and whether the latch operates as a flow-through device.

To obtain an advanced level of caching and to make the random access memory 30 operate faster, many latches are used instead of the only two latches 40, 42 shown here. be able to. All such latches receive inputs from sense amplifiers 39 in parallel.

Although the present invention has been described based on examples, it will be obvious to those skilled in the art that the present invention can be modified in various ways without departing from the spirit of the invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a random access memory constructed according to a typical prior art.

FIG. 2 is a schematic diagram of a random access memory constructed in accordance with the present invention.

[Explanation of symbols]

10, 30 Random access memory 12, 32
Memory cells 14, 34 Row decoders 18, 38 Bit lines 19, 39 Sense amplifiers 20, 46 Column decode circuits 40, 42 Latch 44 Multiplexer

Claims (1)

[Claims] 1. A matrix of memory cells and a row address circuit for selecting memory cells in a particular row of the matrix; apparatus for providing a signal representative of the state of the memory cells in a selected row of the matrix; one of the memory cells connected to said device for providing a signal representative of the state of the memory cells in a selected row of the matrix;
a first latch having a number of stages for storing signals from cells in a row; connected to said device for providing signals representative of the state of the memory cells in a selected row of the matrix; a second latch having a number of stages for storing signals from cells of the cell; means for selectively enabling and disabling each latch; and means for selecting a signal at the output of the first or second latch. Random access memory featuring
array.